diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc
index a705ffda..1c35aaff 100644
--- a/search/MakeTimingModel.cc
+++ b/search/MakeTimingModel.cc
@@ -71,8 +71,10 @@ MakeTimingModel::makeTimingModel(const char *lib_name,
   makeCell(cell_name, filename);
   makePorts();
 
-  for (Clock *clk : *sdc_->clocks())
+  for (Clock *clk : *sdc_->clocks()) {
     sta_->setPropagatedClock(clk);
+    checkClock(clk);
+  }
 
   sta_->searchPreamble();
   graph_ = sta_->graph();
@@ -157,6 +159,17 @@ MakeTimingModel::makePorts()
   delete port_iter;
 }
 
+void
+MakeTimingModel::checkClock(Clock *clk)
+{
+  for (const Pin *pin : clk->leafPins()) {
+    if (!network_->isTopLevelPort(pin))
+      report_->warn(810, "clock %s pin %s is inside model block.",
+                    clk->name(),
+                    network_->pathName(pin));
+  }
+}
+
 ////////////////////////////////////////////////////////////////
 
 class MakeEndTimingArcs : public PathEndVisitor
diff --git a/search/MakeTimingModel.hh b/search/MakeTimingModel.hh
index d9627e6c..4468e5c4 100644
--- a/search/MakeTimingModel.hh
+++ b/search/MakeTimingModel.hh
@@ -59,6 +59,7 @@ private:
   void makeCell(const char *cell_name,
                  const char *filename);
   void makePorts();
+  void checkClock(Clock *clk);
   void findTimingFromInputs();
   void findClkedOutputPaths();
   void findOutputDelays(const RiseFall *input_rf,