diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc
index be0a3d89..561b7953 100644
--- a/dcalc/PrimaDelayCalc.cc
+++ b/dcalc/PrimaDelayCalc.cc
@@ -931,15 +931,18 @@ std::string
 PrimaDelayCalc::reportGateDelay(const Pin *drvr_pin,
                                 const TimingArc *arc,
                                 const Slew &in_slew,
-                                float,
-                                const Parasitic *,
-                                const LoadPinIndexMap &,
+                                float load_cap,
+                                const Parasitic *parasitic,
+                                const LoadPinIndexMap &load_pin_index_map,
                                 const Scene *scene,
                                 const MinMax *min_max,
                                 int digits)
 {
   GateTimingModel *model = arc->gateModel(scene, min_max);
   if (model) {
+    // Delay calc to find ceff.
+    gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic,
+              load_pin_index_map, scene, min_max);
     float in_slew1 = delayAsFloat(in_slew);
     float ceff = ceff_vth_[0];
     return model->reportGateDelay(pinPvt(drvr_pin, scene, min_max),
diff --git a/test/prima3.ok b/test/prima3.ok
index a4ac1d9c..cd2c8cac 100644
--- a/test/prima3.ok
+++ b/test/prima3.ok
@@ -31,3 +31,55 @@ Path Type: max
                  228.48   slack (MET)
 
 
+Library: asap7_small
+Cell: BUFx2_ASAP7_75t_R
+Arc sense: positive_unate
+Arc type: combinational
+A ^ -> Y ^
+P = 1.00 V = 0.70 T = 25.00
+------- input_net_transition = 59.28
+|       total_output_net_capacitance = 13.54
+|        11.52     23.04
+v      --------------------
+40.00 | 48.68     71.50
+80.00 | 56.23     79.10
+Table value = 56.33
+PVT scale factor = 1.00
+Delay = 56.33
+
+------- input_net_transition = 59.28
+|       total_output_net_capacitance = 13.54
+|        11.52     23.04
+v      --------------------
+40.00 | 53.99     104.08
+80.00 | 54.58     104.40
+Table value = 63.04
+PVT scale factor = 1.00
+Slew = 63.04
+
+.............................................
+
+A v -> Y v
+P = 1.00 V = 0.70 T = 25.00
+------- input_net_transition = 52.93
+|       total_output_net_capacitance = 12.09
+|        11.52     23.04
+v      --------------------
+40.00 | 48.42     67.20
+80.00 | 57.92     76.86
+Table value = 52.43
+PVT scale factor = 1.00
+Delay = 52.43
+
+------- input_net_transition = 52.93
+|       total_output_net_capacitance = 12.09
+|        11.52     23.04
+v      --------------------
+40.00 | 42.77     80.89
+80.00 | 43.84     81.48
+Table value = 45.00
+PVT scale factor = 1.00
+Slew = 45.00
+
+.............................................
+
diff --git a/test/prima3.tcl b/test/prima3.tcl
index b2e20eab..0b285c72 100644
--- a/test/prima3.tcl
+++ b/test/prima3.tcl
@@ -9,3 +9,4 @@ set_propagated_clock {clk1 clk2 clk3}
 read_spef reg1_asap7.spef
 sta::set_delay_calculator prima
 report_checks -fields {input_pins slew} -format full_clock
+report_dcalc -from u1/A -to u1/Y