From 616cb6234aafb8ef5bd4fee84d4d008636f64087 Mon Sep 17 00:00:00 2001 From: Jaehyun Kim Date: Mon, 6 Apr 2026 14:41:40 +0900 Subject: [PATCH] Fix report_checks -fields {nets} typo to {net} across test scripts The valid field name is "net" (singular) per search/Search.tcl. Using "nets" triggered Warning 168 (unknown field) silently in 29 test scripts. Fix the field name and regolden .ok files. Co-Authored-By: Claude Signed-off-by: Jaehyun Kim --- graph/test/graph_bidirect.ok | 5 ++++- graph/test/graph_bidirect.tcl | 2 +- graph/test/graph_delete_modify.ok | 5 ++++- graph/test/graph_delete_modify.tcl | 2 +- graph/test/graph_modify.ok | 14 +++++++++++-- graph/test/graph_modify.tcl | 4 ++-- graph/test/graph_operations.ok | 7 ++++++- graph/test/graph_operations.tcl | 2 +- network/test/network_advanced.ok | 4 +++- network/test/network_advanced.tcl | 2 +- network/test/network_bus_parse.ok | 6 +++++- network/test/network_bus_parse.tcl | 2 +- network/test/network_escaped_names.ok | 4 +++- network/test/network_escaped_names.tcl | 2 +- network/test/network_hierarchy.ok | 8 +++++++- network/test/network_hierarchy.tcl | 2 +- network/test/network_leaf_iter.ok | 8 +++++++- network/test/network_leaf_iter.tcl | 2 +- network/test/network_properties.ok | 4 +++- network/test/network_properties.tcl | 2 +- network/test/network_sdc_pattern_deep.ok | 8 +++++++- network/test/network_sdc_pattern_deep.tcl | 2 +- network/test/network_sdc_query.ok | 6 +++++- network/test/network_sdc_query.tcl | 2 +- network/test/network_sorting.ok | 8 ++++++-- network/test/network_sorting.tcl | 4 ++-- .../test/parasitics_annotation_query.ok | 8 ++++++-- .../test/parasitics_annotation_query.tcl | 4 ++-- parasitics/test/parasitics_coupling.ok | 4 +++- parasitics/test/parasitics_coupling.tcl | 2 +- parasitics/test/parasitics_coupling_reduce.ok | 4 +++- .../test/parasitics_coupling_reduce.tcl | 2 +- parasitics/test/parasitics_estimate_wirerc.ok | 4 +++- .../test/parasitics_estimate_wirerc.tcl | 2 +- parasitics/test/parasitics_gcd_spef.ok | 16 ++++++++++++++- parasitics/test/parasitics_gcd_spef.tcl | 2 +- parasitics/test/parasitics_pi_pole_residue.ok | 4 +++- .../test/parasitics_pi_pole_residue.tcl | 2 +- parasitics/test/parasitics_reduce_dcalc.ok | 4 +++- parasitics/test/parasitics_reduce_dcalc.tcl | 2 +- parasitics/test/parasitics_spef_namemap.ok | 4 +++- parasitics/test/parasitics_spef_namemap.tcl | 2 +- sdf/test/sdf_cond_pathpulse.ok | 6 +++++- sdf/test/sdf_cond_pathpulse.tcl | 2 +- sdf/test/sdf_device_cond.ok | 6 +++++- sdf/test/sdf_device_cond.tcl | 2 +- search/test/search_path_enum_deep.ok | 20 ++++++++++++++++++- search/test/search_path_enum_deep.tcl | 2 +- search/test/search_report_path_types.ok | 13 ++++++++---- search/test/search_report_path_types.tcl | 8 ++++---- verilog/test/verilog_const_concat.ok | 3 ++- verilog/test/verilog_const_concat.tcl | 2 +- verilog/test/verilog_error_paths.ok | 6 +++++- verilog/test/verilog_error_paths.tcl | 2 +- verilog/test/verilog_preproc_param.ok | 5 ++++- verilog/test/verilog_preproc_param.tcl | 2 +- verilog/test/verilog_supply_tristate.ok | 2 +- verilog/test/verilog_supply_tristate.tcl | 2 +- 58 files changed, 196 insertions(+), 70 deletions(-) diff --git a/graph/test/graph_bidirect.ok b/graph/test/graph_bidirect.ok index c6c91805..2d8940b7 100644 --- a/graph/test/graph_bidirect.ok +++ b/graph/test/graph_bidirect.ok @@ -68,7 +68,6 @@ No paths found. No paths found. No paths found. --- Test 3: report with fields --- -Warning 168: graph_bidirect.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -80,12 +79,16 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v d1 (in) + d1 (net) 0.10 0.00 0.00 v buf1/A (BUF_X1) 2 1.67 0.01 0.06 0.06 v buf1/Z (BUF_X1) + n1 (net) 0.01 0.00 0.06 v or1/A1 (OR2_X1) 2 1.96 0.01 0.05 0.10 v or1/ZN (OR2_X1) + n6 (net) 0.01 0.00 0.10 v and2/A2 (AND2_X1) 1 1.06 0.01 0.03 0.13 v and2/ZN (AND2_X1) + n9 (net) 0.01 0.00 0.13 v reg2/D (DFF_X1) 0.13 data arrival time diff --git a/graph/test/graph_bidirect.tcl b/graph/test/graph_bidirect.tcl index 52c911ff..a3dc640c 100644 --- a/graph/test/graph_bidirect.tcl +++ b/graph/test/graph_bidirect.tcl @@ -41,7 +41,7 @@ report_checks -from [get_ports d3] -to [get_ports q4] # Test 3: Fields that exercise graph delay/slew queries #--------------------------------------------------------------- puts "--- Test 3: report with fields ---" -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/graph/test/graph_delete_modify.ok b/graph/test/graph_delete_modify.ok index 40ef20c8..d6617f9e 100644 --- a/graph/test/graph_delete_modify.ok +++ b/graph/test/graph_delete_modify.ok @@ -58,7 +58,6 @@ Path Type: min 1.03 slack (MET) -Warning 168: graph_delete_modify.tcl line 1, unknown field nets. Startpoint: d2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -70,12 +69,16 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.88 0.10 0.00 1.00 v d2 (in) + d2 (net) 0.10 0.00 1.00 v buf2/A (BUF_X1) 2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1) + n2 (net) 0.01 0.00 1.06 v or1/A1 (OR2_X1) 2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1) + n6 (net) 0.01 0.00 1.11 v nand1/A2 (NAND2_X1) 1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1) + n7 (net) 0.01 0.00 1.12 ^ reg2/D (DFF_X1) 1.12 data arrival time diff --git a/graph/test/graph_delete_modify.tcl b/graph/test/graph_delete_modify.tcl index 7f4fb42e..b43fc647 100644 --- a/graph/test/graph_delete_modify.tcl +++ b/graph/test/graph_delete_modify.tcl @@ -26,7 +26,7 @@ report_checks report_checks -path_delay min -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 2: Add multiple instances and nets, then delete diff --git a/graph/test/graph_modify.ok b/graph/test/graph_modify.ok index 62ed0905..d1d2c152 100644 --- a/graph/test/graph_modify.ok +++ b/graph/test/graph_modify.ok @@ -2551,7 +2551,6 @@ A2 -> ZN combinational ^ -> ^ 0.02:0.02:0.09:0.09 v -> v 0.02:0.02:0.16:0.16 --- fields per corner --- -Warning 168: graph_modify.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk1) Endpoint: q3 (output port clocked by clk1) Path Group: clk1 @@ -2564,14 +2563,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.91 0.10 0.00 1.00 v d1 (in) + d1 (net) 0.10 0.00 1.00 v buf1/A (BUF_X1) 2 2.36 0.01 0.04 1.04 v buf1/Z (BUF_X1) + n1 (net) 0.01 0.00 1.04 v and1/A1 (AND2_X1) 1 1.60 0.00 0.02 1.06 v and1/ZN (AND2_X1) + n5 (net) 0.00 0.00 1.06 v nand1/A1 (NAND2_X1) 3 6.91 0.01 0.01 1.07 ^ nand1/ZN (NAND2_X1) + n7 (net) 0.01 0.00 1.07 ^ buf4/A (BUF_X4) 1 0.00 0.00 0.01 1.09 ^ buf4/Z (BUF_X4) + q3 (net) 0.00 0.00 1.09 ^ q3 (out) 1.09 data arrival time @@ -2599,6 +2603,7 @@ Fanout Cap Slew Delay Time Description 0.00 10.00 clock network delay (ideal) 0.00 0.00 10.00 ^ reg1/CK (DFF_X1) 1 1.16 0.00 0.05 10.05 ^ reg1/Q (DFF_X1) + n11 (net) 0.00 0.00 10.05 ^ reg3/D (DFF_X1) 10.05 data arrival time @@ -2615,7 +2620,6 @@ Fanout Cap Slew Delay Time Description 4.93 slack (MET) -Warning 168: graph_modify.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk1) Endpoint: q3 (output port clocked by clk1) Path Group: clk1 @@ -2628,14 +2632,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.84 0.10 0.00 1.00 v d1 (in) + d1 (net) 0.10 0.00 1.00 v buf1/A (BUF_X1) 2 2.20 0.02 0.14 1.14 v buf1/Z (BUF_X1) + n1 (net) 0.02 0.00 1.14 v and1/A1 (AND2_X1) 1 1.45 0.02 0.09 1.23 v and1/ZN (AND2_X1) + n5 (net) 0.02 0.00 1.23 v nand1/A1 (NAND2_X1) 3 6.52 0.07 0.09 1.32 ^ nand1/ZN (NAND2_X1) + n7 (net) 0.07 0.00 1.32 ^ buf4/A (BUF_X4) 1 0.00 0.01 0.07 1.38 ^ buf4/Z (BUF_X4) + q3 (net) 0.01 0.00 1.38 ^ q3 (out) 1.38 data arrival time @@ -2663,6 +2672,7 @@ Fanout Cap Slew Delay Time Description 0.00 10.00 clock network delay (ideal) 0.00 0.00 10.00 ^ reg1/CK (DFF_X1) 1 1.03 0.02 0.23 10.23 v reg1/Q (DFF_X1) + n11 (net) 0.02 0.00 10.23 v reg3/D (DFF_X1) 10.23 data arrival time diff --git a/graph/test/graph_modify.tcl b/graph/test/graph_modify.tcl index 4a318c58..142c6b88 100644 --- a/graph/test/graph_modify.tcl +++ b/graph/test/graph_modify.tcl @@ -228,9 +228,9 @@ report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN] # report_checks with fields per corner #--------------------------------------------------------------- puts "--- fields per corner ---" -report_checks -corner fast -fields {slew cap input_pins nets fanout} +report_checks -corner fast -fields {slew cap input_pins net fanout} -report_checks -corner slow -fields {slew cap input_pins nets fanout} +report_checks -corner slow -fields {slew cap input_pins net fanout} report_checks -corner fast -format full_clock diff --git a/graph/test/graph_operations.ok b/graph/test/graph_operations.ok index 6b017770..a84a82b7 100644 --- a/graph/test/graph_operations.ok +++ b/graph/test/graph_operations.ok @@ -1784,7 +1784,6 @@ Path Type: max --- report_checks options --- -Warning 168: graph_operations.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk1) Endpoint: q3 (output port clocked by clk1) Path Group: clk1 @@ -1796,14 +1795,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.88 0.10 0.00 1.00 v d1 (in) + d1 (net) 0.10 0.00 1.00 v buf1/A (BUF_X1) 2 2.29 0.01 0.06 1.06 v buf1/Z (BUF_X1) + n1 (net) 0.01 0.00 1.06 v and1/A1 (AND2_X1) 1 1.53 0.01 0.03 1.09 v and1/ZN (AND2_X1) + n5 (net) 0.01 0.00 1.09 v nand1/A1 (NAND2_X1) 3 6.80 0.02 0.03 1.11 ^ nand1/ZN (NAND2_X1) + n7 (net) 0.02 0.00 1.11 ^ buf4/A (BUF_X4) 1 0.00 0.00 0.02 1.13 ^ buf4/Z (BUF_X4) + q3 (net) 0.00 0.00 1.13 ^ q3 (out) 1.13 data arrival time @@ -1830,6 +1834,7 @@ Fanout Cap Slew Delay Time Description 0.00 10.00 clock network delay (ideal) 0.00 0.00 10.00 ^ reg1/CK (DFF_X1) 1 1.06 0.01 0.08 10.08 v reg1/Q (DFF_X1) + n11 (net) 0.01 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time diff --git a/graph/test/graph_operations.tcl b/graph/test/graph_operations.tcl index b3fee861..30823865 100644 --- a/graph/test/graph_operations.tcl +++ b/graph/test/graph_operations.tcl @@ -241,7 +241,7 @@ report_check_types -max_delay -min_delay -verbose # report_checks with various options #--------------------------------------------------------------- puts "--- report_checks options ---" -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/network/test/network_advanced.ok b/network/test/network_advanced.ok index 0c4b86d1..7c2b8780 100644 --- a/network/test/network_advanced.ok +++ b/network/test/network_advanced.ok @@ -210,7 +210,6 @@ Path Type: max No paths found. No paths found. -Warning 168: network_advanced.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -222,10 +221,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.00 0.00 0.00 v in1 (in) + in1 (net) 0.00 0.00 0.00 v buf1/A (BUF_X1) 1 0.87 0.00 0.02 0.02 v buf1/Z (BUF_X1) + n1 (net) 0.00 0.00 0.02 v and1/A1 (AND2_X1) 1 1.06 0.01 0.02 0.05 v and1/ZN (AND2_X1) + n2 (net) 0.01 0.00 0.05 v reg1/D (DFF_X1) 0.05 data arrival time diff --git a/network/test/network_advanced.tcl b/network/test/network_advanced.tcl index 378cebee..5d6d148b 100644 --- a/network/test/network_advanced.tcl +++ b/network/test/network_advanced.tcl @@ -204,5 +204,5 @@ report_checks -from [get_ports in1] -to [get_ports out1] report_checks -from [get_ports in2] -to [get_ports out1] # Report with various field combinations -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock_expanded diff --git a/network/test/network_bus_parse.ok b/network/test/network_bus_parse.ok index f4f9a4f2..2c2d6443 100644 --- a/network/test/network_bus_parse.ok +++ b/network/test/network_bus_parse.ok @@ -239,7 +239,6 @@ Path Type: min No paths found. -Warning 168: network_bus_parse.tcl line 1, unknown field nets. Startpoint: data_a[6] (input port clocked by clk) Endpoint: carry (output port clocked by clk) Path Group: clk @@ -251,14 +250,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.00 0.00 0.00 v data_a[6] (in) + data_a[6] (net) 0.00 0.00 0.00 v buf_a6/A (BUF_X1) 1 0.87 0.00 0.02 0.02 v buf_a6/Z (BUF_X1) + stage1[6] (net) 0.00 0.00 0.02 v and6/A1 (AND2_X1) 3 2.85 0.01 0.03 0.05 v and6/ZN (AND2_X1) + stage2[6] (net) 0.01 0.00 0.05 v or_carry/A2 (OR2_X1) 1 0.88 0.01 0.05 0.10 v or_carry/ZN (OR2_X1) + internal_carry (net) 0.01 0.00 0.10 v buf_carry/A (BUF_X1) 1 0.00 0.00 0.02 0.12 v buf_carry/Z (BUF_X1) + carry (net) 0.00 0.00 0.12 v carry (out) 0.12 data arrival time diff --git a/network/test/network_bus_parse.tcl b/network/test/network_bus_parse.tcl index ee658e7d..8f3b2b86 100644 --- a/network/test/network_bus_parse.tcl +++ b/network/test/network_bus_parse.tcl @@ -173,4 +173,4 @@ puts "--- timing analysis ---" report_checks report_checks -path_delay min report_checks -from [get_ports {data_a[0]}] -to [get_ports {result[0]}] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} diff --git a/network/test/network_escaped_names.ok b/network/test/network_escaped_names.ok index 82d1c906..7cc3e1be 100644 --- a/network/test/network_escaped_names.ok +++ b/network/test/network_escaped_names.ok @@ -361,7 +361,6 @@ Path Type: max 9.92 slack (MET) -Warning 168: network_escaped_names.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -373,10 +372,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v in1 (in) + in1 (net) 0.10 0.00 0.00 v buf1/A (BUF_X1) 1 0.87 0.01 0.06 0.06 v buf1/Z (BUF_X1) + n1 (net) 0.01 0.00 0.06 v and1/A1 (AND2_X1) 1 1.06 0.01 0.03 0.08 v and1/ZN (AND2_X1) + n2 (net) 0.01 0.00 0.08 v reg1/D (DFF_X1) 0.08 data arrival time diff --git a/network/test/network_escaped_names.tcl b/network/test/network_escaped_names.tcl index 1b986e0d..826820c4 100644 --- a/network/test/network_escaped_names.tcl +++ b/network/test/network_escaped_names.tcl @@ -225,7 +225,7 @@ report_checks -rise_to [get_ports out1] report_checks -fall_to [get_ports out1] # Various report formats -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock report_checks -format full_clock_expanded report_checks -digits 6 diff --git a/network/test/network_hierarchy.ok b/network/test/network_hierarchy.ok index 633802c6..22846e00 100644 --- a/network/test/network_hierarchy.ok +++ b/network/test/network_hierarchy.ok @@ -359,7 +359,6 @@ Path Type: max 9.89 slack (MET) -Warning 168: network_hierarchy.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -371,18 +370,25 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v in1 (in) + in1 (net) 0.10 0.00 0.00 v buf_in/A (BUF_X1) 1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1) + w1 (net) 0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1) + sub1/n1 (net) 0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1) 1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1) + w2 (net) 0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1) + sub2/n1 (net) 0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1) 2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1) + w3 (net) 0.01 0.00 0.16 v inv1/A (INV_X1) 1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1) + w4 (net) 0.01 0.00 0.17 ^ reg1/D (DFF_X1) 0.17 data arrival time diff --git a/network/test/network_hierarchy.tcl b/network/test/network_hierarchy.tcl index 7a269f2e..03f2f8f7 100644 --- a/network/test/network_hierarchy.tcl +++ b/network/test/network_hierarchy.tcl @@ -213,7 +213,7 @@ report_checks -from [get_ports in2] -to [get_ports out1] report_checks -from [get_ports in3] -to [get_ports out2] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/network/test/network_leaf_iter.ok b/network/test/network_leaf_iter.ok index 626622cc..f5553f37 100644 --- a/network/test/network_leaf_iter.ok +++ b/network/test/network_leaf_iter.ok @@ -193,7 +193,6 @@ Path Type: max 9.80 slack (MET) -Warning 168: network_leaf_iter.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -205,18 +204,25 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v in1 (in) + in1 (net) 0.10 0.00 0.00 v buf_in/A (BUF_X1) 1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1) + w1 (net) 0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1) + sub1/n1 (net) 0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1) 1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1) + w2 (net) 0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1) + sub2/n1 (net) 0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1) 2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1) + w3 (net) 0.01 0.00 0.16 v inv1/A (INV_X1) 1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1) + w4 (net) 0.01 0.00 0.17 ^ reg1/D (DFF_X1) 0.17 data arrival time diff --git a/network/test/network_leaf_iter.tcl b/network/test/network_leaf_iter.tcl index 64aa5f87..97494ada 100644 --- a/network/test/network_leaf_iter.tcl +++ b/network/test/network_leaf_iter.tcl @@ -214,7 +214,7 @@ report_checks -path_delay min report_checks -path_delay max # Detailed reports with various fields -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock report_checks -format full_clock_expanded diff --git a/network/test/network_properties.ok b/network/test/network_properties.ok index eed01fa5..a31ae764 100644 --- a/network/test/network_properties.ok +++ b/network/test/network_properties.ok @@ -242,7 +242,6 @@ Path Type: min -5.33 slack (VIOLATED) -Warning 168: network_properties.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -254,10 +253,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 0.58 6.09 45.31 45.31 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 6.09 0.00 45.31 ^ u1/A (BUFx2_ASAP7_75t_R) 1 0.57 5.15 11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 5.15 0.00 57.08 ^ u2/B (AND2x2_ASAP7_75t_R) 1 0.62 6.96 14.88 71.95 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 6.96 0.00 71.95 ^ r3/D (DFFHQx4_ASAP7_75t_R) 71.95 data arrival time diff --git a/network/test/network_properties.tcl b/network/test/network_properties.tcl index 5a079201..a31ba29b 100644 --- a/network/test/network_properties.tcl +++ b/network/test/network_properties.tcl @@ -190,4 +190,4 @@ puts "all_registers -output_pins: [llength $reg_output]" puts "--- timing analysis ---" report_checks report_checks -path_delay min -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} diff --git a/network/test/network_sdc_pattern_deep.ok b/network/test/network_sdc_pattern_deep.ok index d2d53709..31db1b74 100644 --- a/network/test/network_sdc_pattern_deep.ok +++ b/network/test/network_sdc_pattern_deep.ok @@ -216,7 +216,6 @@ Path Type: max 6.82 slack (MET) -Warning 168: network_sdc_pattern_deep.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk @@ -228,18 +227,25 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.88 0.10 0.00 1.00 v in1 (in) + in1 (net) 0.10 0.00 1.00 v buf_in/A (BUF_X1) 1 0.87 0.01 0.06 1.06 v buf_in/Z (BUF_X1) + w1 (net) 0.01 0.00 1.06 v sub1/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.03 1.08 v sub1/and_gate/ZN (AND2_X1) + sub1/n1 (net) 0.01 0.00 1.08 v sub1/buf_gate/A (BUF_X1) 1 0.87 0.00 0.02 1.11 v sub1/buf_gate/Z (BUF_X1) + w2 (net) 0.00 0.00 1.11 v sub2/and_gate/A1 (AND2_X1) 1 0.88 0.01 0.02 1.13 v sub2/and_gate/ZN (AND2_X1) + sub2/n1 (net) 0.01 0.00 1.13 v sub2/buf_gate/A (BUF_X1) 2 2.42 0.01 0.03 1.16 v sub2/buf_gate/Z (BUF_X1) + w3 (net) 0.01 0.00 1.16 v buf_out2/A (BUF_X1) 1 0.00 0.00 0.02 1.18 v buf_out2/Z (BUF_X1) + out2 (net) 0.00 0.00 1.18 v out2 (out) 1.18 data arrival time diff --git a/network/test/network_sdc_pattern_deep.tcl b/network/test/network_sdc_pattern_deep.tcl index 228b8c79..0875d488 100644 --- a/network/test/network_sdc_pattern_deep.tcl +++ b/network/test/network_sdc_pattern_deep.tcl @@ -150,7 +150,7 @@ report_checks -to [get_ports out1] report_checks -to [get_ports out2] # Fields -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/network/test/network_sdc_query.ok b/network/test/network_sdc_query.ok index b392496f..4c23f4e4 100644 --- a/network/test/network_sdc_query.ok +++ b/network/test/network_sdc_query.ok @@ -448,7 +448,6 @@ Path Type: max 9.88 slack (MET) -Warning 168: network_sdc_query.tcl line 1, unknown field nets. Startpoint: data_a[6] (input port clocked by clk) Endpoint: carry (output port clocked by clk) Path Group: clk @@ -460,14 +459,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v data_a[6] (in) + data_a[6] (net) 0.10 0.00 0.00 v buf_a6/A (BUF_X1) 1 0.87 0.01 0.06 0.06 v buf_a6/Z (BUF_X1) + stage1[6] (net) 0.01 0.00 0.06 v and6/A1 (AND2_X1) 3 2.85 0.01 0.03 0.09 v and6/ZN (AND2_X1) + stage2[6] (net) 0.01 0.00 0.09 v or_carry/A2 (OR2_X1) 1 0.88 0.01 0.05 0.13 v or_carry/ZN (OR2_X1) + internal_carry (net) 0.01 0.00 0.13 v buf_carry/A (BUF_X1) 1 0.00 0.00 0.02 0.16 v buf_carry/Z (BUF_X1) + carry (net) 0.00 0.00 0.16 v carry (out) 0.16 data arrival time diff --git a/network/test/network_sdc_query.tcl b/network/test/network_sdc_query.tcl index 65e7a9e6..83157b5d 100644 --- a/network/test/network_sdc_query.tcl +++ b/network/test/network_sdc_query.tcl @@ -279,7 +279,7 @@ report_checks -from [get_ports {data_a[7]}] -to [get_ports carry] report_checks -from [get_ports {data_b[6]}] -to [get_ports overflow] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -endpoint_count 5 diff --git a/network/test/network_sorting.ok b/network/test/network_sorting.ok index c369d500..3789c171 100644 --- a/network/test/network_sorting.ok +++ b/network/test/network_sorting.ok @@ -68,7 +68,6 @@ buf1 pins: 2 and1 pins: 3 reg1 pins: 6 --- timing report sorting --- -Warning 168: network_sorting.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -80,10 +79,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 10.00 0.00 0.00 v in1 (in) + in1 (net) 10.00 0.00 0.00 v buf1/A (BUF_X1) 1 0.87 0.32 2.03 2.03 v buf1/Z (BUF_X1) + n1 (net) 0.32 0.00 2.03 v and1/A1 (AND2_X1) 1 1.06 0.30 0.10 2.13 v and1/ZN (AND2_X1) + n2 (net) 0.30 0.00 2.13 v reg1/D (DFF_X1) 2.13 data arrival time @@ -100,7 +102,6 @@ Fanout Cap Slew Delay Time Description 7.74 slack (MET) -Warning 168: network_sorting.tcl line 1, unknown field nets. Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -112,10 +113,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 1 0.97 10.00 0.00 0.00 ^ in1 (in) + in1 (net) 10.00 0.00 0.00 ^ buf1/A (BUF_X1) 1 0.92 0.31 -0.18 -0.18 ^ buf1/Z (BUF_X1) + n1 (net) 0.31 0.00 -0.18 ^ and1/A1 (AND2_X1) 1 1.14 0.02 0.06 -0.12 ^ and1/ZN (AND2_X1) + n2 (net) 0.02 0.00 -0.12 ^ reg1/D (DFF_X1) -0.12 data arrival time diff --git a/network/test/network_sorting.tcl b/network/test/network_sorting.tcl index 129d4cee..9189a844 100644 --- a/network/test/network_sorting.tcl +++ b/network/test/network_sorting.tcl @@ -86,8 +86,8 @@ puts "reg1 pins: [llength $reg_pins]" # sorting in report paths #--------------------------------------------------------------- puts "--- timing report sorting ---" -report_checks -path_delay max -fields {slew cap input_pins nets fanout} -report_checks -path_delay min -fields {slew cap input_pins nets fanout} +report_checks -path_delay max -fields {slew cap input_pins net fanout} +report_checks -path_delay min -fields {slew cap input_pins net fanout} report_checks -sort_by_slack report_checks -group_path_count 5 diff --git a/parasitics/test/parasitics_annotation_query.ok b/parasitics/test/parasitics_annotation_query.ok index 05b495da..68f8c470 100644 --- a/parasitics/test/parasitics_annotation_query.ok +++ b/parasitics/test/parasitics_annotation_query.ok @@ -94,7 +94,6 @@ Path Type: min No paths found. No paths found. -Warning 168: parasitics_annotation_query.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -106,10 +105,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (propagated) 10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R) 1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R) 1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R) 75.04 data arrival time @@ -217,7 +219,6 @@ elmore u1/Y->u2/A after SPEF: 0.0 elmore r1/Q->u1/A after SPEF: 0.0 elmore r3/Q->out after SPEF: 1.6213998893510606e-11 --- Test 8: detailed reports --- -Warning 168: parasitics_annotation_query.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -229,10 +230,13 @@ Fanout Cap Slew Delay Time Description 12.11 12.11 clock network delay (propagated) 48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R) 1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R) 1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R) 201.72 data arrival time diff --git a/parasitics/test/parasitics_annotation_query.tcl b/parasitics/test/parasitics_annotation_query.tcl index cdc06241..4464287b 100644 --- a/parasitics/test/parasitics_annotation_query.tcl +++ b/parasitics/test/parasitics_annotation_query.tcl @@ -123,7 +123,7 @@ report_checks -from [get_ports in1] -to [get_ports out] report_checks -from [get_ports in2] -to [get_ports out] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 4: Report parasitic annotation @@ -206,7 +206,7 @@ puts "elmore r3/Q->out after SPEF: $elm_r3_spef" #--------------------------------------------------------------- puts "--- Test 8: detailed reports ---" -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/parasitics/test/parasitics_coupling.ok b/parasitics/test/parasitics_coupling.ok index 14dd6d6b..d73158ce 100644 --- a/parasitics/test/parasitics_coupling.ok +++ b/parasitics/test/parasitics_coupling.ok @@ -152,7 +152,6 @@ Path Type: max No paths found. No paths found. -Warning 168: parasitics_coupling.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -164,10 +163,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (propagated) 10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R) 1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R) 1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R) 75.04 data arrival time diff --git a/parasitics/test/parasitics_coupling.tcl b/parasitics/test/parasitics_coupling.tcl index 695dafb5..cb7d7789 100644 --- a/parasitics/test/parasitics_coupling.tcl +++ b/parasitics/test/parasitics_coupling.tcl @@ -92,7 +92,7 @@ report_checks -from [get_ports in1] -to [get_ports out] report_checks -from [get_ports in2] -to [get_ports out] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Report parasitic annotation diff --git a/parasitics/test/parasitics_coupling_reduce.ok b/parasitics/test/parasitics_coupling_reduce.ok index dfca9ae6..c9e0b0ab 100644 --- a/parasitics/test/parasitics_coupling_reduce.ok +++ b/parasitics/test/parasitics_coupling_reduce.ok @@ -72,7 +72,6 @@ Path Type: min -13.41 slack (VIOLATED) -Warning 168: parasitics_coupling_reduce.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -84,10 +83,13 @@ Fanout Cap Slew Delay Time Description 11.30 11.30 clock network delay (propagated) 45.81 0.00 11.30 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 13.58 23.96 64.33 75.63 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 37.80 9.52 85.14 ^ u1/A (BUFx2_ASAP7_75t_R) 1 13.07 43.97 33.69 118.83 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 57.40 12.42 131.25 ^ u2/B (AND2x2_ASAP7_75t_R) 1 13.12 52.35 44.67 175.92 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 64.37 12.82 188.74 ^ r3/D (DFFHQx4_ASAP7_75t_R) 188.74 data arrival time diff --git a/parasitics/test/parasitics_coupling_reduce.tcl b/parasitics/test/parasitics_coupling_reduce.tcl index 9862639d..898a6621 100644 --- a/parasitics/test/parasitics_coupling_reduce.tcl +++ b/parasitics/test/parasitics_coupling_reduce.tcl @@ -38,7 +38,7 @@ report_checks report_checks -path_delay min -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 2: DMP calculators with coupling caps diff --git a/parasitics/test/parasitics_estimate_wirerc.ok b/parasitics/test/parasitics_estimate_wirerc.ok index 7be33041..1686cd49 100644 --- a/parasitics/test/parasitics_estimate_wirerc.ok +++ b/parasitics/test/parasitics_estimate_wirerc.ok @@ -138,7 +138,6 @@ Path Type: max 419.17 slack (MET) -Warning 168: parasitics_estimate_wirerc.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -150,10 +149,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (propagated) 10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R) 1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R) 1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R) 75.04 data arrival time diff --git a/parasitics/test/parasitics_estimate_wirerc.tcl b/parasitics/test/parasitics_estimate_wirerc.tcl index 7afbfb07..073fb336 100644 --- a/parasitics/test/parasitics_estimate_wirerc.tcl +++ b/parasitics/test/parasitics_estimate_wirerc.tcl @@ -77,7 +77,7 @@ report_checks -path_delay min report_checks -path_delay max -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Try different delay calculators with these parasitics diff --git a/parasitics/test/parasitics_gcd_spef.ok b/parasitics/test/parasitics_gcd_spef.ok index 01ab1b72..0fa6b610 100644 --- a/parasitics/test/parasitics_gcd_spef.ok +++ b/parasitics/test/parasitics_gcd_spef.ok @@ -179,7 +179,6 @@ Path Type: max 0.06 slack (MET) -Warning 168: parasitics_gcd_spef.tcl line 1, unknown field nets. Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _418_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -191,34 +190,49 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4) 3 0.01 0.04 0.32 0.32 v _414_/Q (sky130_fd_sc_hd__dfxtp_4) + dpath.a_lt_b$in1[0] (net) 0.04 0.00 0.32 v _214_/B_N (sky130_fd_sc_hd__nor2b_4) 2 0.01 0.04 0.12 0.45 v _214_/Y (sky130_fd_sc_hd__nor2b_4) + _052_ (net) 0.04 0.00 0.45 v _215_/C (sky130_fd_sc_hd__maj3_2) 2 0.01 0.07 0.32 0.77 v _215_/X (sky130_fd_sc_hd__maj3_2) + _053_ (net) 0.07 0.00 0.77 v _216_/C (sky130_fd_sc_hd__maj3_2) 2 0.01 0.06 0.32 1.10 v _216_/X (sky130_fd_sc_hd__maj3_2) + _054_ (net) 0.06 0.00 1.10 v _217_/C (sky130_fd_sc_hd__maj3_2) 2 0.02 0.09 0.36 1.46 v _217_/X (sky130_fd_sc_hd__maj3_2) + _055_ (net) 0.09 0.00 1.46 v _218_/C (sky130_fd_sc_hd__maj3_2) 2 0.02 0.10 0.38 1.83 v _218_/X (sky130_fd_sc_hd__maj3_2) + _056_ (net) 0.10 0.00 1.84 v _219_/C (sky130_fd_sc_hd__maj3_2) 3 0.03 0.12 0.39 2.23 v _219_/X (sky130_fd_sc_hd__maj3_2) + _057_ (net) 0.12 0.00 2.23 v _222_/A2 (sky130_fd_sc_hd__o211ai_4) 3 0.02 0.23 0.25 2.48 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4) + _060_ (net) 0.23 0.00 2.48 ^ _225_/A3 (sky130_fd_sc_hd__a311oi_4) 4 0.02 0.14 0.16 2.63 v _225_/Y (sky130_fd_sc_hd__a311oi_4) + _063_ (net) 0.14 0.00 2.64 v _228_/A3 (sky130_fd_sc_hd__o311ai_4) 3 0.02 0.33 0.34 2.97 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4) + _066_ (net) 0.33 0.00 2.97 ^ _231_/A3 (sky130_fd_sc_hd__a311oi_4) 2 0.02 0.14 0.17 3.14 v _231_/Y (sky130_fd_sc_hd__a311oi_4) + _069_ (net) 0.14 0.00 3.15 v _292_/A3 (sky130_fd_sc_hd__o311a_2) 3 0.02 0.10 0.43 3.58 v _292_/X (sky130_fd_sc_hd__o311a_2) + _110_ (net) 0.10 0.00 3.58 v _295_/A3 (sky130_fd_sc_hd__o31ai_4) 11 0.08 0.88 0.72 4.30 ^ _295_/Y (sky130_fd_sc_hd__o31ai_4) + _113_ (net) 0.88 0.00 4.30 ^ split1/A (sky130_fd_sc_hd__buf_4) 10 0.07 0.20 0.36 4.66 ^ split1/X (sky130_fd_sc_hd__buf_4) + net1 (net) 0.20 0.00 4.66 ^ _316_/A2 (sky130_fd_sc_hd__a221oi_1) 1 0.00 0.13 0.11 4.78 v _316_/Y (sky130_fd_sc_hd__a221oi_1) + _007_ (net) 0.13 0.00 4.78 v _418_/D (sky130_fd_sc_hd__dfxtp_1) 4.78 data arrival time diff --git a/parasitics/test/parasitics_gcd_spef.tcl b/parasitics/test/parasitics_gcd_spef.tcl index b78cf631..66de7335 100644 --- a/parasitics/test/parasitics_gcd_spef.tcl +++ b/parasitics/test/parasitics_gcd_spef.tcl @@ -37,7 +37,7 @@ report_checks -path_delay min report_checks -path_delay max -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/parasitics/test/parasitics_pi_pole_residue.ok b/parasitics/test/parasitics_pi_pole_residue.ok index 61eefdaa..ca479a7e 100644 --- a/parasitics/test/parasitics_pi_pole_residue.ok +++ b/parasitics/test/parasitics_pi_pole_residue.ok @@ -67,7 +67,6 @@ Path Type: min No paths found. No paths found. -Warning 168: parasitics_pi_pole_residue.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -79,10 +78,13 @@ Fanout Cap Slew Delay Time Description 12.11 12.11 clock network delay (propagated) 48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 22.89 17.61 93.23 ^ u1/A (BUFx2_ASAP7_75t_R) 1 13.97 46.91 30.36 123.59 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 46.91 17.58 141.17 ^ u2/B (AND2x2_ASAP7_75t_R) 1 14.02 56.09 42.76 183.93 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 56.09 17.72 201.65 ^ r3/D (DFFHQx4_ASAP7_75t_R) 201.65 data arrival time diff --git a/parasitics/test/parasitics_pi_pole_residue.tcl b/parasitics/test/parasitics_pi_pole_residue.tcl index 390abf2e..188f8c4b 100644 --- a/parasitics/test/parasitics_pi_pole_residue.tcl +++ b/parasitics/test/parasitics_pi_pole_residue.tcl @@ -35,7 +35,7 @@ report_checks -from [get_ports in1] -to [get_ports out] report_checks -from [get_ports in2] -to [get_ports out] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 3: Delay calc reports with two-pole model diff --git a/parasitics/test/parasitics_reduce_dcalc.ok b/parasitics/test/parasitics_reduce_dcalc.ok index f03d9162..68cca2f9 100644 --- a/parasitics/test/parasitics_reduce_dcalc.ok +++ b/parasitics/test/parasitics_reduce_dcalc.ok @@ -125,7 +125,6 @@ Path Type: min No paths found. No paths found. -Warning 168: parasitics_reduce_dcalc.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -137,10 +136,13 @@ Fanout Cap Slew Delay Time Description 12.11 12.11 clock network delay (propagated) 48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R) 1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R) 1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R) 201.72 data arrival time diff --git a/parasitics/test/parasitics_reduce_dcalc.tcl b/parasitics/test/parasitics_reduce_dcalc.tcl index 7b485a20..1aac67ab 100644 --- a/parasitics/test/parasitics_reduce_dcalc.tcl +++ b/parasitics/test/parasitics_reduce_dcalc.tcl @@ -43,7 +43,7 @@ report_checks -from [get_ports in1] -to [get_ports out] report_checks -from [get_ports in2] -to [get_ports out] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} # Detailed dcalc report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max diff --git a/parasitics/test/parasitics_spef_namemap.ok b/parasitics/test/parasitics_spef_namemap.ok index 4145e250..25d17a0c 100644 --- a/parasitics/test/parasitics_spef_namemap.ok +++ b/parasitics/test/parasitics_spef_namemap.ok @@ -359,7 +359,6 @@ Path Type: max 301.74 slack (MET) -Warning 168: parasitics_spef_namemap.tcl line 1, unknown field nets. Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -371,10 +370,13 @@ Fanout Cap Slew Delay Time Description 12.11 12.11 clock network delay (propagated) 48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) 1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R) + r2q (net) 50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R) 1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R) + u1z (net) 66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R) 1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R) + u2z (net) 73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R) 201.72 data arrival time diff --git a/parasitics/test/parasitics_spef_namemap.tcl b/parasitics/test/parasitics_spef_namemap.tcl index a54f1c21..224b1adf 100644 --- a/parasitics/test/parasitics_spef_namemap.tcl +++ b/parasitics/test/parasitics_spef_namemap.tcl @@ -66,7 +66,7 @@ report_checks -path_delay min report_checks -path_delay max -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock_expanded diff --git a/sdf/test/sdf_cond_pathpulse.ok b/sdf/test/sdf_cond_pathpulse.ok index 2e94f71d..4068ae1a 100644 --- a/sdf/test/sdf_cond_pathpulse.ok +++ b/sdf/test/sdf_cond_pathpulse.ok @@ -289,7 +289,6 @@ Unannotated Arcs width reg2/CK -> reg2/CK --- Test 5: write SDF --- --- Test 6: detailed reports --- -Warning 168: sdf_cond_pathpulse.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -301,14 +300,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v d1 (in) + d1 (net) 0.10 0.00 0.00 v buf1/A (BUF_X1) 1 0.87 0.01 0.14 0.14 v buf1/Z (BUF_X1) + n1 (net) 0.01 0.03 0.17 v and1/A1 (AND2_X1) 1 0.90 0.01 0.13 0.30 v and1/ZN (AND2_X1) + n3 (net) 0.01 0.03 0.33 v or1/A2 (OR2_X1) 2 2.59 0.01 0.10 0.43 v or1/ZN (OR2_X1) + n4 (net) 0.01 0.03 0.46 v nand1/A1 (NAND2_X1) 1 1.14 0.02 0.10 0.56 ^ nand1/ZN (NAND2_X1) + n5 (net) 0.02 0.02 0.58 ^ reg2/D (DFF_X1) 0.58 data arrival time diff --git a/sdf/test/sdf_cond_pathpulse.tcl b/sdf/test/sdf_cond_pathpulse.tcl index 9bcfd50f..c36355f9 100644 --- a/sdf/test/sdf_cond_pathpulse.tcl +++ b/sdf/test/sdf_cond_pathpulse.tcl @@ -119,7 +119,7 @@ write_sdf -divider . $sdf_out4 #--------------------------------------------------------------- puts "--- Test 6: detailed reports ---" -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -digits 6 diff --git a/sdf/test/sdf_device_cond.ok b/sdf/test/sdf_device_cond.ok index 80133e63..b22fe363 100644 --- a/sdf/test/sdf_device_cond.ok +++ b/sdf/test/sdf_device_cond.ok @@ -320,7 +320,6 @@ cell hold arcs 3 3 0 ---------------------------------------------------------------- 6 6 0 --- Test 7: detailed reports --- -Warning 168: sdf_device_cond.tcl line 1, unknown field nets. Startpoint: d1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -332,14 +331,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 1 0.97 0.10 0.00 0.00 ^ d1 (in) + d1 (net) 0.10 0.00 0.00 ^ buf1/A (BUF_X1) 2 2.62 0.01 0.15 0.15 ^ buf1/Z (BUF_X1) + n1 (net) 0.01 0.03 0.18 ^ inv1/A (INV_X1) 1 0.79 0.00 0.09 0.27 v inv1/ZN (INV_X1) + n3 (net) 0.00 0.02 0.29 v or1/A1 (OR2_X1) 2 2.59 0.01 0.03 0.32 v or1/ZN (OR2_X1) + n5 (net) 0.01 0.03 0.35 v nand1/A1 (NAND2_X1) 1 1.14 0.02 0.10 0.45 ^ nand1/ZN (NAND2_X1) + n6 (net) 0.02 0.02 0.47 ^ reg2/D (DFF_X1) 0.47 data arrival time diff --git a/sdf/test/sdf_device_cond.tcl b/sdf/test/sdf_device_cond.tcl index 27c7b52f..402973b0 100644 --- a/sdf/test/sdf_device_cond.tcl +++ b/sdf/test/sdf_device_cond.tcl @@ -121,7 +121,7 @@ report_annotated_check -setup -hold # Test 7: Detailed path reports #--------------------------------------------------------------- puts "--- Test 7: detailed reports ---" -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} report_checks -format full_clock diff --git a/search/test/search_path_enum_deep.ok b/search/test/search_path_enum_deep.ok index 0767ec9f..c4bb688f 100644 --- a/search/test/search_path_enum_deep.ok +++ b/search/test/search_path_enum_deep.ok @@ -52,7 +52,6 @@ Sorted correctly: 0 Warning 502: search_path_enum_deep.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead. grouped epc 5: 14 --- report_checks epc 3 -fields --- -Warning 168: search_path_enum_deep.tcl line 1, unknown field nets. Warning 502: search_path_enum_deep.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead. Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) @@ -65,10 +64,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.89 0.00 0.00 1.00 v in2 (in) + in2 (net) 0.00 0.00 1.00 v and1/A2 (AND2_X1) 1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1) + n1 (net) 0.01 0.00 1.02 v buf1/A (BUF_X1) 1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1) + n2 (net) 0.01 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time @@ -96,10 +98,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.87 0.00 0.00 1.00 v in1 (in) + in1 (net) 0.00 0.00 1.00 v and1/A1 (AND2_X1) 1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1) + n1 (net) 0.01 0.00 1.02 v buf1/A (BUF_X1) 1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1) + n2 (net) 0.01 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time @@ -127,10 +132,13 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 1 0.97 0.00 0.00 1.00 ^ in2 (in) + in2 (net) 0.00 0.00 1.00 ^ and1/A2 (AND2_X1) 1 0.97 0.01 0.03 1.03 ^ and1/ZN (AND2_X1) + n1 (net) 0.01 0.00 1.03 ^ buf1/A (BUF_X1) 1 1.13 0.01 0.02 1.05 ^ buf1/Z (BUF_X1) + n2 (net) 0.01 0.00 1.05 ^ reg1/D (DFFR_X1) 1.05 data arrival time @@ -158,8 +166,10 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.10 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.12 ^ buf2/Z (BUF_X1) + out1 (net) 0.00 0.00 0.12 ^ out1 (out) 0.12 data arrival time @@ -186,8 +196,10 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg2/CK (DFFR_X1) 1 0.97 0.01 0.10 0.10 ^ reg2/Q (DFFR_X1) + n5 (net) 0.01 0.00 0.10 ^ buf3/A (BUF_X1) 1 0.00 0.00 0.02 0.11 ^ buf3/Z (BUF_X1) + out2 (net) 0.00 0.00 0.11 ^ out2 (out) 0.11 data arrival time @@ -214,8 +226,10 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.08 v buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.11 v buf2/Z (BUF_X1) + out1 (net) 0.00 0.00 0.11 v out1 (out) 0.11 data arrival time @@ -242,6 +256,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.00 0.00 0.50 ^ rst (in) + rst (net) 0.00 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time @@ -269,6 +284,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.00 0.00 0.50 ^ rst (in) + rst (net) 0.00 0.00 0.50 ^ reg2/RN (DFFR_X1) 0.50 data arrival time @@ -296,6 +312,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.10 ^ reg2/D (DFFR_X1) 0.10 data arrival time @@ -323,6 +340,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time diff --git a/search/test/search_path_enum_deep.tcl b/search/test/search_path_enum_deep.tcl index fee85497..586f290f 100644 --- a/search/test/search_path_enum_deep.tcl +++ b/search/test/search_path_enum_deep.tcl @@ -92,7 +92,7 @@ puts "grouped epc 5: [llength $paths_g]" # report_checks with endpoint_count (text output) ############################################################ puts "--- report_checks epc 3 -fields ---" -report_checks -path_delay max -endpoint_count 3 -fields {slew cap input_pins nets fanout} +report_checks -path_delay max -endpoint_count 3 -fields {slew cap input_pins net fanout} puts "--- report_checks epc 3 -format end ---" report_checks -path_delay max -endpoint_count 3 -format end diff --git a/search/test/search_report_path_types.ok b/search/test/search_report_path_types.ok index 41ba7d4a..f74d96cd 100644 --- a/search/test/search_report_path_types.ok +++ b/search/test/search_report_path_types.ok @@ -536,8 +536,7 @@ Path Type: max 7.88 slack (MET) ---- report_checks -fields nets --- -Warning 168: search_report_path_types.tcl line 1, unknown field nets. +--- report_checks -fields net --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous @@ -549,6 +548,7 @@ Path Type: max 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) + rst (net) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time @@ -576,7 +576,9 @@ Path Type: max 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) + n3 (net) 0.02 0.12 ^ buf2/Z (BUF_X1) + out1 (net) 0.00 0.12 ^ out1 (out) 0.12 data arrival time @@ -648,7 +650,6 @@ Fanout Delay Time Description --- report_checks -fields all --- -Warning 168: search_report_path_types.tcl line 1, unknown field nets. Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous @@ -660,6 +661,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.10 0.00 0.50 ^ rst (in) + rst (net) 0.10 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time @@ -687,8 +689,10 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.10 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.12 ^ buf2/Z (BUF_X1) + out1 (net) 0.00 0.00 0.12 ^ out1 (out) 0.12 data arrival time @@ -705,7 +709,6 @@ Fanout Cap Slew Delay Time Description --- report_checks min -fields all --- -Warning 168: search_report_path_types.tcl line 1, unknown field nets. Startpoint: rst (input port clocked by clk) Endpoint: reg1 (removal check against rising-edge clock clk) Path Group: asynchronous @@ -717,6 +720,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.10 0.00 0.50 ^ rst (in) + rst (net) 0.10 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time @@ -744,6 +748,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) + n3 (net) 0.01 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time diff --git a/search/test/search_report_path_types.tcl b/search/test/search_report_path_types.tcl index 9de8827f..7c7bc947 100644 --- a/search/test/search_report_path_types.tcl +++ b/search/test/search_report_path_types.tcl @@ -69,17 +69,17 @@ report_checks -path_delay max -fields {cap} puts "--- report_checks -fields input_pins ---" report_checks -path_delay max -fields {input_pins} -puts "--- report_checks -fields nets ---" -report_checks -path_delay max -fields {nets} +puts "--- report_checks -fields net ---" +report_checks -path_delay max -fields {net} puts "--- report_checks -fields fanout ---" report_checks -path_delay max -fields {fanout} puts "--- report_checks -fields all ---" -report_checks -path_delay max -fields {slew cap input_pins nets fanout} +report_checks -path_delay max -fields {slew cap input_pins net fanout} puts "--- report_checks min -fields all ---" -report_checks -path_delay min -fields {slew cap input_pins nets fanout} +report_checks -path_delay min -fields {slew cap input_pins net fanout} ############################################################ # report_checks with -digits diff --git a/verilog/test/verilog_const_concat.ok b/verilog/test/verilog_const_concat.ok index d71a9b6c..b8366ee5 100644 --- a/verilog/test/verilog_const_concat.ok +++ b/verilog/test/verilog_const_concat.ok @@ -69,7 +69,6 @@ Path Type: min No paths found. No paths found. -Warning 168: verilog_const_concat.tcl line 1, unknown field nets. Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -81,8 +80,10 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 2 2.34 10.00 0.00 0.00 v in2 (in) + in2 (net) 10.00 0.00 0.00 v or_const/A1 (OR2_X1) 1 1.06 0.33 2.85 2.85 v or_const/ZN (OR2_X1) + n2 (net) 0.33 0.00 2.85 v reg2/D (DFF_X1) 2.85 data arrival time diff --git a/verilog/test/verilog_const_concat.tcl b/verilog/test/verilog_const_concat.tcl index 9f14367f..c7cc180e 100644 --- a/verilog/test/verilog_const_concat.tcl +++ b/verilog/test/verilog_const_concat.tcl @@ -44,7 +44,7 @@ report_checks -from [get_ports in1] -to [get_ports out1] report_checks -from [get_ports in2] -to [get_ports out2] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 3: Write verilog diff --git a/verilog/test/verilog_error_paths.ok b/verilog/test/verilog_error_paths.ok index fb9266ba..964cb32a 100644 --- a/verilog/test/verilog_error_paths.ok +++ b/verilog/test/verilog_error_paths.ok @@ -106,7 +106,6 @@ No paths found. din[2]->dout[2]: done No paths found. din[3]->dout[3]: done -Warning 168: verilog_error_paths.tcl line 1, unknown field nets. Startpoint: din[1] (input port clocked by clk) Endpoint: reg_b0 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -118,14 +117,19 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.88 0.10 0.00 0.00 v din[1] (in) + din[1] (net) 0.10 0.00 0.00 v buf1/A (BUF_X1) 4 4.36 0.01 0.06 0.06 v buf1/Z (BUF_X1) + stage2[1] (net) 0.01 0.00 0.06 v sub1/and_inner/A1 (AND2_X1) 1 0.88 0.01 0.03 0.09 v sub1/and_inner/ZN (AND2_X1) + sub1/n1 (net) 0.01 0.00 0.09 v sub1/buf_inner/A (BUF_X1) 1 0.89 0.00 0.02 0.12 v sub1/buf_inner/Z (BUF_X1) + wide1[0] (net) 0.00 0.00 0.12 v and_b0/A2 (AND2_X1) 1 1.06 0.01 0.03 0.14 v and_b0/ZN (AND2_X1) + wide2[0] (net) 0.01 0.00 0.14 v reg_b0/D (DFF_X1) 0.14 data arrival time diff --git a/verilog/test/verilog_error_paths.tcl b/verilog/test/verilog_error_paths.tcl index 6f301eab..a7832349 100644 --- a/verilog/test/verilog_error_paths.tcl +++ b/verilog/test/verilog_error_paths.tcl @@ -86,7 +86,7 @@ foreach from_idx {0 1 2 3} { puts "din\[$from_idx\]->dout\[$from_idx\]: done" } -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 3: Fanin/fanout through hierarchy and assigns diff --git a/verilog/test/verilog_preproc_param.ok b/verilog/test/verilog_preproc_param.ok index cbc10019..36769eaa 100644 --- a/verilog/test/verilog_preproc_param.ok +++ b/verilog/test/verilog_preproc_param.ok @@ -65,7 +65,6 @@ Path Type: min No paths found. No paths found. No paths found. -Warning 168: verilog_preproc_param.tcl line 1, unknown field nets. Startpoint: d2 (input port clocked by clk) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -77,12 +76,16 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 1 0.89 0.10 0.00 0.00 v d2 (in) + d2 (net) 0.10 0.00 0.00 v ps1/g1/A2 (AND2_X1) 2 1.94 0.01 0.07 0.07 v ps1/g1/ZN (AND2_X1) + n1 (net) 0.01 0.00 0.07 v buf1/A (BUF_X1) 2 1.96 0.01 0.03 0.09 v buf1/Z (BUF_X1) + n4 (net) 0.01 0.00 0.09 v or1/A2 (OR2_X1) 1 1.06 0.01 0.05 0.14 v or1/ZN (OR2_X1) + n6 (net) 0.01 0.00 0.14 v reg3/D (DFF_X1) 0.14 data arrival time diff --git a/verilog/test/verilog_preproc_param.tcl b/verilog/test/verilog_preproc_param.tcl index 869bdbc6..c5811b69 100644 --- a/verilog/test/verilog_preproc_param.tcl +++ b/verilog/test/verilog_preproc_param.tcl @@ -53,7 +53,7 @@ report_checks -from [get_ports d3] -to [get_ports q2] report_checks -from [get_ports d1] -to [get_ports q3] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 3: Write verilog and verify diff --git a/verilog/test/verilog_supply_tristate.ok b/verilog/test/verilog_supply_tristate.ok index 3b164f8b..fc079533 100644 --- a/verilog/test/verilog_supply_tristate.ok +++ b/verilog/test/verilog_supply_tristate.ok @@ -101,7 +101,6 @@ Path Type: max No paths found. -Warning 168: verilog_supply_tristate.tcl line 1, unknown field nets. Startpoint: in3 (input port clocked by clk) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk @@ -113,6 +112,7 @@ Fanout Cap Slew Delay Time Description 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 2 2.61 10.00 0.00 0.00 v in3 (in) + in3 (net) 10.00 0.00 0.00 v reg3/D (DFF_X1) 0.00 data arrival time diff --git a/verilog/test/verilog_supply_tristate.tcl b/verilog/test/verilog_supply_tristate.tcl index 10951289..5c20bd17 100644 --- a/verilog/test/verilog_supply_tristate.tcl +++ b/verilog/test/verilog_supply_tristate.tcl @@ -71,7 +71,7 @@ report_checks -from [get_ports in3] -to [get_ports out3] report_checks -from [get_ports in3] -to [get_ports {outbus[0]}] -report_checks -fields {slew cap input_pins nets fanout} +report_checks -fields {slew cap input_pins net fanout} #--------------------------------------------------------------- # Test 3: report_net for assign-related nets