diff --git a/dcalc/CcsCeffDelayCalc.cc b/dcalc/CcsCeffDelayCalc.cc
index 45fe8fff..fbd331a4 100644
--- a/dcalc/CcsCeffDelayCalc.cc
+++ b/dcalc/CcsCeffDelayCalc.cc
@@ -104,7 +104,8 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin,
       vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_;
       vh_ = drvr_library->slewUpperThreshold(drvr_rf_) * vdd_;
 
-      drvr_cell->ensureVoltageWaveforms(dcalc_ap);
+      const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts();
+      drvr_cell->ensureVoltageWaveforms(dcalc_aps);
       in_slew_ = delayAsFloat(in_slew);
       output_waveforms_ = output_waveforms;
       ref_time_ = output_waveforms_->referenceTime(in_slew_);
diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc
index b16b6128..1c1f2b4e 100644
--- a/dcalc/PrimaDelayCalc.cc
+++ b/dcalc/PrimaDelayCalc.cc
@@ -206,6 +206,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
 
   bool failed = false;
   output_waveforms_.resize(drvr_count_);
+  const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts();
   for (size_t drvr_idx = 0; drvr_idx < drvr_count_; drvr_idx++) {
     ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
     GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(dcalc_ap);
@@ -226,7 +227,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
         drvr_library->supplyVoltage("VDD", vdd_, vdd_exists);
         if (!vdd_exists)
           report_->error(1720, "VDD not defined in library %s", drvr_library->name());
-        drvr_cell->ensureVoltageWaveforms(dcalc_ap);
+        drvr_cell->ensureVoltageWaveforms(dcalc_aps);
         if (drvr_idx == 0) {
           vth_ = drvr_library->outputThreshold(drvr_rf_) * vdd_;
           vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_;
diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh
index 68ac7a55..a4fab952 100644
--- a/include/sta/Liberty.hh
+++ b/include/sta/Liberty.hh
@@ -80,6 +80,7 @@ typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
 typedef Map<const char *, float, CharPtrLess> SupplyVoltageMap;
 typedef Map<const char *, LibertyPgPort*, CharPtrLess> LibertyPgPortMap;
 typedef Map<const char *, DriverWaveform*, CharPtrLess> DriverWaveformMap;
+typedef Vector<DcalcAnalysisPt*> DcalcAnalysisPtSeq;
 
 enum class ClockGateType { none, latch_posedge, latch_negedge, other };
 
@@ -532,7 +533,7 @@ public:
   // Check all liberty cells to make sure they exist
   // for all the defined corners.
   static void checkLibertyCorners();
-  void ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap);
+  void ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps);
 
 protected:
   void addPort(ConcretePort *port);
diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc
index 7c33b262..48e9b345 100644
--- a/liberty/Liberty.cc
+++ b/liberty/Liberty.cc
@@ -1933,7 +1933,7 @@ LibertyCell::latchCheckEnableEdge(TimingArcSet *check_set)
 }
 
 void
-LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap)
+LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps)
 {
   if (!have_voltage_waveforms_) {
     float vdd = 0.0;  // shutup gcc
@@ -1943,11 +1943,13 @@ LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap)
       criticalError(1120, "library missing vdd");
     for (TimingArcSet *arc_set : timingArcSets()) {
       for (TimingArc *arc : arc_set->arcs()) {
-        GateTableModel *model = arc->gateTableModel(dcalc_ap);
-        if (model) {
-          OutputWaveforms *output_waveforms = model->outputWaveforms();
-          if (output_waveforms)
-            output_waveforms->makeVoltageWaveforms(vdd);
+        for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) {
+          GateTableModel *model = arc->gateTableModel(dcalc_ap);
+          if (model) {
+            OutputWaveforms *output_waveforms = model->outputWaveforms();
+            if (output_waveforms)
+              output_waveforms->makeVoltageWaveforms(vdd);
+          }
         }
       }
     }
diff --git a/liberty/Liberty.i b/liberty/Liberty.i
index 8aa0d751..f6eeac35 100644
--- a/liberty/Liberty.i
+++ b/liberty/Liberty.i
@@ -289,9 +289,9 @@ timing_arc_sets()
 void
 ensure_voltage_waveforms()
 {
-  Corner *corner = Sta::sta()->cmdCorner();
-  DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
-  self->ensureVoltageWaveforms(dcalc_ap);
+  Corners *corners = Sta::sta()->corners();
+  const DcalcAnalysisPtSeq &dcalc_aps = corners->dcalcAnalysisPts();
+  self->ensureVoltageWaveforms(dcalc_aps);
 }
 
 } // LibertyCell methods