From 5e4ce2fd233977f705f2696f3e6096bf997c5e8c Mon Sep 17 00:00:00 2001
From: James Cherry <cherry@parallaxsw.com>
Date: Wed, 9 Jul 2025 11:50:36 -0700
Subject: [PATCH] replace_cell equiv funcs, diff arcs resolves #267

Signed-off-by: James Cherry <cherry@parallaxsw.com>
---
 include/sta/EquivCells.hh |  8 +++++++-
 liberty/EquivCells.cc     | 13 +++++++++++++
 search/Sta.cc             |  4 +++-
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/include/sta/EquivCells.hh b/include/sta/EquivCells.hh
index 2b201d2b..4a337b0c 100644
--- a/include/sta/EquivCells.hh
+++ b/include/sta/EquivCells.hh
@@ -57,11 +57,17 @@ protected:
 };
 
 // Predicate that is true when the ports, functions, sequentials and
-// timing arcs match.
+// functions or timing arcs match.
 bool
 equivCells(const LibertyCell *cell1,
 	   const LibertyCell *cell2);
 
+// Predicate that is true when the ports, functions, sequentials and
+// timing arcs match.
+bool
+equivCellsArcs(const LibertyCell *cell1,
+               const LibertyCell *cell2);
+
 // Predicate that is true when the ports match.
 bool
 equivCellPorts(const LibertyCell *cell1,
diff --git a/liberty/EquivCells.cc b/liberty/EquivCells.cc
index 84e57cc0..da960f9c 100644
--- a/liberty/EquivCells.cc
+++ b/liberty/EquivCells.cc
@@ -341,6 +341,19 @@ equivCells(const LibertyCell *cell1,
         || equivCellTimingArcSets(cell1, cell2));
 }
 
+bool
+equivCellsArcs(const LibertyCell *cell1,
+               const LibertyCell *cell2)
+{
+  return equivCellPorts(cell1, cell2)
+    && equivCellFuncs(cell1, cell2)
+    && equivCellPgPorts(cell1, cell2)
+    && equivCellSequentials(cell1, cell2)
+    && equivCellStatetables(cell1, cell2)
+    // Reqwuire timing arc equivalence if there are no functions.
+    && equivCellTimingArcSets(cell1, cell2);
+}
+
 static bool
 cellHasFuncs(const LibertyCell *cell)
 {
diff --git a/search/Sta.cc b/search/Sta.cc
index d88c5a07..d86434af 100644
--- a/search/Sta.cc
+++ b/search/Sta.cc
@@ -4089,7 +4089,9 @@ Sta::replaceCell(Instance *inst,
 {
   NetworkEdit *network = networkCmdEdit();
   LibertyCell *from_lib_cell = network->libertyCell(inst);
-  if (sta::equivCells(from_lib_cell, to_lib_cell)) {
+  if (sta::equivCellsArcs(from_lib_cell, to_lib_cell)) {
+    // Replace celll optimized for less disruption to graph
+    // when ports and timing arcs are equivalent.
     replaceEquivCellBefore(inst, to_lib_cell);
     network->replaceCell(inst, to_cell);
     replaceEquivCellAfter(inst);