diff --git a/Dockerfile b/Dockerfile
index d67b926f..43572a8f 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -1,5 +1,6 @@
 FROM centos:centos7 AS base-dependencies
-LABEL maintainer="Abdelrahman Hosny <abdelrahman_hosny@brown.edu>"
+LABEL author="James Cherry"
+LABEL maintainer="James Cherry <cherry@parallaxsw.com>"
 
 # Install dev and runtime dependencies
 RUN yum group install -y "Development Tools" \
diff --git a/Dockerfile.ubuntu_18.04 b/Dockerfile.ubuntu_18.04
new file mode 100644
index 00000000..82ee3ef0
--- /dev/null
+++ b/Dockerfile.ubuntu_18.04
@@ -0,0 +1,32 @@
+FROM ubuntu:18.04
+LABEL author="James Cherry"
+LABEL maintainer="James Cherry <cherry@parallaxsw.com>"
+
+# install basics
+ARG DEBIAN_FRONTEND=noninteractive
+RUN apt-get update && \
+    apt-get install -y wget apt-utils git cmake gcc tcl-dev swig bison flex
+
+# download CUDD
+RUN wget https://www.davidkebo.com/source/cudd_versions/cudd-3.0.0.tar.gz && \
+    tar -xvf cudd-3.0.0.tar.gz && \
+    rm cudd-3.0.0.tar.gz
+
+# install CUDD
+RUN cd cudd-3.0.0 && \
+    mkdir ../cudd && \
+    ./configure --prefix=$HOME/cudd && \
+    make && \
+    make install
+
+# copy files and install OpenSTA
+RUN mkdir OpenSTA
+COPY . OpenSTA
+RUN cd OpenSTA && \
+    mkdir build && \
+    cd build && \
+    cmake .. -DCUDD=$HOME/cudd && \
+    make
+
+# Run sta on entry
+ENTRYPOINT ["OpenSTA/app/sta"]
diff --git a/README.md b/README.md
index e3bee224..4d7cea0a 100644
--- a/README.md
+++ b/README.md
@@ -63,13 +63,13 @@ work, but these are the versions used for development.
 
 ```
          from   Ubuntu   Xcode
-                18.04.1  10.1
-cmake    3.9
-clang    9.1.0           10.0.0
+                18.04.1  11.3
+cmake    3.10.2 3.10.2   3.16.2
+clang    9.1.0           11.0.0
 gcc      3.3.2   7.3.0   
 tcl      8.2     8.6     8.6.6
-swig     1.3.28  3.0.12  3.0.12
-bison    1.35    3.0.4   2.3
+swig     1.3.28  3.0.12  4.0.1
+bison    1.35    3.0.4   3.5
 flex     2.5.4   2.6.4   2.5.35
 ```
 
diff --git a/tcl/Sdc.tcl b/tcl/Sdc.tcl
index 0f3b6887..cce5d13e 100644
--- a/tcl/Sdc.tcl
+++ b/tcl/Sdc.tcl
@@ -672,6 +672,7 @@ proc get_lib_pins { args } {
   
   set regexp [info exists flags(-regexp)]
   set nocase [info exists flags(-nocase)]
+  set quiet [info exists flags(-quiet)]
   # Copy backslashes that will be removed by foreach.
   set patterns [string map {\\ \\\\} [lindex $args 0]]
   # Parse library_name/cell_name/pattern.
@@ -697,22 +698,22 @@ proc get_lib_pins { args } {
 	    }
 	  }
 	  if { $ports == {} } {
-	    if {![info exists flags(-quiet)]} {
+	    if { !$quiet } {
 	      sta_warn "port '$port_pattern' not found."
 	    }
 	  }
 	} else {
-	  if {![info exists flags(-quiet)]} {
+	  if { !$quiet } {
 	    sta_warn "cell '$cell_name' not found."
 	  }
 	}
       } else {
-	if {![info exists flags(-quiet)]} {
+	if { !$quiet } {
 	  sta_warn "library '$lib_name' not found."
 	}
       }
     } else {
-      if {![info exists flags(-quiet)]} {
+      if { !$quiet } {
 	sta_warn "library/cell/port '$pattern' not found."
       }
     }
diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc
index b1dc4c2e..0f1eecb9 100644
--- a/verilog/VerilogReader.cc
+++ b/verilog/VerilogReader.cc
@@ -1830,20 +1830,20 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
 		verilogName(mod_inst));
   }
   if (cell) {
+    LibertyCell *lib_cell = network_->libertyCell(cell);
+    if (lib_cell)
+      cell = network_->cell(lib_cell);
     Instance *inst = network_->makeInstance(cell, mod_inst->instanceName(),
 					    parent);
-    bool is_leaf = network_->isLeaf(cell);
-    if (is_leaf) {
-      // Make all pins.
-      LibertyCell *lib_cell = network_->libertyCell(cell);
-      if (lib_cell) {
-	LibertyCellPortBitIterator port_iter(lib_cell);
-	while (port_iter.hasNext()) {
-	  LibertyPort *port = port_iter.next();
-	  network_->makePin(inst, reinterpret_cast<Port*>(port), nullptr);
-	}
+    if (lib_cell) {
+      // Make all pins so timing arcs are built.
+      LibertyCellPortBitIterator port_iter(lib_cell);
+      while (port_iter.hasNext()) {
+	LibertyPort *port = port_iter.next();
+	network_->makePin(inst, reinterpret_cast<Port*>(port), nullptr);
       }
     }
+    bool is_leaf = network_->isLeaf(cell);
     VerilogBindingTbl bindings(zero_net_name_, one_net_name_);
     if (mod_inst->hasPins()) {
       if (mod_inst->namedPins())