From 4da3eb909981998c039071703c3e80e43c9c175d Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 9 Oct 2023 19:28:18 -0700 Subject: [PATCH] write_timing_model seg fault Signed-off-by: James Cherry --- search/MakeTimingModel.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc index 734c80f7..b73c7b89 100644 --- a/search/MakeTimingModel.cc +++ b/search/MakeTimingModel.cc @@ -515,14 +515,14 @@ MakeTimingModel::findClkInsertionDelays() { Instance *top_inst = network_->topInstance(); Cell *top_cell = network_->cell(top_inst); - CellPortIterator *port_iter = network_->portIterator(top_cell); + CellPortIterator *port_iter = network_->portBitIterator(top_cell); while (port_iter->hasNext()) { Port *port = port_iter->next(); if (network_->direction(port)->isInput()) { const char *port_name = network_->name(port); LibertyPort *lib_port = cell_->findLibertyPort(port_name); Pin *pin = network_->findPin(top_inst, port); - if (sdc_->isClock(pin)) { + if (pin && sdc_->isClock(pin)) { lib_port->setIsClock(true); ClockSet *clks = sdc_->findClocks(pin); size_t clk_count = clks->size();