From 832c62b57952637b5f6959ca9a8c513524481723 Mon Sep 17 00:00:00 2001 From: Drew Lewis Date: Thu, 18 Jun 2026 16:52:14 -0400 Subject: [PATCH 01/35] Refactor DMP solver to use Eigen and implement Determinant Guarded solver (#450) This commit refactors the Dartu-Menezes-Pileggi (DMP) effective capacitance algorithm solver to use the Eigen library, and implements a Determinant Guarded solver to handle singular and near-singular Jacobians safely and efficiently. Key changes: 1. Refactored the DMP solver to use Eigen stack-based data structures, replacing the custom Crout LU decomposition and solver. 2. Extracted the linear solver logic into a dedicated helper function DmpAlg::solveNewtonStep. 3. Implemented a "Determinant Guarded" solver: - Manually checks the determinant of the Jacobian (safety guard). - Throws a DmpError if the determinant is dangerously close to zero (|det| < 1e-12), safely triggering the lumped capacitance fallback. - Otherwise, solves using Eigen's highly optimized analytical inverse (fast path). 4. Added documentation in the comments on how to easily swap back to LU decomposition with partial pivoting (PartialPivLU) if any numerical precision issues arise in the future. Benchmark Results (Optimized Release Build, 5,288 DMP calls): | Test Case | Calls | 1. Original (Crout LU) | 2. Eigen (PartialPivLU) | 3. Eigen (Determinant Guarded) | Speedup (3 vs 1) | Speedup (3 vs 2) | | :--- | :---: | :---: | :---: | :---: | :---: | :---: | | power | 2,608 | 1.8822 ms | 1.6791 ms | 1.2702 ms | +32.5% | +24.4% | | power_vcd | 2,608 | 1.8729 ms | 1.6704 ms | 1.2768 ms | +31.8% | +23.6% | | spef_parasitics | 24 | 0.0193 ms | 0.0187 ms | 0.0140 ms | +27.5% | +25.1% | | mcmm3 | 48 | 0.0728 ms | 0.0756 ms | 0.0817 ms | -12.2% | -8.1% | | Total DMP Time | 5,288 | 3.8472 ms | 3.4438 ms | 2.6427 ms | +31.3% | +23.3% | --- dcalc/DmpCeff.cc | 350 ++++++++++++++++++++++------------------------- dcalc/DmpCeff.hh | 46 ++++--- 2 files changed, 194 insertions(+), 202 deletions(-) diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index 5d0aef1d..6a37f348 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -31,6 +31,7 @@ // slew voltage is matched instead of y20 in eqn 12. #include "DmpCeff.hh" +#include #include #include @@ -137,20 +138,23 @@ DmpAlg::init(const LibertyLibrary *drvr_library, void DmpAlg::findDriverParams(double ceff) { + Eigen::Vector3d x = Eigen::Vector3d::Zero(); if (nr_order_ == 3) - x_[DmpParam::ceff] = ceff; + x[DmpParam::ceff] = ceff; auto [t_vth, t_vl, slew] = gateDelays(ceff); // Scale slew to 0-100% double dt = slew / (vh_ - vl_); double t0 = t_vth + std::log(1.0 - vth_) * rd_ * ceff - vth_ * dt; - x_[DmpParam::dt] = dt; - x_[DmpParam::t0] = t0; - newtonRaphson(); - t0_ = x_[DmpParam::t0]; - dt_ = x_[DmpParam::dt]; + x[DmpParam::dt] = dt; + x[DmpParam::t0] = t0; + newtonRaphson(x); + t0_ = x[DmpParam::t0]; + dt_ = x[DmpParam::dt]; + if (nr_order_ == 3) + ceff_ = x[DmpParam::ceff]; debugPrint(debug_, "dmp_ceff", 3, " t0 = {} dt = {} ceff = {}", units_->timeUnit()->asString(t0_), units_->timeUnit()->asString(dt_), - units_->capacitanceUnit()->asString(x_[DmpParam::ceff])); + units_->capacitanceUnit()->asString(ceff_)); if (debug_->check("dmp_ceff", 4)) showVo(); } @@ -241,21 +245,21 @@ DmpAlg::y0dcl(double t, } void -DmpAlg::showX() +DmpAlg::showX(const Eigen::Vector3d &x) { for (int i = 0; i < nr_order_; i++) - report_->report("{:4} {:12.3e}", dmp_param_index_strings[i], x_[i]); + report_->report("{:4} {:12.3e}", dmp_param_index_strings[i], x[i]); } void -DmpAlg::showFvec() +DmpAlg::showFvec(const Eigen::Vector3d &fvec) { for (int i = 0; i < nr_order_; i++) - report_->report("{:4} {:12.3e}", dmp_func_index_strings[i], fvec_[i]); + report_->report("{:4} {:12.3e}", dmp_func_index_strings[i], fvec[i]); } void -DmpAlg::showJacobian() +DmpAlg::showJacobian(const Eigen::Matrix3d &fjac) { std::string line = " "; for (int j = 0; j < nr_order_; j++) @@ -265,7 +269,7 @@ DmpAlg::showJacobian() line.clear(); line += sta::format("{:4} ", dmp_func_index_strings[i]); for (int j = 0; j < nr_order_; j++) - line += sta::format("{:12.3e} ", fjac_[i][j]); + line += sta::format("{:12.3e} ", fjac(i, j)); report_->reportLine(line); } } @@ -505,7 +509,9 @@ DmpCap::loadDelaySlew(const Pin *, } void -DmpCap::evalDmpEqns() +DmpCap::evalDmpEqns(Eigen::Vector3d &, + Eigen::Vector3d &, + Eigen::Matrix3d &) { } @@ -584,7 +590,6 @@ DmpPi::gateDelaySlew() double slew = 0.0; try { findDriverParamsPi(); - ceff_ = x_[DmpParam::ceff]; auto [table_delay, table_slew] = gateCapDelaySlew(ceff_); delay = table_delay; // slew = table_slew; @@ -623,60 +628,85 @@ DmpPi::findDriverParamsPi() // Given x_ as a vector of input parameters, fill fvec_ with the // equations evaluated at x_ and fjac_ with the jacobian evaluated at x_. void -DmpPi::evalDmpEqns() +DmpPi::evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) { - double t0 = x_[DmpParam::t0]; - double dt = x_[DmpParam::dt]; - double ceff = x_[DmpParam::ceff]; + const double t0 = x[DmpParam::t0]; + const double dt = x[DmpParam::dt]; + const double ceff = x[DmpParam::ceff]; - if (ceff < 0.0) + // Validate bounds to prevent mathematical domain errors. + if (ceff < 0.0) { throw DmpError("eqn eval failed: ceff < 0"); - if (ceff > (c1_ + c2_)) + } + if (ceff > (c1_ + c2_)) { throw DmpError("eqn eval failed: ceff > c2 + c1"); + } + if (dt <= 0.0) { + throw DmpError("eqn eval failed: dt < 0"); + } auto [t_vth, t_vl, slew] = gateDelays(ceff); - if (slew == 0.0) + if (slew == 0.0) { throw DmpError("eqn eval failed: slew = 0"); + } - double ceff_time = slew / (vh_ - vl_); - ceff_time = std::min(ceff_time, 1.4 * dt); + // ceff_time is bounded by 1.4 * dt. + const double ceff_time = std::min(slew / (vh_ - vl_), 1.4 * dt); - if (dt <= 0.0) - throw DmpError("eqn eval failed: dt < 0"); + // Pre-calculate exponential terms to avoid redundant calls to + // transcendental functions. + const double exp_p1_dt = exp2(-p1_ * dt); + const double exp_p2_dt = exp2(-p2_ * dt); + const double exp_dt_rd_ceff = exp2(-dt / (rd_ * ceff)); - double exp_p1_dt = exp2(-p1_ * dt); - double exp_p2_dt = exp2(-p2_ * dt); - double exp_dt_rd_ceff = exp2(-dt / (rd_ * ceff)); + // Evaluate function values (residuals). + const double y50 = y(t_vth, t0, dt, ceff).first; + const double y20 = y(t_vl, t0, dt, ceff).first; - double y50 = y(t_vth, t0, dt, ceff).first; - // Match Vl. - double y20 = y(t_vl, t0, dt, ceff).first; - fvec_[DmpFunc::ipi] = ipiIceff(t0, dt, ceff_time, ceff); - fvec_[DmpFunc::y50] = y50 - vth_; - fvec_[DmpFunc::y20] = y20 - vl_; - fjac_[DmpFunc::ipi][DmpParam::t0] = 0.0; - fjac_[DmpFunc::ipi][DmpParam::dt] = - (-A_ * dt + B_ * dt * exp_p1_dt - (2 * B_ / p1_) * (1.0 - exp_p1_dt) - + D_ * dt * exp_p2_dt - (2 * D_ / p2_) * (1.0 - exp_p2_dt) - + rd_ * ceff - * (dt + dt * exp_dt_rd_ceff - 2 * rd_ * ceff * (1.0 - exp_dt_rd_ceff))) - / (rd_ * dt * dt * dt); - fjac_[DmpFunc::ipi][DmpParam::ceff] = - (2 * rd_ * ceff - dt - (2 * rd_ * ceff + dt) * exp2(-dt / (rd_ * ceff))) - / (dt * dt); + fvec[DmpFunc::ipi] = ipiIceff(t0, dt, ceff_time, ceff); + fvec[DmpFunc::y50] = y50 - vth_; + fvec[DmpFunc::y20] = y20 - vl_; - std::tie(fjac_[DmpFunc::y20][DmpParam::t0], - fjac_[DmpFunc::y20][DmpParam::dt], - fjac_[DmpFunc::y20][DmpParam::ceff]) = dy(t_vl, t0, dt, ceff); + // Pre-calculate common sub-expressions for the Jacobian derivatives. + const double b_div_p1 = B_ / p1_; + const double d_div_p2 = D_ / p2_; + const double rd_ceff = rd_ * ceff; - std::tie(fjac_[DmpFunc::y50][DmpParam::t0], - fjac_[DmpFunc::y50][DmpParam::dt], - fjac_[DmpFunc::y50][DmpParam::ceff]) = dy(t_vth, t0, dt, ceff); + // Row 1 (Ipi derivatives). + fjac(DmpFunc::ipi, DmpParam::t0) = 0.0; + + // Derivative w.r.t dt (broken down into physical terms). + const double term_a = -A_ * dt; + const double term_b = + B_ * dt * exp_p1_dt - 2.0 * b_div_p1 * (1.0 - exp_p1_dt); + const double term_d = + D_ * dt * exp_p2_dt - 2.0 * d_div_p2 * (1.0 - exp_p2_dt); + const double term_rd = rd_ceff + * (dt + dt * exp_dt_rd_ceff - 2.0 * rd_ceff * (1.0 - exp_dt_rd_ceff)); + + fjac(DmpFunc::ipi, DmpParam::dt) = + (term_a + term_b + term_d + term_rd) / (rd_ * dt * dt * dt); + + // Derivative w.r.t ceff (reusing exp_dt_rd_ceff). + const double two_rd_ceff = 2.0 * rd_ceff; + fjac(DmpFunc::ipi, DmpParam::ceff) = + (two_rd_ceff - dt - (two_rd_ceff + dt) * exp_dt_rd_ceff) / (dt * dt); + + // Rows 2 & 3 (y20 and y50 derivatives). + std::tie(fjac(DmpFunc::y20, DmpParam::t0), + fjac(DmpFunc::y20, DmpParam::dt), + fjac(DmpFunc::y20, DmpParam::ceff)) = dy(t_vl, t0, dt, ceff); + + std::tie(fjac(DmpFunc::y50, DmpParam::t0), + fjac(DmpFunc::y50, DmpParam::dt), + fjac(DmpFunc::y50, DmpParam::ceff)) = dy(t_vth, t0, dt, ceff); if (debug_->check("dmp_ceff", 4)) { - showX(); - showFvec(); - showJacobian(); + showX(x); + showFvec(fvec); + showJacobian(fjac); report_->report("................."); } } @@ -741,35 +771,37 @@ DmpOnePole::DmpOnePole(StaState *sta) : } void -DmpOnePole::evalDmpEqns() +DmpOnePole::evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) { - double t0 = x_[DmpParam::t0]; - double dt = x_[DmpParam::dt]; + double t0 = x[DmpParam::t0]; + double dt = x[DmpParam::dt]; auto [t_vth, t_vl, ignore1] = gateDelays(ceff_); double ignore2; if (dt <= 0.0) - dt = x_[DmpParam::dt] = (t_vl - t_vth) / 100; + dt = x[DmpParam::dt] = (t_vl - t_vth) / 100; - fvec_[DmpFunc::y50] = y(t_vth, t0, dt, ceff_).first - vth_; - fvec_[DmpFunc::y20] = y(t_vl, t0, dt, ceff_).first - vl_; + fvec[DmpFunc::y50] = y(t_vth, t0, dt, ceff_).first - vth_; + fvec[DmpFunc::y20] = y(t_vl, t0, dt, ceff_).first - vl_; if (debug_->check("dmp_ceff", 4)) { - showX(); - showFvec(); + showX(x); + showFvec(fvec); } - std::tie(fjac_[DmpFunc::y20][DmpParam::t0], - fjac_[DmpFunc::y20][DmpParam::dt], + std::tie(fjac(DmpFunc::y20, DmpParam::t0), + fjac(DmpFunc::y20, DmpParam::dt), ignore2) = dy(t_vl, t0, dt, ceff_); - std::tie(fjac_[DmpFunc::y50][DmpParam::t0], - fjac_[DmpFunc::y50][DmpParam::dt], + std::tie(fjac(DmpFunc::y50, DmpParam::t0), + fjac(DmpFunc::y50, DmpParam::dt), ignore2) = dy(t_vth, t0, dt, ceff_); if (debug_->check("dmp_ceff", 4)) { - showJacobian(); + showJacobian(fjac); report_->report("................."); } } @@ -870,136 +902,86 @@ DmpZeroC2::voCrossingUpperBound() // driver_param_tol_ is the scale that all changes in x must be under (1.0 = 100%). // evalDmpEqns() fills fvec_ and fjac_. void -DmpAlg::newtonRaphson() +DmpAlg::newtonRaphson(Eigen::Vector3d &x) { - for (int k = 0; k < newton_raphson_max_iter_; k++) { - evalDmpEqns(); - for (int i = 0; i < nr_order_; i++) - // Right-hand side of linear equations. - p_[i] = -fvec_[i]; - luDecomp(); - luSolve(); + Eigen::Vector3d fvec = Eigen::Vector3d::Zero(); + Eigen::Matrix3d fjac = Eigen::Matrix3d::Zero(); + Eigen::Vector3d p = Eigen::Vector3d::Zero(); + + for (int k = 0; k < newton_raphson_max_iter_; k++) { + evalDmpEqns(x, fvec, fjac); + + p = solveNewtonStep(fjac, fvec); + + // Note: 'auto' on Eigen expressions captures the expression template + // and doesn't form a temporary vector/matrix, avoiding extra + // allocations. + auto p_abs = p.head(nr_order_).array().abs(); + auto x_tol = x.head(nr_order_).array().abs() * driver_param_tol_; + bool all_under_x_tol = (p_abs <= x_tol).all(); + x.head(nr_order_) += p.head(nr_order_); - bool all_under_x_tol = true; - for (int i = 0; i < nr_order_; i++) { - if (std::abs(p_[i]) > std::abs(x_[i]) * driver_param_tol_) - all_under_x_tol = false; - x_[i] += p_[i]; - } if (all_under_x_tol) { - evalDmpEqns(); return; } } throw DmpError("Newton-Raphson max iterations exceeded"); } -// luDecomp, luSolve based on MatClass from C. R. Birchenhall, -// University of Manchester -// ftp://ftp.mcc.ac.uk/pub/matclass/libmat.tar.Z - -// Crout's Method of LU decomposition of square matrix, with implicit -// partial pivoting. fjac_ is overwritten. U is explicit in the upper -// triangle and L is in multiplier form in the subdiagionals i.e. subdiag -// a[i,j] is the multiplier used to eliminate the [i,j] term. +// Solves the linear system J * p = -f (Jacobian * step = -residuals) for the Newton step. // -// Replaces fjac_[0..nr_order_-1][*] by the LU decomposition. -// index_[0..nr_order_-1] is an output vector of the row permutations. -void -DmpAlg::luDecomp() +// This implementation uses a "Determinant Guarded" solver: +// 1. Manually computes/checks the determinant of the Jacobian (safety guard). +// 2. If the determinant is dangerously close to zero (< 1e-12), throws a DmpError. +// 3. Otherwise, uses Eigen's highly optimized analytical inverse (fast path). +// +// Performance Note: +// Analytical solvers are extremely fast for 2x2 and 3x3 matrices because they +// contain no loops or branching, allowing the compiler to unroll them and use +// SIMD instructions. This yields a ~23% speedup over LU decomposition in optimized builds. +// +// Numerical Stability Note: +// If this analytical approach ever causes numerical issues (e.g., in extremely +// ill-conditioned systems where the determinant is > 1e-12 but still causes loss +// of precision), it can be TRIVIALLY swapped back to a robust LU decomposition +// with partial pivoting by replacing the body of this function with: +// +// Eigen::Vector3d p = Eigen::Vector3d::Zero(); +// if (nr_order_ == 2) { +// auto lu = fjac.topLeftCorner<2, 2>().partialPivLu(); +// if (std::abs(lu.matrixLU().diagonal().prod()) < 1e-12) { +// throw DmpError("Jacobian is singular (order 2)"); +// } +// p.head<2>() = lu.solve(-fvec.head<2>()); +// return p; +// } +// auto lu = fjac.partialPivLu(); +// if (std::abs(lu.matrixLU().diagonal().prod()) < 1e-12) { +// throw DmpError("Jacobian is singular (order 3)"); +// } +// p = lu.solve(-fvec); +// return p; +// +Eigen::Vector3d +DmpAlg::solveNewtonStep(const Eigen::Matrix3d &fjac, + const Eigen::Vector3d &fvec) { - const int size = nr_order_; + Eigen::Vector3d p = Eigen::Vector3d::Zero(); + if (nr_order_ == 2) { + double det = fjac.topLeftCorner<2, 2>().determinant(); + if (std::abs(det) < 1e-12) { + throw DmpError("Jacobian is singular (order 2)"); + } + p.head<2>() = fjac.topLeftCorner<2, 2>().inverse() * -fvec.head<2>(); + return p; + } - // Find implicit scaling factors. - for (int i = 0; i < size; i++) { - double big = 0.0; - for (int j = 0; j < size; j++) { - double temp = std::abs(fjac_[i][j]); - big = std::max(temp, big); - } - if (big == 0.0) - throw DmpError("LU decomposition: no non-zero row element"); - scale_[i] = 1.0 / big; - } - int size_1 = size - 1; - for (int j = 0; j < size; j++) { - // Run down jth column from top to diag, to form the elements of U. - for (int i = 0; i < j; i++) { - double sum = fjac_[i][j]; - for (int k = 0; k < i; k++) - sum -= fjac_[i][k] * fjac_[k][j]; - fjac_[i][j] = sum; - } - // Run down jth subdiag to form the residuals after the elimination - // of the first j-1 subdiags. These residuals diviyded by the - // appropriate diagonal term will become the multipliers in the - // elimination of the jth. subdiag. Find index of largest scaled - // term in imax. - double big = 0.0; - int imax = 0; - for (int i = j; i < size; i++) { - double sum = fjac_[i][j]; - for (int k = 0; k < j; k++) - sum -= fjac_[i][k] * fjac_[k][j]; - fjac_[i][j] = sum; - double dum = scale_[i] * std::abs(sum); - if (dum >= big) { - big = dum; - imax = i; - } - } - // Permute current row with imax. - if (j != imax) { - // Yes, do so... - for (int k = 0; k < size; k++) { - double dum = fjac_[imax][k]; - fjac_[imax][k] = fjac_[j][k]; - fjac_[j][k] = dum; - } - scale_[imax] = scale_[j]; - } - index_[j] = imax; - // If diag term is not zero divide subdiag to form multipliers. - if (fjac_[j][j] == 0.0) - fjac_[j][j] = tiny_double_; - if (j != size_1) { - double pivot = 1.0 / fjac_[j][j]; - for (int i = j + 1; i < size; i++) - fjac_[i][j] *= pivot; - } - } -} - -// Solves fjac_ * x = p_ for x, assuming fjac_ is LU form from luDecomp. -// Solution overwrites p_. -void -DmpAlg::luSolve() -{ - const int size = nr_order_; - - // Transform p_ allowing for leading zeros. - int non_zero = -1; - for (int i = 0; i < size; i++) { - int iperm = index_[i]; - double sum = p_[iperm]; - p_[iperm] = p_[i]; - if (non_zero != -1) { - for (int j = non_zero; j <= i - 1; j++) - sum -= fjac_[i][j] * p_[j]; - } - else { - if (sum != 0.0) - non_zero = i; - } - p_[i] = sum; - } - // Backsubstitution. - for (int i = size - 1; i >= 0; i--) { - double sum = p_[i]; - for (int j = i + 1; j < size; j++) - sum -= fjac_[i][j] * p_[j]; - p_[i] = sum / fjac_[i][i]; + double det = fjac.determinant(); + if (std::abs(det) < 1e-12) { + throw DmpError("Jacobian is singular (order 3)"); } + p = fjac.inverse() * -fvec; + return p; } //////////////////////////////////////////////////////////////// diff --git a/dcalc/DmpCeff.hh b/dcalc/DmpCeff.hh index a2e8a144..6db5f338 100644 --- a/dcalc/DmpCeff.hh +++ b/dcalc/DmpCeff.hh @@ -27,6 +27,9 @@ #include #include +#include +#include + #include "LibertyClass.hh" #include "LumpedCapDelayCalc.hh" @@ -59,18 +62,21 @@ public: double elmore); double ceff() { return ceff_; } - // Given x_ as a vector of input parameters, fill fvec_ with the - // equations evaluated at x_ and fjac_ with the jabobian evaluated at x_. - virtual void evalDmpEqns() = 0; + virtual void + evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) = 0; // Output response to vs(t) ramp driving pi model load (vo, dvo_dt). std::pair Vo(double t); // Load response to driver waveform (vl, dvl/dt). std::pair Vl(double t); protected: - void luDecomp(); - void luSolve(); - void newtonRaphson(); + void newtonRaphson(Eigen::Vector3d &x); + // Solves J * p = -f using a fast analytical solver with singularity checks. + // Can be easily swapped to LU with partial pivoting if needed. + Eigen::Vector3d solveNewtonStep(const Eigen::Matrix3d &fjac, + const Eigen::Vector3d &fvec); // Find driver parameters t0, delta_t, Ceff. void findDriverParams(double ceff); std::pair gateCapDelaySlew(double ceff); @@ -84,9 +90,9 @@ protected: double cl); double y0dcl(double t, double cl); - void showX(); - void showFvec(); - void showJacobian(); + void showX(const Eigen::Vector3d &x); + void showFvec(const Eigen::Vector3d &fvec); + void showJacobian(const Eigen::Matrix3d &fjac); std::pair findDriverDelaySlew(); double findVoCrossing(double vth, double t_lower, @@ -148,12 +154,7 @@ protected: static constexpr int max_nr_order_ = 3; - std::array x_; - std::array fvec_; - std::array, max_nr_order_> fjac_; - std::array scale_; - std::array p_; - std::array index_; + // Driver slew used to check load delay. double drvr_slew_; @@ -194,7 +195,10 @@ public: std::pair gateDelaySlew() override; std::pair loadDelaySlew(const Pin *, double elmore) override; - void evalDmpEqns() override; + void + evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) override; protected: double voCrossingUpperBound() override; @@ -219,7 +223,10 @@ public: double rpi, double c1) override; std::pair gateDelaySlew() override; - void evalDmpEqns() override; + void + evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) override; protected: double voCrossingUpperBound() override; @@ -255,7 +262,10 @@ class DmpOnePole : public DmpAlg { public: DmpOnePole(StaState *sta); - void evalDmpEqns() override; + void + evalDmpEqns(Eigen::Vector3d &x, + Eigen::Vector3d &fvec, + Eigen::Matrix3d &fjac) override; protected: double voCrossingUpperBound() override; From 9a11f094b9e499d6989cf66cd458ea9d3537e6e2 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 17 Jun 2026 18:27:48 -0700 Subject: [PATCH 02/35] typos/format Signed-off-by: James Cherry --- search/Latches.cc | 4 ++-- search/PathEnum.cc | 3 ++- search/Search.cc | 6 +++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/search/Latches.cc b/search/Latches.cc index f8d5b68e..73fc8929 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -359,7 +359,7 @@ Latches::latchOutArrival(const Path *data_path, arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, false, min_max, dcalc_ap, sdc); q_arrival = delaySum(data_path->arrival(), arc_delay, this); - // Copy the data tag but remove the drprClkPath. + // Copy the data tag but remove the crprClkPath. // Levelization does not traverse latch D->Q edges, so in some cases // level(Q) < level(D) // Note that @@ -368,7 +368,7 @@ Latches::latchOutArrival(const Path *data_path, // level(crprClkPath(data)) == level(Q) // or some other downstream vertex. // This can lead to data races when finding arrivals at the same level - // use multiple threads. + // with multiple threads. // Kill the crprClklPath to be safe. const ClkInfo *data_clk_info = data_path->clkInfo(this); const ClkInfo *q_clk_info = diff --git a/search/PathEnum.cc b/search/PathEnum.cc index 7c65f26e..7abd4a80 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -381,7 +381,8 @@ PathEnumFaninVisitor::visitEdge(const Pin *from_pin, Path *from_path = from_iter.next(); const Mode *mode = from_path->mode(this); const Sdc *sdc = mode->sdc(); - if (pred_->searchFrom(from_vertex, mode) && pred_->searchThru(edge, mode) + if (pred_->searchFrom(from_vertex, mode) + && pred_->searchThru(edge, mode) && pred_->searchTo(to_vertex, mode) // Fanin paths are broken by path delay internal pin startpoints. && !sdc->isPathDelayInternalFromBreak(to_pin)) { diff --git a/search/Search.cc b/search/Search.cc index 8e78f358..28277d3e 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -95,9 +95,9 @@ EvalPred::searchThru(Edge *edge, { const TimingRole *role = edge->role(); return SearchPred0::searchThru(edge, mode) - && (sta_->variables()->dynamicLoopBreaking() || !edge->isDisabledLoop()) - && (search_thru_latches_ || role->isLatchDtoQ() - || sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open); + && (sta_->variables()->dynamicLoopBreaking() || !edge->isDisabledLoop()) + && (search_thru_latches_ || role->isLatchDtoQ() + || sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open); } bool From 1b71a26667a1d252ed3586f13aa383774d2d97c5 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 17 Jun 2026 18:29:15 -0700 Subject: [PATCH 03/35] Levelize::isRoot bidirect leftover Signed-off-by: James Cherry --- search/Levelize.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/search/Levelize.cc b/search/Levelize.cc index baacfdb3..76788b40 100644 --- a/search/Levelize.cc +++ b/search/Levelize.cc @@ -187,9 +187,7 @@ Levelize::isRoot(Vertex *vertex) if (searchThru(edge)) return false; } - // Levelize bidirect driver as if it was a fanout of the bidirect load. - return !(graph_delay_calc_->bidirectDrvrSlewFromLoad(vertex->pin()) - && vertex->isBidirectDriver()); + return true; } bool From 0e79e35d17556c0adfe17e2b4b2addc21a734e4d Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 17 Jun 2026 18:29:59 -0700 Subject: [PATCH 04/35] indent Signed-off-by: James Cherry --- dcalc/GraphDelayCalc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index c61ebfed..6fac6faa 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -378,7 +378,7 @@ void GraphDelayCalc::seedInvalidDelays() { for (Vertex *vertex : invalid_delays_) - iter_->enqueue(vertex); + iter_->enqueue(vertex); invalid_delays_.clear(); } From 9e39e42703da2ffaa6d1b31f875fbfbf61f9e270 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 18 Jun 2026 13:38:47 -0700 Subject: [PATCH 05/35] comment Signed-off-by: James Cherry --- search/Search.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/search/Search.cc b/search/Search.cc index 28277d3e..22fe70b0 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -1388,9 +1388,9 @@ ArrivalVisitor::pruneCrprArrivals() } void -Search::enqueueLatchDataOutputs(Vertex *vertex) +Search::enqueueLatchDataOutputs(Vertex *latch_data) { - VertexOutEdgeIterator edge_iter(vertex, graph_); + VertexOutEdgeIterator edge_iter(latch_data, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role() == TimingRole::latchDtoQ()) { @@ -2068,9 +2068,8 @@ PathVisitor::visitFromPath(const Pin *from_pin, if (gclk) { Genclks *genclks = mode->genclks(); VertexSet *fanins = genclks->fanins(gclk); - // Note: encountering a latch d->q edge means find the - // latch feedback edges, but they are referenced for - // other edges in the gen clk fanout. + // Note: encountering a latch d->q edge means we need to find + // latch feedback edges. if (role == TimingRole::latchDtoQ()) genclks->findLatchFdbkEdges(gclk); EdgeSet &fdbk_edges = genclks->latchFdbkEdges(gclk); From 1c6ab172e2870bee72127e330c1380e79199a8b7 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 17 Jun 2026 19:54:36 -0700 Subject: [PATCH 06/35] eval latches out of bfs Signed-off-by: James Cherry --- include/sta/Search.hh | 6 +-- search/PathEnum.cc | 10 +++++ search/Search.cc | 92 +++++++++++++++++-------------------------- 3 files changed, 49 insertions(+), 59 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index d6db126e..364e6dfb 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -75,6 +75,8 @@ using ExceptionPathSeq = std::vector; class Search : public StaState { public: + bool postpone_latch_outputs_{false}; + Search(StaState *sta); ~Search() override; void copyState(const StaState *sta) override; @@ -530,9 +532,6 @@ protected: const MinMax *min_max) const; void seedRequireds(); void seedInvalidRequireds(); - [[nodiscard]] bool havePendingLatchOutputs(); - void clearPendingLatchOutputs(); - void enqueuePendingLatchOutputs(); void findFilteredArrivals(bool thru_latches); void findArrivalsSeed(); void seedFilterStarts(); @@ -669,7 +668,6 @@ protected: std::mutex filtered_arrivals_lock_; bool found_downstream_clk_pins_{false}; - bool postpone_latch_outputs_{false}; std::vector enum_paths_; VisitPathEnds *visit_path_ends_; diff --git a/search/PathEnum.cc b/search/PathEnum.cc index 7abd4a80..3be9e114 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -356,7 +356,9 @@ PathEnumFaninVisitor::visitFaninPathsThru(Path *before_div, prev_vertex_ = prev_vertex; visited_fanins_.clear(); unique_edge_divs_.clear(); + search_->postpone_latch_outputs_ = false; visitFaninPaths(before_div_->vertex(this)); + search_->postpone_latch_outputs_ = true; if (unique_edges_) { for (auto [vertex_edge, div] : unique_edge_divs_) @@ -422,6 +424,14 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *, Arrival & /* to_arrival */, const MinMax *) { + debugPrint(debug_, "path_enum", 3, "visit fanin {} -> {} {} {}", + from_path->to_string(this), + to_vertex->to_string(this), to_rf->shortName(), + delayAsString( + search_->deratedDelay( + from_vertex, arc, edge, false, from_path->minMax(this), + from_path->dcalcAnalysisPtIndex(this), from_path->sdc(this)), + this)); // These paths fanin to before_div_ so we know to_vertex matches. if ((!unique_pins_ || from_vertex != prev_vertex_) && (!unique_edges_ || from_vertex != prev_vertex_ diff --git a/search/Search.cc b/search/Search.cc index 22fe70b0..d943d3fc 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -326,7 +326,7 @@ Search::clear() deletePathGroups(); deletePaths(); deleteTags(); - clearPendingLatchOutputs(); + pending_latch_outputs_.clear(); pending_clk_endpoints_.clear(); deleteFilter(); found_downstream_clk_pins_ = false; @@ -644,18 +644,26 @@ Search::findFilteredArrivals(bool thru_latches) // Search always_to_endpoint to search from exisiting arrivals at // fanin startpoints to reach -thru/-to endpoints. arrival_visitor_->init(true, false, eval_pred_); - // Iterate until data arrivals at all latches stop changing. - postpone_latch_outputs_ = true; enqueuePendingClkFanouts(); - for (int pass = 1; pass == 1 || (thru_latches && havePendingLatchOutputs()); + postpone_latch_outputs_ = true; + bool have_pending_latch_outputs = false; + // Iterate until data arrivals at all latches stop changing. + for (int pass = 1; + pass == 1 || (thru_latches && have_pending_latch_outputs); pass++) { - if (thru_latches) - enqueuePendingLatchOutputs(); debugPrint(debug_, "search", 1, "find arrivals pass {}", pass); + int arrival_count = arrival_iter_->visitParallel(max_level, arrival_visitor_); - deleteTagsPrev(); debugPrint(debug_, "search", 1, "found {} arrivals", arrival_count); + + have_pending_latch_outputs = !pending_latch_outputs_.empty(); postpone_latch_outputs_ = false; + for (Vertex *latch_vertex : pending_latch_outputs_) + arrival_visitor_->visit(latch_vertex); + pending_latch_outputs_.clear(); + postpone_latch_outputs_ = true; + + deleteTagsPrev(); } arrivals_exist_ = true; } @@ -983,41 +991,23 @@ Search::findAllArrivals(bool thru_latches, if (!clks_only) enqueuePendingClkFanouts(); arrival_visitor_->init(false, clks_only, eval_pred_); - // Iterate until data arrivals at all latches stop changing. postpone_latch_outputs_ = true; - for (int pass = 1; pass == 1 || (thru_latches && havePendingLatchOutputs()); + bool have_pending_latch_outputs = false; + // Iterate until data arrivals at all latches stop changing. + for (int pass = 1; pass == 1 || (thru_latches && have_pending_latch_outputs); pass++) { - enqueuePendingLatchOutputs(); debugPrint(debug_, "search", 1, "find arrivals pass {}", pass); findArrivals1(levelize_->maxLevel()); - if (pass > 2) - postpone_latch_outputs_ = false; + + have_pending_latch_outputs = !pending_latch_outputs_.empty(); + postpone_latch_outputs_ = false; + for (Vertex *latch_vertex : pending_latch_outputs_) + arrival_visitor_->visit(latch_vertex); + pending_latch_outputs_.clear(); + postpone_latch_outputs_ = true; } } -bool -Search::havePendingLatchOutputs() -{ - return !pending_latch_outputs_.empty(); -} - -void -Search::clearPendingLatchOutputs() -{ - pending_latch_outputs_.clear(); -} - -void -Search::enqueuePendingLatchOutputs() -{ - for (Vertex *latch_vertex : pending_latch_outputs_) { - debugPrint(debug_, "search", 2, "enqueue latch output {}", - latch_vertex->to_string(this)); - arrival_iter_->enqueue(latch_vertex); - } - clearPendingLatchOutputs(); -} - void Search::enqueuePendingClkFanouts() { @@ -1148,6 +1138,17 @@ ArrivalVisitor::visit(Vertex *vertex) { debugPrint(debug_, "search", 2, "find arrivals {}", vertex->to_string(this)); + + if (search_->postponeLatchOutputs()) { + VertexInEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + if (edge->role()->isLatchDtoQ()) { + search_->enqueueLatchOutput(edge->to(graph_)); + return; + } + } + } Pin *pin = vertex->pin(); tag_bldr_->init(vertex); has_fanin_one_ = graph_->hasFaninOne(vertex); @@ -2139,26 +2140,7 @@ PathVisitor::visitFromPath(const Pin *from_pin, } else if (edge->role() == TimingRole::latchDtoQ()) { if (min_max == MinMax::max() && clk) { - bool postponed = false; - if (search_->postponeLatchOutputs()) { - const Path *from_clk_path = from_clk_info->crprClkPath(this); - if (from_clk_path) { - Vertex *d_clk_vertex = from_clk_path->vertex(this); - Level d_clk_level = d_clk_vertex->level(); - Level q_level = to_vertex->level(); - if (d_clk_level >= q_level) { - // Crpr clk path on latch data input is required to find Q - // arrival. If the data clk path level is >= Q level the - // crpr clk path prev_path pointers are not complete. - debugPrint(debug_, "search", 3, "postponed latch eval {} {} -> {} {}", - d_clk_level, d_clk_vertex->to_string(this), - edge->to_string(this), q_level); - postponed = true; - search_->enqueueLatchOutput(to_vertex); - } - } - } - if (!postponed) { + if (!search_->postponeLatchOutputs()) { arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, min_max, dcalc_ap, sdc); latches_->latchOutArrival(from_path, arc, edge, to_tag, arc_delay, From dea1ea2c133f2954b1b76f7eac084f94428ce1f3 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 17 Jun 2026 20:23:42 -0700 Subject: [PATCH 07/35] rm Search::postpone_latch_outputs_ Signed-off-by: James Cherry --- include/sta/Search.hh | 8 +++--- search/Genclks.cc | 2 +- search/PathEnum.cc | 4 +-- search/Search.cc | 67 ++++++++++++++++++++++--------------------- 4 files changed, 41 insertions(+), 40 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 364e6dfb..8122752e 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -75,8 +75,6 @@ using ExceptionPathSeq = std::vector; class Search : public StaState { public: - bool postpone_latch_outputs_{false}; - Search(StaState *sta); ~Search() override; void copyState(const StaState *sta) override; @@ -408,7 +406,6 @@ public: void checkPrevPaths() const; void deletePaths(Vertex *vertex); void deleteTagGroup(TagGroup *group); - bool postponeLatchOutputs() const { return postpone_latch_outputs_; } void saveEnumPath(Path *path); bool isSrchRoot(Vertex *vertex, const Mode *mode) const; @@ -710,7 +707,8 @@ public: bool make_tag_cache, const StaState *sta); ~PathVisitor() override; - virtual void visitFaninPaths(Vertex *to_vertex); + virtual void visitFaninPaths(Vertex *to_vertex, + bool with_latch_edges); virtual void visitFanoutPaths(Vertex *from_vertex); // Return false to stop visiting. virtual bool visitFromToPath(const Pin *from_pin, @@ -777,6 +775,8 @@ public: SearchPred *pred); void copyState(const StaState *sta) override; void visit(Vertex *vertex) override; + void visit(Vertex *vertex, + bool with_latch_edges); VertexVisitor *copy() const override; // Return false to stop visiting. bool visitFromToPath(const Pin *from_pin, diff --git a/search/Genclks.cc b/search/Genclks.cc index 851a601a..acf801b7 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -748,7 +748,7 @@ GenclkSrcArrivalVisitor::visit(Vertex *vertex) tag_bldr_->init(vertex); has_fanin_one_ = graph_->hasFaninOne(vertex); genclks_->copyGenClkSrcPaths(vertex, tag_bldr_); - visitFaninPaths(vertex); + visitFaninPaths(vertex, true); // Propagate beyond the clock tree to reach generated clk roots. insert_iter_->enqueueAdjacentVertices(vertex, &srch_pred_, mode_); search_->setVertexArrivals(vertex, tag_bldr_); diff --git a/search/PathEnum.cc b/search/PathEnum.cc index 3be9e114..e433c703 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -356,9 +356,7 @@ PathEnumFaninVisitor::visitFaninPathsThru(Path *before_div, prev_vertex_ = prev_vertex; visited_fanins_.clear(); unique_edge_divs_.clear(); - search_->postpone_latch_outputs_ = false; - visitFaninPaths(before_div_->vertex(this)); - search_->postpone_latch_outputs_ = true; + visitFaninPaths(before_div_->vertex(this), true); if (unique_edges_) { for (auto [vertex_edge, div] : unique_edge_divs_) diff --git a/search/Search.cc b/search/Search.cc index d943d3fc..08829669 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -645,7 +645,6 @@ Search::findFilteredArrivals(bool thru_latches) // fanin startpoints to reach -thru/-to endpoints. arrival_visitor_->init(true, false, eval_pred_); enqueuePendingClkFanouts(); - postpone_latch_outputs_ = true; bool have_pending_latch_outputs = false; // Iterate until data arrivals at all latches stop changing. for (int pass = 1; @@ -657,11 +656,9 @@ Search::findFilteredArrivals(bool thru_latches) debugPrint(debug_, "search", 1, "found {} arrivals", arrival_count); have_pending_latch_outputs = !pending_latch_outputs_.empty(); - postpone_latch_outputs_ = false; - for (Vertex *latch_vertex : pending_latch_outputs_) - arrival_visitor_->visit(latch_vertex); + for (Vertex *latch_output : pending_latch_outputs_) + arrival_visitor_->visit(latch_output, true); pending_latch_outputs_.clear(); - postpone_latch_outputs_ = true; deleteTagsPrev(); } @@ -991,20 +988,19 @@ Search::findAllArrivals(bool thru_latches, if (!clks_only) enqueuePendingClkFanouts(); arrival_visitor_->init(false, clks_only, eval_pred_); - postpone_latch_outputs_ = true; bool have_pending_latch_outputs = false; // Iterate until data arrivals at all latches stop changing. - for (int pass = 1; pass == 1 || (thru_latches && have_pending_latch_outputs); + for (int pass = 1; + pass == 1 || (thru_latches && have_pending_latch_outputs); pass++) { debugPrint(debug_, "search", 1, "find arrivals pass {}", pass); + findArrivals1(levelize_->maxLevel()); have_pending_latch_outputs = !pending_latch_outputs_.empty(); - postpone_latch_outputs_ = false; - for (Vertex *latch_vertex : pending_latch_outputs_) - arrival_visitor_->visit(latch_vertex); + for (Vertex *latch_output : pending_latch_outputs_) + arrival_visitor_->visit(latch_output, true); pending_latch_outputs_.clear(); - postpone_latch_outputs_ = true; } } @@ -1135,27 +1131,32 @@ ArrivalVisitor::setAlwaysToEndpoints(bool to_endpoints) void ArrivalVisitor::visit(Vertex *vertex) +{ + VertexInEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + if (edge->role()->isLatchDtoQ()) { + search_->enqueueLatchOutput(vertex); + return; + } + } + visit(vertex, false); +} + +void +ArrivalVisitor::visit(Vertex *vertex, + bool with_latch_edges) { debugPrint(debug_, "search", 2, "find arrivals {}", vertex->to_string(this)); - if (search_->postponeLatchOutputs()) { - VertexInEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->role()->isLatchDtoQ()) { - search_->enqueueLatchOutput(edge->to(graph_)); - return; - } - } - } Pin *pin = vertex->pin(); tag_bldr_->init(vertex); has_fanin_one_ = graph_->hasFaninOne(vertex); if (crpr_active_ && !has_fanin_one_) tag_bldr_no_crpr_->init(vertex); - visitFaninPaths(vertex); + visitFaninPaths(vertex, with_latch_edges); if (crpr_active_ && search_->crprPathPruningEnabled() // No crpr for ideal clocks. @@ -1949,12 +1950,16 @@ PathVisitor::~PathVisitor() } void -PathVisitor::visitFaninPaths(Vertex *to_vertex) +PathVisitor::visitFaninPaths(Vertex *to_vertex, + bool with_latch_edges) { VertexInEdgeIterator edge_iter(to_vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - if (!edge->role()->isTimingCheck()) { + const TimingRole *role = edge->role(); + if (!(role->isTimingCheck() + || (role == TimingRole::latchDtoQ() + && !with_latch_edges))) { Vertex *from_vertex = edge->from(graph_); const Pin *from_pin = from_vertex->pin(); const Pin *to_pin = to_vertex->pin(); @@ -2140,14 +2145,12 @@ PathVisitor::visitFromPath(const Pin *from_pin, } else if (edge->role() == TimingRole::latchDtoQ()) { if (min_max == MinMax::max() && clk) { - if (!search_->postponeLatchOutputs()) { - arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, min_max, - dcalc_ap, sdc); - latches_->latchOutArrival(from_path, arc, edge, to_tag, arc_delay, - to_arrival); - if (to_tag) - to_tag = search_->thruTag(to_tag, edge, to_rf, tag_cache_); - } + arc_delay = search_->deratedDelay(from_vertex, arc, edge, false, min_max, + dcalc_ap, sdc); + latches_->latchOutArrival(from_path, arc, edge, to_tag, arc_delay, + to_arrival); + if (to_tag) + to_tag = search_->thruTag(to_tag, edge, to_rf, tag_cache_); } } else if (from_tag->isClock()) { From 7a541edb708abf8194ef43398489521dd08227bb Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 18 Jun 2026 09:15:32 -0700 Subject: [PATCH 08/35] levelize rm latch d->q handling Signed-off-by: James Cherry --- search/Levelize.cc | 37 ------------------------------------- search/Levelize.hh | 2 -- 2 files changed, 39 deletions(-) diff --git a/search/Levelize.cc b/search/Levelize.cc index 76788b40..bc1b5609 100644 --- a/search/Levelize.cc +++ b/search/Levelize.cc @@ -134,7 +134,6 @@ Levelize::findLevels() findBackEdges(); VertexSeq topo_sorted = findTopologicalOrder(); assignLevels(topo_sorted); - ensureLatchLevels(); // Set level of stranded vertices (constants) to zero. VertexIterator vertex_iter2(graph_); @@ -354,8 +353,6 @@ Levelize::findTopologicalOrder() Vertex *to_vertex = edge->to(graph_); if (searchThru(edge)) in_degree[to_vertex] += 1; - if (edge->role() == TimingRole::latchDtoQ()) - latch_d_to_q_edges_.insert(edge); } // Levelize bidirect driver as if it was a fanout of the bidirect load. const Pin *pin = vertex->pin(); @@ -507,27 +504,6 @@ Levelize::assignLevels(VertexSeq &topo_sorted) //////////////////////////////////////////////////////////////// -// Make sure latch D input level is not the same as the Q level. -// This is because the Q arrival depends on the D arrival and -// to find them in parallel they have to be scheduled separately -// to avoid a race condition. -void -Levelize::ensureLatchLevels() -{ - for (Edge *edge : latch_d_to_q_edges_) { - Vertex *from = edge->from(graph_); - Vertex *to = edge->to(graph_); - if (from->level() == to->level()) { - Level adjusted_level = from->level() + level_space_; - debugPrint(debug_, "levelize", 2, "latch {} {} (adjusted {}) -> {} {}", - from->to_string(this), from->level(), adjusted_level, - to->to_string(this), to->level()); - setLevel(from, adjusted_level); - } - } - latch_d_to_q_edges_.clear(); -} - void Levelize::setLevel(Vertex *vertex, Level level) @@ -604,7 +580,6 @@ Levelize::relevelize() EdgeSeq path; visit(vertex, nullptr, vertex->level(), 1, path_vertices, path); } - ensureLatchLevels(); levels_valid_ = true; relevelize_from_.clear(); } @@ -635,18 +610,6 @@ Levelize::visit(Vertex *vertex, visit(to_vertex, edge, level + level_space, level_space, path_vertices, path); } - - const TimingRole *role = edge->role(); - if (role->isLatchDtoQ()) - latch_d_to_q_edges_.insert(edge); - if (role->isLatchEnToQ()) { - VertexInEdgeIterator edge_iter2(to_vertex, graph_); - while (edge_iter2.hasNext()) { - Edge *edge2 = edge_iter2.next(); - if (edge2->role()->isLatchDtoQ()) - latch_d_to_q_edges_.insert(edge2); - } - } } // Levelize bidirect driver as if it was a fanout of the bidirect load. diff --git a/search/Levelize.hh b/search/Levelize.hh index 094e3d47..22b268b8 100644 --- a/search/Levelize.hh +++ b/search/Levelize.hh @@ -83,7 +83,6 @@ protected: EdgeSeq &path); EdgeSeq *loopEdges(EdgeSeq &path, Edge *closing_edge); - void ensureLatchLevels(); void findBackEdges(); EdgeSet findBackEdges(EdgeSeq &path, FindBackEdgesStack &stack); @@ -113,7 +112,6 @@ protected: GraphLoopSeq loops_; EdgeSet loop_edges_; EdgeSet disabled_loop_edges_; - EdgeSet latch_d_to_q_edges_; LevelizeObserver *observer_{nullptr}; }; From 46d6ca9fc839f44fd65db4f24765d751e6c63066 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 18 Jun 2026 13:24:04 -0700 Subject: [PATCH 09/35] comment Signed-off-by: James Cherry --- search/Latches.cc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/search/Latches.cc b/search/Latches.cc index 73fc8929..5dcf6957 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -360,15 +360,6 @@ Latches::latchOutArrival(const Path *data_path, false, min_max, dcalc_ap, sdc); q_arrival = delaySum(data_path->arrival(), arc_delay, this); // Copy the data tag but remove the crprClkPath. - // Levelization does not traverse latch D->Q edges, so in some cases - // level(Q) < level(D) - // Note that - // level(crprClkPath(data)) < level(D) - // The danger is that - // level(crprClkPath(data)) == level(Q) - // or some other downstream vertex. - // This can lead to data races when finding arrivals at the same level - // with multiple threads. // Kill the crprClklPath to be safe. const ClkInfo *data_clk_info = data_path->clkInfo(this); const ClkInfo *q_clk_info = From 63361465e2b34b25a4d8048a5cce55d1c8186161 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 18 Jun 2026 14:08:43 -0700 Subject: [PATCH 10/35] ChangeLog typo Signed-off-by: James Cherry --- doc/ChangeLog.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/ChangeLog.txt b/doc/ChangeLog.txt index c30947f8..c456d0e0 100644 --- a/doc/ChangeLog.txt +++ b/doc/ChangeLog.txt @@ -55,7 +55,7 @@ link_design top create_clock -period 50 clk set_input_delay -clock clk 1 {in1 in2} set sta_pocv_mode skew_normal -report_checks -fields {slew variation input_pin variation} -digits 3 +report_checks -fields {slew variation input_pin} -digits 3 Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) From 7ca079f3f6421e41bab12d8db5218c13c2683404 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 18 Jun 2026 14:42:12 -0700 Subject: [PATCH 11/35] LibertyPort::setIsLatchOutput Signed-off-by: James Cherry --- include/sta/Liberty.hh | 3 +++ include/sta/Network.hh | 1 + liberty/Liberty.cc | 8 ++++++++ network/Network.cc | 10 ++++++++++ search/Search.cc | 13 ++++--------- 5 files changed, 26 insertions(+), 9 deletions(-) diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 461166a1..f34d5e8f 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -861,6 +861,8 @@ public: void setIsRegOutput(bool is_reg_out); bool isLatchData() const { return is_latch_data_; } void setIsLatchData(bool is_latch_data); + bool isLatchOutput() const { return is_latch_output_; } + void setIsLatchOutput(bool is_latch_output); // Is the clock for timing checks. bool isCheckClk() const { return is_check_clk_; } void setIsCheckClk(bool is_clk); @@ -956,6 +958,7 @@ protected: bool is_reg_clk_:1 {false}; bool is_reg_output_:1 {false}; bool is_latch_data_: 1 {false}; + bool is_latch_output_:1 {false}; bool is_check_clk_:1 {false}; bool is_clk_gate_clk_:1 {false}; bool is_clk_gate_enable_:1 {false}; diff --git a/include/sta/Network.hh b/include/sta/Network.hh index 9c45f095..d07b3db3 100644 --- a/include/sta/Network.hh +++ b/include/sta/Network.hh @@ -319,6 +319,7 @@ public: // Pin clocks a timing check. [[nodiscard]] bool isCheckClk(const Pin *pin) const; [[nodiscard]] bool isLatchData(const Pin *pin) const; + [[nodiscard]] bool isLatchOutput(const Pin *pin) const; // Iterate over all of the pins connected to a pin and the parent // and child nets it is hierarchically connected to (port, leaf and diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index b63e56fa..09c92678 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -1769,6 +1769,7 @@ LibertyCell::makeLatchEnable(LibertyPort *d, latch_d_to_q_map_[d_to_q] = idx; latch_check_map_[setup_check] = idx; d->setIsLatchData(true); + q->setIsLatchOutput(true); debugPrint(debug, "liberty_latch", 1, "latch {} -> {} | {} {} -> {} | {} {} -> {} setup", d->name(), @@ -2434,6 +2435,13 @@ LibertyPort::setIsLatchData(bool is_latch_data) setMemberFlag(is_latch_data, &LibertyPort::setIsLatchData); } +void +LibertyPort::setIsLatchOutput(bool is_latch_output) +{ + is_latch_output_ = is_latch_output; + setMemberFlag(is_latch_output, &LibertyPort::setIsLatchOutput); +} + void LibertyPort::setIsCheckClk(bool is_clk) { diff --git a/network/Network.cc b/network/Network.cc index 3bf22cf6..373d52b7 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -636,6 +636,16 @@ Network::isLatchData(const Pin *pin) const return false; } +bool +Network::isLatchOutput(const Pin *pin) const +{ + LibertyPort *port = libertyPort(pin); + if (port) + return port->isLatchOutput(); + else + return false; +} + //////////////////////////////////////////////////////////////// std::string diff --git a/search/Search.cc b/search/Search.cc index 08829669..ae23c681 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -1132,15 +1132,10 @@ ArrivalVisitor::setAlwaysToEndpoints(bool to_endpoints) void ArrivalVisitor::visit(Vertex *vertex) { - VertexInEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - if (edge->role()->isLatchDtoQ()) { - search_->enqueueLatchOutput(vertex); - return; - } - } - visit(vertex, false); + if (network_->isLatchOutput(vertex->pin())) + search_->enqueueLatchOutput(vertex); + else + visit(vertex, false); } void From 8d7babf44ef4dca11f478207a39273969fc32bd1 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 19 Jun 2026 10:49:10 +0800 Subject: [PATCH 12/35] Bump actions/checkout from 6 to 7 (#451) Signed-off-by: dependabot[bot] --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 65c53abb..d02e9616 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -9,7 +9,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: submodules: true From 4f0c4c8bb33054ffb63b45eb16d153356a91c4a2 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 20 Jun 2026 10:05:07 -0700 Subject: [PATCH 13/35] gated clk activity use passes instead of enqueue Signed-off-by: James Cherry --- power/Power.cc | 33 +++++++++++++++++++++++++++------ power/Power.hh | 2 ++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/power/Power.cc b/power/Power.cc index c5075522..0d7a4848 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -701,10 +701,8 @@ PropActivityVisitor::visit(Vertex *vertex) if (cell->isClockGate()) { const Pin *enable, *clk, *gclk; power_->clockGatePins(inst, enable, clk, gclk); - if (gclk) { - Vertex *gclk_vertex = graph_->pinDrvrVertex(gclk); - bfs_->enqueue(gclk_vertex); - } + if (gclk) + visited_regs_.insert(inst); } } bfs_->enqueueAdjacentVertices(vertex, mode_); @@ -972,6 +970,8 @@ Power::seedRegOutputActivities(const Instance *inst, const SequentialSeq &seqs = test_cell->sequentials(); seedRegOutputActivities(inst, test_cell, seqs, bfs); } + else if (cell->isClockGate()) + seedClkGateOutputActivities(inst, bfs); } } @@ -1045,6 +1045,23 @@ Power::seedRegOutputActivities(const Instance *reg, } } +void +Power::seedClkGateOutputActivities(const Instance *inst, + BfsFwdIterator &bfs) +{ + InstancePinIterator *pin_iter = network_->pinIterator(inst); + while (pin_iter->hasNext()) { + Pin *pin = pin_iter->next(); + LibertyPort *port = network_->libertyPort(pin); + if (port && port->isClockGateOut()) { + Vertex *vertex = graph_->pinDrvrVertex(pin); + if (vertex) + bfs.enqueue(vertex); + } + } + delete pin_iter; +} + //////////////////////////////////////////////////////////////// void @@ -1566,8 +1583,12 @@ Power::findActivity(const Pin *pin) if (activity && activity->origin() != PwrActivityOrigin::unknown) return *activity; const Clock *clk = findClk(pin); - float duty = clockDuty(clk); - return PwrActivity(2.0 / clk->period(), duty, PwrActivityOrigin::clock); + if (clk) { + float duty = clockDuty(clk); + return PwrActivity(2.0 / clk->period(), duty, PwrActivityOrigin::clock); + } + else + return PwrActivity(); } else if (global_activity_.isSet()) return global_activity_; diff --git a/power/Power.hh b/power/Power.hh index 8a19f309..ccffea64 100644 --- a/power/Power.hh +++ b/power/Power.hh @@ -224,6 +224,8 @@ protected: const LibertyCell *test_cell, const SequentialSeq &seqs, BfsFwdIterator &bfs); + void seedClkGateOutputActivities(const Instance *inst, + BfsFwdIterator &bfs); PwrActivity evalActivity(FuncExpr *expr, const Instance *inst); PwrActivity evalActivity(FuncExpr *expr, From 70e8f9f4735d2a8fbabdb5a609d2487cb8d26a25 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sun, 21 Jun 2026 20:55:57 -0700 Subject: [PATCH 14/35] genclks use queue instead of bfs Signed-off-by: James Cherry --- search/Genclks.cc | 68 ++++++++++++++++++++++++++++++----------------- search/Genclks.hh | 14 +++++++--- 2 files changed, 55 insertions(+), 27 deletions(-) diff --git a/search/Genclks.cc b/search/Genclks.cc index acf801b7..5e71b207 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -457,11 +457,11 @@ Genclks::findInsertionDelays(Clock *gclk) debugPrint(debug_, "genclk", 2, "find gen clk {} insertion", gclk->name()); GenclkInfo *genclk_info = makeGenclkInfo(gclk); FilterPath *src_filter = genclk_info->srcFilter(); + VertexQueue insert_queue; GenClkInsertionSearchPred srch_pred(gclk, genclk_info, this); - BfsFwdIterator insert_iter(BfsIndex::other, &srch_pred, this); - seedSrcPins(gclk, src_filter, insert_iter); + seedSrcPins(gclk, src_filter, insert_queue, srch_pred); // Propagate arrivals to generated clk root pin level. - findSrcArrivals(gclk, insert_iter, genclk_info); + findSrcArrivals(gclk, genclk_info, insert_queue); // Unregister the filter so that it is not triggered by other searches. // The exception itself has to stick around because the source path // tags reference it. @@ -591,7 +591,8 @@ Genclks::makeSrcFilter(Clock *gclk, void Genclks::seedSrcPins(Clock *gclk, FilterPath *src_filter, - BfsFwdIterator &insert_iter) + VertexQueue &insert_queue, + SearchPred &srch_pred) { Clock *master_clk = gclk->masterClk(); for (const Pin *master_pin : master_clk->leafPins()) { @@ -613,13 +614,28 @@ Genclks::seedSrcPins(Clock *gclk, tag_bldr.setArrival(tag, insert); } } - search_->setVertexArrivals(vertex, &tag_bldr); - insert_iter.enqueueAdjacentVertices(vertex, mode_); } + search_->setVertexArrivals(vertex, &tag_bldr); + enqueueFanout(vertex, insert_queue, srch_pred); } } } +void +Genclks::enqueueFanout(Vertex *vertex, + VertexQueue &insert_queue, + SearchPred &srch_pred) +{ + VertexOutEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *to_vertex = edge->to(graph_); + if (srch_pred.searchThru(edge, mode_) + && srch_pred.searchTo(to_vertex, mode_)) + insert_queue.push(to_vertex); + } +} + Tag * Genclks::makeTag(const Clock *gclk, const Clock *master_clk, @@ -690,8 +706,8 @@ class GenclkSrcArrivalVisitor : public ArrivalVisitor { public: GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, GenclkInfo *genclk_info, + VertexQueue &insert_queue, const Mode *mode); GenclkSrcArrivalVisitor(const GenclkSrcArrivalVisitor &visitor); VertexVisitor *copy() const override; @@ -699,7 +715,7 @@ public: protected: Clock *gclk_; - BfsFwdIterator *insert_iter_; + VertexQueue &insert_queue_; GenclkInfo *genclk_info_; GenClkInsertionSearchPred srch_pred_; const Mode *mode_; @@ -708,12 +724,12 @@ protected: }; GenclkSrcArrivalVisitor::GenclkSrcArrivalVisitor(Clock *gclk, - BfsFwdIterator *insert_iter, GenclkInfo *genclk_info, + VertexQueue &insert_queue, const Mode *mode) : ArrivalVisitor(mode->sta()), gclk_(gclk), - insert_iter_(insert_iter), + insert_queue_(insert_queue), genclk_info_(genclk_info), srch_pred_(gclk_, genclk_info, mode->sta()), mode_(mode), @@ -725,7 +741,7 @@ GenclkSrcArrivalVisitor::GenclkSrcArrivalVisitor(Clock *gclk, GenclkSrcArrivalVisitor::GenclkSrcArrivalVisitor(const GenclkSrcArrivalVisitor &visitor) : ArrivalVisitor(visitor), gclk_(visitor.gclk_), - insert_iter_(visitor.insert_iter_), + insert_queue_(visitor.insert_queue_), genclk_info_(visitor.genclk_info_), srch_pred_(visitor.gclk_, visitor.genclk_info_, this), mode_(visitor.mode_), @@ -749,23 +765,27 @@ GenclkSrcArrivalVisitor::visit(Vertex *vertex) has_fanin_one_ = graph_->hasFaninOne(vertex); genclks_->copyGenClkSrcPaths(vertex, tag_bldr_); visitFaninPaths(vertex, true); - // Propagate beyond the clock tree to reach generated clk roots. - insert_iter_->enqueueAdjacentVertices(vertex, &srch_pred_, mode_); search_->setVertexArrivals(vertex, tag_bldr_); + // Propagate beyond the clock tree to reach generated clk roots. + genclks_->enqueueFanout(vertex, insert_queue_, srch_pred_); } void Genclks::findSrcArrivals(Clock *gclk, - BfsFwdIterator &insert_iter, - GenclkInfo *genclk_info) + GenclkInfo *genclk_info, + VertexQueue &insert_queue) { GenClkArrivalSearchPred eval_pred(gclk, this); - GenclkSrcArrivalVisitor arrival_visitor(gclk, &insert_iter, genclk_info, mode_); + GenclkSrcArrivalVisitor arrival_visitor(gclk, genclk_info, insert_queue, mode_); arrival_visitor.init(true, false, &eval_pred); // This cannot restrict the search level because loops in the clock tree // can circle back to the generated clock src pin. // Parallel visit is slightly slower (at last check). - insert_iter.visit(levelize_->maxLevel(), &arrival_visitor); + while (!insert_queue.empty()) { + Vertex *vertex = insert_queue.front(); + insert_queue.pop(); + arrival_visitor.visit(vertex); + } } // Copy generated clock source paths to tag_bldr. @@ -886,15 +906,15 @@ void Genclks::deleteGenclkSrcPaths(Clock *gclk) { GenclkInfo *genclk_info = genclkInfo(gclk); - GenClkInsertionSearchPred srch_pred(gclk, genclk_info, mode_->sta()); - BfsFwdIterator insert_iter(BfsIndex::other, &srch_pred, this); + VertexQueue insert_queue; + GenClkInsertionSearchPred srch_pred(gclk, genclk_info, this); FilterPath *src_filter = genclk_info->srcFilter(); - seedSrcPins(gclk, src_filter, insert_iter); - GenClkArrivalSearchPred eval_pred(gclk, this); - while (insert_iter.hasNext()) { - Vertex *vertex = insert_iter.next(); + seedSrcPins(gclk, src_filter, insert_queue, srch_pred); + while (!insert_queue.empty()) { + Vertex *vertex = insert_queue.front(); + insert_queue.pop(); search_->deletePaths(vertex); - insert_iter.enqueueAdjacentVertices(vertex, &srch_pred, mode_); + enqueueFanout(vertex, insert_queue, srch_pred); } } diff --git a/search/Genclks.hh b/search/Genclks.hh index 67cc55de..500e58e9 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -59,6 +60,7 @@ public: using GenclkInfoMap = std::map; using GenclkSrcPathMap = std::map, ClockPinPairLess>; using VertexGenclkSrcPathsMap = std::map, VertexIdLess>; +using VertexQueue = std::queue; class Genclks : public StaState { @@ -110,10 +112,11 @@ private: const Clock *gclk) const; void seedSrcPins(Clock *gclk, FilterPath *src_filter, - BfsFwdIterator &insert_iter); + VertexQueue &insert_queue, + SearchPred &srch_pred); void findSrcArrivals(Clock *gclk, - BfsFwdIterator &insert_iter, - GenclkInfo *genclk_info); + GenclkInfo *genclk_info, + VertexQueue &insert_queue); FilterPath *makeSrcFilter(Clock *gclk, Sdc *sdc); void deleteGenClkInfo(); @@ -128,6 +131,9 @@ private: void seedSrcPins(Clock *clk, BfsBkwdIterator &iter); void findInsertionDelay(Clock *gclk); + void enqueueFanout(Vertex *vertex, + VertexQueue &insert_queue, + SearchPred &srch_pred); GenclkInfo *makeGenclkInfo(Clock *gclk); FilterPath *srcFilter(Clock *gclk); void findFanin(Clock *gclk, @@ -147,6 +153,8 @@ private: GenclkSrcPathMap genclk_src_paths_; GenclkInfoMap genclk_info_map_; VertexGenclkSrcPathsMap vertex_src_paths_map_; + + friend class GenclkSrcArrivalVisitor; }; } // namespace sta From 266061fcee806fb48e64a4c4665b75d48a0fd8cd Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 09:08:39 -0700 Subject: [PATCH 15/35] Genclks::ensureMaster use queue instead of BfsIterator Signed-off-by: James Cherry --- search/Genclks.cc | 75 ++++++++++++++++++++++++++++------------------- search/Genclks.hh | 5 ++-- 2 files changed, 48 insertions(+), 32 deletions(-) diff --git a/search/Genclks.cc b/search/Genclks.cc index 5e71b207..cf28ace3 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -270,30 +270,38 @@ Genclks::ensureMaster(Clock *gclk, } if (!found_master) { // Search backward from generated clock source pin to a clock pin. - GenClkMasterSearchPred pred(this); - BfsBkwdIterator iter(BfsIndex::other, &pred, this); - seedSrcPins(gclk, iter); - while (iter.hasNext()) { - Vertex *vertex = iter.next(); - Pin *pin = vertex->pin(); - if (sdc->isLeafPinClock(pin)) { - ClockSet *master_clks = sdc->findLeafPinClocks(pin); - if (master_clks) { - ClockSet::iterator master_iter = master_clks->begin(); - if (master_iter != master_clks->end()) { - master_clk = *master_iter++; - // Master source pin can actually be a clock source pin. - if (master_clk != gclk) { - gclk->setInferedMasterClk(master_clk); - debugPrint(debug_, "genclk", 2, " {} master clk {}", gclk->name(), - master_clk->name()); - master_clk_count++; - break; + GenClkMasterSearchPred srch_pred(this); + VertexQueue master_queue; + VertexSet visited = makeVertexSet(this); + VertexSet src_vertices = makeVertexSet(this); + gclk->srcPinVertices(src_vertices, network_, graph_); + for (Vertex *vertex : src_vertices) + master_queue.push(vertex); + while (!master_queue.empty()) { + Vertex *vertex = master_queue.front(); + master_queue.pop(); + if (!visited.contains(vertex)) { + visited.insert(vertex); + Pin *pin = vertex->pin(); + if (sdc->isLeafPinClock(pin)) { + ClockSet *master_clks = sdc->findLeafPinClocks(pin); + if (master_clks) { + ClockSet::iterator master_iter = master_clks->begin(); + if (master_iter != master_clks->end()) { + master_clk = *master_iter++; + // Master source pin can actually be a clock source pin. + if (master_clk != gclk) { + gclk->setInferedMasterClk(master_clk); + debugPrint(debug_, "genclk", 2, " {} master clk {}", gclk->name(), + master_clk->name()); + master_clk_count++; + break; + } } } } + enqueueFanin(vertex, master_queue, srch_pred); } - iter.enqueueAdjacentVertices(vertex, mode_); } } if (master_clk_count > 1) @@ -303,16 +311,6 @@ Genclks::ensureMaster(Clock *gclk, } } -void -Genclks::seedSrcPins(Clock *clk, - BfsBkwdIterator &iter) -{ - VertexSet src_vertices = makeVertexSet(this); - clk->srcPinVertices(src_vertices, network_, graph_); - for (Vertex *vertex : src_vertices) - iter.enqueue(vertex); -} - //////////////////////////////////////////////////////////////// // Similar to ClkTreeSearchPred but @@ -621,6 +619,23 @@ Genclks::seedSrcPins(Clock *gclk, } } +void +Genclks::enqueueFanin(Vertex *vertex, + VertexQueue &insert_queue, + SearchPred &srch_pred) +{ + if (srch_pred.searchTo(vertex, mode_)) { + VertexInEdgeIterator edge_iter(vertex, graph_); + while (edge_iter.hasNext()) { + Edge *edge = edge_iter.next(); + Vertex *from_vertex = edge->from(graph_); + if (srch_pred.searchFrom(from_vertex, mode_) + && srch_pred.searchThru(edge, mode_)) + insert_queue.push(from_vertex); + } + } +} + void Genclks::enqueueFanout(Vertex *vertex, VertexQueue &insert_queue, diff --git a/search/Genclks.hh b/search/Genclks.hh index 500e58e9..172ba789 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -128,9 +128,10 @@ private: Arrival insert, Scene *scene, const MinMax *min_max); - void seedSrcPins(Clock *clk, - BfsBkwdIterator &iter); void findInsertionDelay(Clock *gclk); + void enqueueFanin(Vertex *vertex, + VertexQueue &insert_queue, + SearchPred &srch_pred); void enqueueFanout(Vertex *vertex, VertexQueue &insert_queue, SearchPred &srch_pred); From 2349b76a9535db21076d24ec942c364db7e7ca53 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 09:30:45 -0700 Subject: [PATCH 16/35] Genclks::findFanin use queue instead of BfsIterator Signed-off-by: James Cherry --- search/Genclks.cc | 21 +++++++++++---------- search/Genclks.hh | 7 +++---- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/search/Genclks.cc b/search/Genclks.cc index cf28ace3..caaee7ba 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -26,7 +26,6 @@ #include -#include "Bfs.hh" #include "Clock.hh" #include "ContainerHelpers.hh" #include "Debug.hh" @@ -347,32 +346,34 @@ Genclks::findFanin(Clock *gclk, { // Search backward from generated clock source pin to a clock pin. GenClkFaninSrchPred srch_pred(gclk, this); - BfsBkwdIterator iter(BfsIndex::other, &srch_pred, this); - seedClkVertices(gclk, iter, fanins); - while (iter.hasNext()) { - Vertex *vertex = iter.next(); + VertexQueue fanin_queue; + seedClkVertices(gclk, fanin_queue, fanins, srch_pred); + while (!fanin_queue.empty()) { + Vertex *vertex = fanin_queue.front(); + fanin_queue.pop(); if (!fanins.contains(vertex)) { fanins.insert(vertex); debugPrint(debug_, "genclk", 2, "gen clk {} fanin {}", gclk->name(), vertex->to_string(this)); - iter.enqueueAdjacentVertices(vertex, mode_); + enqueueFanin(vertex, fanin_queue, srch_pred); } } } void Genclks::seedClkVertices(Clock *clk, - BfsBkwdIterator &iter, - VertexSet &fanins) + VertexQueue &fanin_queue, + VertexSet &fanins, + SearchPred &srch_pred) { for (const Pin *pin : clk->leafPins()) { Vertex *vertex, *bidirect_drvr_vertex; graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); fanins.insert(vertex); - iter.enqueueAdjacentVertices(vertex, mode_); + enqueueFanin(vertex, fanin_queue, srch_pred); if (bidirect_drvr_vertex) { fanins.insert(bidirect_drvr_vertex); - iter.enqueueAdjacentVertices(bidirect_drvr_vertex, mode_); + enqueueFanin(bidirect_drvr_vertex, fanin_queue, srch_pred); } } } diff --git a/search/Genclks.hh b/search/Genclks.hh index 172ba789..6ec66cee 100644 --- a/search/Genclks.hh +++ b/search/Genclks.hh @@ -43,8 +43,6 @@ namespace sta { class GenclkInfo; -class BfsFwdIterator; -class BfsBkwdIterator; class SearchPred; class TagGroupBldr; @@ -104,8 +102,9 @@ private: void recordSrcPaths(Clock *gclk); void findInsertionDelays(Clock *gclk); void seedClkVertices(Clock *clk, - BfsBkwdIterator &iter, - VertexSet &dfanins); + VertexQueue &fanin_queue, + VertexSet &fanins, + SearchPred &srch_pred); size_t srcPathIndex(const RiseFall *clk_rf, const MinMax *min_max) const; bool matchesSrcFilter(Path *path, From 0939625580bb752254f8ba778eb4409009e582c5 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 09:31:54 -0700 Subject: [PATCH 17/35] .cursor Signed-off-by: James Cherry --- .cursor/rules/cpp-coding-standards.mdc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.cursor/rules/cpp-coding-standards.mdc b/.cursor/rules/cpp-coding-standards.mdc index fc06afdf..4589e5b3 100644 --- a/.cursor/rules/cpp-coding-standards.mdc +++ b/.cursor/rules/cpp-coding-standards.mdc @@ -34,6 +34,13 @@ alwaysApply: true - Prefer `std::string` over `char*` for string members. - Prefer pass-by-value and move for sink parameters (parameters that get stored). +## Control flow + +- Prefer positive `if` conditions that wrap the main logic instead of early + `continue` or `return` to skip work. +- Example: use `if (!visited.contains(vertex)) { ... }` rather than + `if (visited.contains(vertex)) continue;`. + ## File Extensions - C++ source: `.cc` From c81f0c169d15896eece4b1ecc9fd7dfba3fac041 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 16:54:27 -0700 Subject: [PATCH 18/35] cleanup Signed-off-by: James Cherry --- dcalc/GraphDelayCalc.cc | 66 ++++++++++++++++++++--------------------- power/Power.cc | 28 ++++++++++------- search/Genclks.cc | 11 +++---- 3 files changed, 55 insertions(+), 50 deletions(-) diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index 6fac6faa..6c821dab 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -248,7 +248,7 @@ GraphDelayCalc::delayInvalid(Vertex *vertex) { debugPrint(debug_, "delay_calc", 2, "delay invalid {}", vertex->to_string(this)); - if (graph_ && incremental_) { + if (incremental_) { invalid_delays_.insert(vertex); // Invalidate driver that triggers dcalc for multi-driver nets. MultiDrvrNet *multi_drvr = multiDrvrNet(vertex); @@ -338,40 +338,38 @@ FindVertexDelays::visit(Vertex *vertex) void GraphDelayCalc::findDelays(Level level) { - if (arc_delay_calc_) { - Stats stats(debug_, report_); - int dcalc_count = 0; - debugPrint(debug_, "delay_calc", 1, "find delays to level {}", level); - if (!delays_seeded_) { - iter_->clear(); - seedRootSlews(); - delays_seeded_ = true; - } - else - iter_->ensureSize(); - if (incremental_) - seedInvalidDelays(); - - if (!iter_->empty()) { - FindVertexDelays visitor(this); - dcalc_count += iter_->visitParallel(level, &visitor); - } - - // Timing checks require slews at both ends of the arc, - // so find their delays after all slews are known. - for (Edge *check_edge : invalid_check_edges_) - findCheckEdgeDelays(check_edge, arc_delay_calc_); - invalid_check_edges_.clear(); - - for (Edge *latch_edge : invalid_latch_edges_) - findLatchEdgeDelays(latch_edge); - invalid_latch_edges_.clear(); - - delays_exist_ = true; - incremental_ = true; - debugPrint(debug_, "delay_calc", 1, "found {} delays", dcalc_count); - stats.report("Delay calc"); + Stats stats(debug_, report_); + int dcalc_count = 0; + debugPrint(debug_, "delay_calc", 1, "find delays to level {}", level); + if (!delays_seeded_) { + iter_->clear(); + seedRootSlews(); + delays_seeded_ = true; } + else + iter_->ensureSize(); + if (incremental_) + seedInvalidDelays(); + + if (!iter_->empty()) { + FindVertexDelays visitor(this); + dcalc_count += iter_->visitParallel(level, &visitor); + } + + // Timing checks require slews at both ends of the arc, + // so find their delays after all slews are known. + for (Edge *check_edge : invalid_check_edges_) + findCheckEdgeDelays(check_edge, arc_delay_calc_); + invalid_check_edges_.clear(); + + for (Edge *latch_edge : invalid_latch_edges_) + findLatchEdgeDelays(latch_edge); + invalid_latch_edges_.clear(); + + delays_exist_ = true; + incremental_ = true; + debugPrint(debug_, "delay_calc", 1, "found {} delays", dcalc_count); + stats.report("Delay calc"); } void diff --git a/power/Power.cc b/power/Power.cc index 0d7a4848..0296093e 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -554,9 +554,12 @@ ActivitySrchPred::searchThru(Edge *edge, { const Sdc *sdc = mode->sdc(); const TimingRole *role = edge->role(); - return !(edge->role()->isTimingCheck() || sdc->isDisabledConstraint(edge) - || sdc->isDisabledCondDefault(edge) || edge->isBidirectInstPath() - || edge->isDisabledLoop() || role == TimingRole::regClkToQ() + return !(edge->role()->isTimingCheck() + || sdc->isDisabledConstraint(edge) + || sdc->isDisabledCondDefault(edge) + || edge->isBidirectInstPath() + || edge->isDisabledLoop() + || role == TimingRole::regClkToQ() || role->isLatchDtoQ()); } @@ -744,9 +747,9 @@ PropActivityVisitor::setActivityCheck(const Pin *pin, max_change_ = duty_delta; max_change_pin_ = pin; } - bool changed = density_delta > change_tolerance_ || duty_delta > change_tolerance_ - || activity.origin() != prev_activity.origin(); - ; + bool changed = density_delta > change_tolerance_ + || duty_delta > change_tolerance_ + || activity.origin() != prev_activity.origin(); power_->setActivity(pin, activity); return changed; } @@ -903,8 +906,9 @@ Power::ensureActivities(const Scene *scene) // unless it has been set by command. if (input_activity_.origin() == PwrActivityOrigin::unknown) { float min_period = clockMinPeriod(scene_->mode()->sdc()); - float density = - 0.1 / (min_period != 0.0 ? min_period : units_->timeUnit()->scale()); + if (min_period == 0.0) + min_period = units_->timeUnit()->scale(); + float density = 0.1 / min_period; input_activity_.set(density, 0.5, PwrActivityOrigin::input); } ActivitySrchPred activity_srch_pred(this); @@ -916,7 +920,7 @@ Power::ensureActivities(const Scene *scene) // Propagate activiities through registers. InstanceSet regs = std::move(visitor.visitedRegs()); int pass = 1; - while (!regs.empty() && pass < max_activity_passes_) { + while (!regs.empty() && pass <= max_activity_passes_) { visitor.init(); for (const Instance *reg : regs) // Propagate activiities across register D->Q. @@ -925,8 +929,10 @@ Power::ensureActivities(const Scene *scene) // combinational logic. bfs.visit(levelize_->maxLevel(), &visitor); regs = std::move(visitor.visitedRegs()); - debugPrint(debug_, "power_activity", 1, "Pass {} change {:.2f} {}", pass, - visitor.maxChange(), network_->pathName(visitor.maxChangePin())); + debugPrint(debug_, "power_activity", 1, "Pass {} change {:.2f} {}", + pass, + visitor.maxChange(), + network_->pathName(visitor.maxChangePin())); pass++; } } diff --git a/search/Genclks.cc b/search/Genclks.cc index caaee7ba..03d53d74 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -669,11 +669,12 @@ Genclks::makeTag(const Clock *gclk, state = state->nextState(); ExceptionStateSet *states = new ExceptionStateSet(); states->insert(state); - const ClkInfo *clk_info = search_->findClkInfo( - scene, master_clk->edge(master_rf), master_pin, true, nullptr, true, nullptr, - insert, 0.0, nullptr, min_max, nullptr); - return search_->findTag(scene, master_rf, min_max, clk_info, false, nullptr, false, - states, true, nullptr); + const ClkInfo *clk_info = search_->findClkInfo(scene, master_clk->edge(master_rf), + master_pin, true, nullptr, true, + nullptr, insert, 0.0, nullptr, + min_max, nullptr); + return search_->findTag(scene, master_rf, min_max, clk_info, false, nullptr, + false, states, true, nullptr); } class GenClkArrivalSearchPred : public EvalPred From 458c277c8056bad59a69bcd821c7a4bee093cdc9 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 19:14:30 -0700 Subject: [PATCH 19/35] Sta::delaysInvalidFromFanin Signed-off-by: James Cherry --- include/sta/Sta.hh | 1 - search/Sta.cc | 28 ++++++++-------------------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index da5da08b..bded0b9a 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -1513,7 +1513,6 @@ protected: bool infer_latches); void delayCalcPreamble(); void delaysInvalidFrom(const Port *port); - void delaysInvalidFromFanin(const Port *port); void deleteEdge(Edge *edge); void netParasiticCaps(Net *net, const RiseFall *rf, diff --git a/search/Sta.cc b/search/Sta.cc index 87a3f7d1..e159c7be 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -3965,7 +3965,7 @@ Sta::setPortExtPinCap(const Port *port, for (const MinMax *mm : min_max->range()) sdc->setPortExtPinCap(port, rf1, mm, cap); } - delaysInvalidFromFanin(port); + delaysInvalidFrom(port); } void @@ -4020,7 +4020,7 @@ Sta::setPortExtWireCap(const Port *port, for (const MinMax *mm : min_max->range()) sdc->setPortExtWireCap(port, rf1, mm, cap); } - delaysInvalidFromFanin(port); + delaysInvalidFrom(port); } void @@ -4038,7 +4038,7 @@ Sta::setPortExtFanout(const Port *port, { for (const MinMax *mm : min_max->range()) sdc->setPortExtFanout(port, mm, fanout); - delaysInvalidFromFanin(port); + delaysInvalidFrom(port); } void @@ -5017,20 +5017,6 @@ Sta::delaysInvalidFrom(Vertex *vertex) graph_delay_calc_->delayInvalid(vertex); } -void -Sta::delaysInvalidFromFanin(const Port *port) -{ - if (graph_) { - Instance *top_inst = network_->topInstance(); - Pin *pin = network_->findPin(top_inst, port); - Vertex *vertex, *bidirect_drvr_vertex; - graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); - delaysInvalidFromFanin(vertex); - if (bidirect_drvr_vertex) - delaysInvalidFromFanin(bidirect_drvr_vertex); - } -} - void Sta::delaysInvalidFromFanin(const Pin *pin) { @@ -5070,9 +5056,11 @@ Sta::delaysInvalidFromFanin(Vertex *vertex) VertexInEdgeIterator edge_iter(vertex, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - Vertex *from_vertex = edge->from(graph_); - delaysInvalidFrom(from_vertex); - search_->requiredInvalid(from_vertex); + if (edge->isWire()) { + Vertex *from_vertex = edge->from(graph_); + delaysInvalidFrom(from_vertex); + search_->requiredInvalid(from_vertex); + } } } From a456c352cf76612abb3cca2039e42b4da455a6c4 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 22 Jun 2026 19:20:39 -0700 Subject: [PATCH 20/35] rename LibertyCell::hasSequentials to isSequential Signed-off-by: James Cherry --- doc/ApiChanges.txt | 5 +++++ include/sta/Liberty.hh | 4 +++- liberty/Liberty.cc | 8 +++++++- power/Power.cc | 5 +++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/doc/ApiChanges.txt b/doc/ApiChanges.txt index 7b62f981..0aa3e9f6 100644 --- a/doc/ApiChanges.txt +++ b/doc/ApiChanges.txt @@ -24,6 +24,11 @@ This file summarizes STA API changes for each release. +2026/06/22 +---------- + +Liberty::hasSequentials has been renamed isSequential. + Release 3.1.0 2026/03/25 ------------------------ diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index f34d5e8f..10596472 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -536,7 +536,9 @@ public: bool leakagePowerExists() const { return leakage_power_exists_; } // Register, Latch or Statetable. - bool hasSequentials() const; + bool isSequential() const; + // deprecated 2026-06-22 (use isSequential) + bool hasSequentials() const __attribute__ ((deprecated)); const SequentialSeq &sequentials() const { return sequentials_; } // Find the sequential with the output connected to an (internal) port. Sequential *outputPortSequential(LibertyPort *port); diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 09c92678..2ad71e12 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -1438,6 +1438,12 @@ LibertyCell::outputPortSequential(LibertyPort *port) return nullptr; } +bool +LibertyCell::isSequential() const +{ + return !sequentials_.empty() || statetable_ != nullptr; +} + bool LibertyCell::hasSequentials() const { @@ -1618,7 +1624,7 @@ void LibertyCell::makeLatchEnables(Report *report, Debug *debug) { - if (hasSequentials() + if (isSequential() || hasInferedRegTimingArcs()) { for (TimingArcSet *d_to_q : timing_arc_sets_) { if (d_to_q->role() == TimingRole::latchDtoQ()) { diff --git a/power/Power.cc b/power/Power.cc index 0296093e..689297f9 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -443,7 +443,7 @@ Power::power(const Scene *scene, pad.incr(inst_power); else if (inClockNetwork(inst, clk_network)) clock.incr(inst_power); - else if (cell->hasSequentials()) + else if (cell->isSequential()) sequential.incr(inst_power); else combinational.incr(inst_power); @@ -695,7 +695,8 @@ PropActivityVisitor::visit(Vertex *vertex) if (cell) { LibertyCell *test_cell = cell->libertyCell()->testCell(); if (network_->isLoad(pin)) { - if (cell->hasSequentials() || (test_cell && test_cell->hasSequentials())) { + if (cell->isSequential() + || (test_cell && test_cell->isSequential())) { debugPrint(debug_, "power_activity", 3, "pending seq {}", network_->pathName(inst)); visited_regs_.insert(inst); From f1adf5b26acd327cfc4b5950036b573ff2efb340 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 23 Jun 2026 15:09:08 -0700 Subject: [PATCH 21/35] Graph::visitFanouts, visitFanins Signed-off-by: James Cherry --- graph/Graph.cc | 85 +++++++++++++++++++++++++++++++++++---- include/sta/Graph.hh | 15 ++++++- include/sta/GraphClass.hh | 2 + search/Genclks.cc | 26 ++++-------- 4 files changed, 101 insertions(+), 27 deletions(-) diff --git a/graph/Graph.cc b/graph/Graph.cc index 6c9d47e8..92775d57 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -32,6 +32,7 @@ #include "Mutex.hh" #include "Network.hh" #include "PortDirection.hh" +#include "SearchPred.hh" #include "Stats.hh" #include "TimingArc.hh" #include "TimingRole.hh" @@ -487,7 +488,7 @@ Graph::deleteVertex(Vertex *vertex) EdgeId edge_id, next_id; for (edge_id = vertex->in_edges_; edge_id; edge_id = next_id) { Edge *edge = Graph::edge(edge_id); - next_id = edge->vertex_in_link_; + next_id = edge->vertex_in_next_; deleteOutEdge(edge->from(this), edge); edge->clear(); edges_->destroy(edge); @@ -508,7 +509,7 @@ bool Graph::hasFaninOne(Vertex *vertex) const { return vertex->in_edges_ - && edge(vertex->in_edges_)->vertex_in_link_ == 0; + && edge(vertex->in_edges_)->vertex_in_next_ == 0; } void @@ -519,12 +520,12 @@ Graph::deleteInEdge(Vertex *vertex, EdgeId prev = 0; for (EdgeId i = vertex->in_edges_; i && i != edge_id; - i = Graph::edge(i)->vertex_in_link_) + i = Graph::edge(i)->vertex_in_next_) prev = i; if (prev) - Graph::edge(prev)->vertex_in_link_ = edge->vertex_in_link_; + Graph::edge(prev)->vertex_in_next_ = edge->vertex_in_next_; else - vertex->in_edges_ = edge->vertex_in_link_; + vertex->in_edges_ = edge->vertex_in_next_; } void @@ -574,6 +575,72 @@ Graph::gateEdgeArc(const Pin *in_pin, //////////////////////////////////////////////////////////////// +void +Graph::visitFanouts(Vertex *vertex, + SearchPred *pred, + const VertexFn &fn) +{ + if (pred->searchFrom(vertex)) { + for (Edge *edge = this->edge(vertex->out_edges_); + edge; + edge = this->edge(edge->vertex_out_next_)) { + Vertex *to_vertex = this->vertex(edge->to_); + if (pred->searchThru(edge) && pred->searchTo(to_vertex)) + fn(to_vertex); + } + } +} + +void +Graph::visitFanoutEdges(Vertex *vertex, + SearchPred *pred, + const EdgeFn &fn) +{ + if (pred->searchFrom(vertex)) { + for (Edge *edge = this->edge(vertex->out_edges_); + edge; + edge = this->edge(edge->vertex_out_next_)) { + Vertex *to_vertex = this->vertex(edge->to_); + if (pred->searchThru(edge) && pred->searchTo(to_vertex)) + fn(edge, to_vertex); + } + } +} + +void +Graph::visitFanins(Vertex *vertex, + SearchPred *pred, + const VertexFn &fn) +{ + if (pred->searchFrom(vertex)) { + for (Edge *edge = this->edge(vertex->in_edges_); + edge; + edge = this->edge(edge->vertex_in_next_)) { + Vertex *from_vertex = this->vertex(edge->from_); + if (pred->searchThru(edge) && pred->searchFrom(from_vertex)) + fn(from_vertex); + } + } +} + +void +Graph::visitFaninEdges(Vertex *vertex, + SearchPred *pred, + const EdgeFn &fn) +{ + if (pred->searchFrom(vertex)) { + for (Edge *edge = this->edge(vertex->in_edges_); + edge; + edge = this->edge(edge->vertex_in_next_)) { + Vertex *from_vertex = this->vertex(edge->from_); + if (pred->searchThru(edge) && pred->searchFrom(from_vertex)) + fn(edge, from_vertex); + } + } +} + +//////////////////////////////////////////////////////////////// + Slew Graph::slew(const Vertex *vertex, const RiseFall *rf, @@ -650,7 +717,7 @@ Graph::makeEdge(Vertex *from, from->out_edges_ = edge_id; // Add in edge to to vertex. - edge->vertex_in_link_ = to->in_edges_; + edge->vertex_in_next_ = to->in_edges_; to->in_edges_ = edge_id; initArcDelays(edge); @@ -1213,7 +1280,7 @@ Edge::init(VertexId from, from_ = from; to_ = to; arc_set_ = arc_set; - vertex_in_link_ = edge_id_null; + vertex_in_next_ = edge_id_null; vertex_out_next_ = edge_id_null; vertex_out_prev_ = edge_id_null; is_bidirect_inst_path_ = false; @@ -1464,6 +1531,8 @@ VertexIterator::findNext() findNextPin(); } +//////////////////////////////////////////////////////////////// + VertexInEdgeIterator::VertexInEdgeIterator(Vertex *vertex, const Graph *graph) : next_(graph->edge(vertex->in_edges_)), @@ -1483,7 +1552,7 @@ VertexInEdgeIterator::next() { Edge *next = next_; if (next_) - next_ = graph_->edge(next_->vertex_in_link_); + next_ = graph_->edge(next_->vertex_in_next_); return next; } diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index 1f6e7ce2..abe38883 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -87,6 +87,19 @@ public: bool hasFaninOne(Vertex *vertex) const; VertexId vertexCount() { return vertices_->size(); } + void visitFanouts(Vertex *vertex, + SearchPred *pred, + const VertexFn &fn); + void visitFanins(Vertex *vertex, + SearchPred *pred, + const VertexFn &fn); + void visitFanoutEdges(Vertex *vertex, + SearchPred *pred, + const EdgeFn &fn); + void visitFaninEdges(Vertex *vertex, + SearchPred *pred, + const EdgeFn &fn); + // Reported slew are the same as those in the liberty tables. // reported_slews = measured_slews / slew_derate_from_library // Measured slews are between slew_lower_threshold and slew_upper_threshold. @@ -394,7 +407,7 @@ protected: TimingArcSet *arc_set_; VertexId from_; VertexId to_; - EdgeId vertex_in_link_; // Vertex in edges list. + EdgeId vertex_in_next_; // Vertex in edges list. EdgeId vertex_out_next_; // Vertex out edges doubly linked list. EdgeId vertex_out_prev_; float *arc_delays_; diff --git a/include/sta/GraphClass.hh b/include/sta/GraphClass.hh index cdf7539b..542f3ac0 100644 --- a/include/sta/GraphClass.hh +++ b/include/sta/GraphClass.hh @@ -65,6 +65,8 @@ using Level = int; using DcalcAPIndex = int; using TagGroupIndex = int; using SlewSeq = std::vector; +using VertexFn = std::function; +using EdgeFn = std::function; static constexpr int level_max = std::numeric_limits::max(); diff --git a/search/Genclks.cc b/search/Genclks.cc index 03d53d74..7b16a51f 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -625,16 +625,10 @@ Genclks::enqueueFanin(Vertex *vertex, VertexQueue &insert_queue, SearchPred &srch_pred) { - if (srch_pred.searchTo(vertex, mode_)) { - VertexInEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *from_vertex = edge->from(graph_); - if (srch_pred.searchFrom(from_vertex, mode_) - && srch_pred.searchThru(edge, mode_)) - insert_queue.push(from_vertex); - } - } + graph_->visitFanins(vertex, &srch_pred, + [&insert_queue] (Vertex *fanin) { + insert_queue.push(fanin); + }); } void @@ -642,14 +636,10 @@ Genclks::enqueueFanout(Vertex *vertex, VertexQueue &insert_queue, SearchPred &srch_pred) { - VertexOutEdgeIterator edge_iter(vertex, graph_); - while (edge_iter.hasNext()) { - Edge *edge = edge_iter.next(); - Vertex *to_vertex = edge->to(graph_); - if (srch_pred.searchThru(edge, mode_) - && srch_pred.searchTo(to_vertex, mode_)) - insert_queue.push(to_vertex); - } + graph_->visitFanouts(vertex, &srch_pred, + [&insert_queue] (Vertex *fanout) { + insert_queue.push(fanout); + }); } Tag * From e603b7abe024fd478b7afc9332a8932439de0b4a Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 24 Jun 2026 16:55:51 -0700 Subject: [PATCH 22/35] dynamic loop do not use search pred Signed-off-by: James Cherry --- graph/Graph.cc | 12 ++- include/sta/Search.hh | 16 ++-- include/sta/SearchPred.hh | 8 +- search/PathEnum.cc | 38 +++++++-- search/Search.cc | 159 +++++++++++++++++++++----------------- 5 files changed, 140 insertions(+), 93 deletions(-) diff --git a/graph/Graph.cc b/graph/Graph.cc index 92775d57..e2123cf2 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -585,7 +585,8 @@ Graph::visitFanouts(Vertex *vertex, edge; edge = this->edge(edge->vertex_out_next_)) { Vertex *to_vertex = this->vertex(edge->to_); - if (pred->searchThru(edge) && pred->searchTo(to_vertex)) + if (pred->searchThru(edge) + && pred->searchTo(to_vertex)) fn(to_vertex); } } @@ -601,7 +602,8 @@ Graph::visitFanoutEdges(Vertex *vertex, edge; edge = this->edge(edge->vertex_out_next_)) { Vertex *to_vertex = this->vertex(edge->to_); - if (pred->searchThru(edge) && pred->searchTo(to_vertex)) + if (pred->searchThru(edge) + && pred->searchTo(to_vertex)) fn(edge, to_vertex); } } @@ -617,7 +619,8 @@ Graph::visitFanins(Vertex *vertex, edge; edge = this->edge(edge->vertex_in_next_)) { Vertex *from_vertex = this->vertex(edge->from_); - if (pred->searchThru(edge) && pred->searchFrom(from_vertex)) + if (pred->searchThru(edge) + && pred->searchFrom(from_vertex)) fn(from_vertex); } } @@ -633,7 +636,8 @@ Graph::visitFaninEdges(Vertex *vertex, edge; edge = this->edge(edge->vertex_in_next_)) { Vertex *from_vertex = this->vertex(edge->from_); - if (pred->searchThru(edge) && pred->searchFrom(from_vertex)) + if (pred->searchThru(edge) + && pred->searchFrom(from_vertex)) fn(edge, from_vertex); } } diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 8122752e..1fff5663 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -284,8 +284,8 @@ public: Vertex *vertex, const Mode *mode, TagGroupBldr *tag_bldr); - void enqueueLatchDataOutputs(Vertex *vertex); - void enqueueLatchOutput(Vertex *vertex); + void postponeLatchDataOutputs(Vertex *vertex); + void postponeArrivals(Vertex *vertex); void enqueuePendingClkFanouts(); void postponeClkFanouts(Vertex *vertex); void seedRequired(Vertex *vertex); @@ -590,7 +590,7 @@ protected: // Search predicates. SearchPred *search_thru_; - SearchAdj *search_adj_; + SearchPred *search_adj_; EvalPred *eval_pred_; // Some arrivals exist. @@ -647,11 +647,11 @@ protected: std::mutex tag_group_lock_; // Latches data outputs to queue on the next search pass. - VertexSet pending_latch_outputs_; - std::mutex pending_latch_outputs_lock_; + VertexSet postponed_arrivals_; + std::mutex postponed_arrivals_lock_; // Clock network endpoints where arrival search was suppended by findClkArrivals(). - VertexSet pending_clk_endpoints_; - std::mutex pending_clk_endpoints_lock_; + VertexSet postponed_clk_endpoints_; + std::mutex postponed_clk_endpoints_lock_; VertexSet endpoints_; bool endpoints_initialized_{false}; @@ -802,6 +802,8 @@ protected: void pruneCrprArrivals(); void constrainedRequiredsInvalid(Vertex *vertex, bool is_clk); + bool hasPendingLoopPaths(Edge *edge) const; + bool always_to_endpoints_; bool always_save_prev_paths_; bool clks_only_; diff --git a/include/sta/SearchPred.hh b/include/sta/SearchPred.hh index 9bcdf9b8..378e8655 100644 --- a/include/sta/SearchPred.hh +++ b/include/sta/SearchPred.hh @@ -51,19 +51,19 @@ public: // Search is allowed from from_vertex. virtual bool searchFrom(const Vertex *from_vertex, const Mode *mode) const = 0; - bool searchFrom(const Vertex *from_vertex) const; + virtual bool searchFrom(const Vertex *from_vertex) const; // Search is allowed through edge. // from/to pins are NOT checked. // inst can be either the from_pin or to_pin instance because it // is only referenced when they are the same (non-wire edge). virtual bool searchThru(Edge *edge, const Mode *mode) const = 0; - bool searchThru(Edge *edge) const; + virtual bool searchThru(Edge *edge) const; // Search is allowed to to_pin. virtual bool searchTo(const Vertex *to_vertex, const Mode *mode) const = 0; - bool searchTo(const Vertex *to_vertex) const; - void copyState(const StaState *sta); + virtual bool searchTo(const Vertex *to_vertex) const; + virtual void copyState(const StaState *sta); protected: const StaState *sta_; diff --git a/search/PathEnum.cc b/search/PathEnum.cc index e433c703..e0a3ec20 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -238,6 +238,28 @@ PathEnum::reportDiversionPath(Diversion *div) using VisitedFanins = std::set>; using VertexEdge = std::pair; +class EnumPred : public EvalPred +{ +public: + EnumPred(const StaState *sta); + bool searchThru(Edge *edge, + const Mode *mode) const override; +}; + +EnumPred::EnumPred(const StaState *sta) : + EvalPred(sta) +{ +} + +bool +EnumPred::searchThru(Edge *edge, + const Mode *mode) const +{ + // Do not enum paths across disabled loop edges. + return EvalPred::searchThru(edge, mode) + && !edge->isDisabledLoop(); +} + class PathEnumFaninVisitor : public PathVisitor { public: @@ -247,6 +269,7 @@ public: bool unique_edges, PathEnum *path_enum); PathEnumFaninVisitor(const PathEnumFaninVisitor &visitor); + virtual ~PathEnumFaninVisitor(); VertexVisitor *copy() const override; void visitFaninPathsThru(Path *before_div, Vertex *prev_vertex, @@ -311,7 +334,7 @@ PathEnumFaninVisitor::PathEnumFaninVisitor(PathEnd *path_end, bool unique_pins, bool unique_edges, PathEnum *path_enum) : - PathVisitor(path_enum), + PathVisitor(new EnumPred(path_enum), false, path_enum), path_end_(path_end), before_div_(before_div), unique_pins_(unique_pins), @@ -334,6 +357,11 @@ PathEnumFaninVisitor::PathEnumFaninVisitor(const PathEnumFaninVisitor &visitor) { } +PathEnumFaninVisitor::~PathEnumFaninVisitor() +{ + delete pred_; +} + VertexVisitor * PathEnumFaninVisitor::copy() const { @@ -655,10 +683,10 @@ PathEnum::makeDivertedPath(Path *path, Path *prev_copy = nullptr; while (p) { // prev_path made in next pass. - Path *copy = - new Path(p->vertex(this), p->tag(this), p->arrival(), - // Replaced on next pass. - p->prevPath(), p->prevEdge(this), p->prevArc(this), true, this); + Path *copy = new Path(p->vertex(this), p->tag(this), p->arrival(), + // Replaced on next pass. + p->prevPath(), p->prevEdge(this), p->prevArc(this), + true, this); search_->saveEnumPath(copy); if (prev_copy) prev_copy->setPrevPath(copy); diff --git a/search/Search.cc b/search/Search.cc index ae23c681..d1de9c1e 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -95,8 +95,8 @@ EvalPred::searchThru(Edge *edge, { const TimingRole *role = edge->role(); return SearchPred0::searchThru(edge, mode) - && (sta_->variables()->dynamicLoopBreaking() || !edge->isDisabledLoop()) - && (search_thru_latches_ || role->isLatchDtoQ() + && (search_thru_latches_ + || role->isLatchDtoQ() || sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open); } @@ -133,54 +133,56 @@ bool SearchThru::searchThru(Edge *edge, const Mode *mode) const { - return EvalPred::searchThru(edge, mode) && !edge->role()->isLatchDtoQ(); + return EvalPred::searchThru(edge, mode) + && !edge->role()->isLatchDtoQ(); } //////////////////////////////////////////////////////////////// // SearchAdj is mode independent. Search unless -// disabled to break combinational loop // latch D->Q edge // timing check edge -// dynamic loop breaking pending tags +// register set/clear +// bidirect load->driver class SearchAdj : public SearchPred { public: - SearchAdj(TagGroupBldr *tag_bldr, - const StaState *sta); + SearchAdj(const StaState *sta); + bool searchFrom(const Vertex *from_vertex) const override; bool searchFrom(const Vertex *from_vertex, const Mode *mode) const override; + bool searchThru(Edge *edge) const override; bool searchThru(Edge *edge, const Mode *mode) const override; + bool searchTo(const Vertex *to_vertex) const override; bool searchTo(const Vertex *to_vertex, const Mode *mode) const override; protected: - bool loopEnabled(Edge *edge) const; - bool hasPendingLoopPaths(Edge *edge) const; - - TagGroupBldr *tag_bldr_; const StaState *sta_; }; -SearchAdj::SearchAdj(TagGroupBldr *tag_bldr, - const StaState *sta) : +SearchAdj::SearchAdj(const StaState *sta) : SearchPred(sta), - tag_bldr_(tag_bldr), sta_(sta) { } bool -SearchAdj::searchFrom(const Vertex * /* from_vertex */, +SearchAdj::searchFrom(const Vertex *) const +{ + return true; +} + +bool +SearchAdj::searchFrom(const Vertex *, const Mode *) const { return true; } bool -SearchAdj::searchThru(Edge *edge, - const Mode *) const +SearchAdj::searchThru(Edge *edge) const { const TimingRole *role = edge->role(); const Variables *variables = sta_->variables(); @@ -189,42 +191,24 @@ SearchAdj::searchThru(Edge *edge, // Register/latch preset/clr edges are disabled by default. || (role == TimingRole::regSetClr() && !variables->presetClrArcsEnabled()) - || sta_->isDisabledBidirectInstPath(edge) - || (edge->isDisabledLoop() - && !(variables->dynamicLoopBreaking() && hasPendingLoopPaths(edge)))); + || sta_->isDisabledBidirectInstPath(edge)); } bool -SearchAdj::loopEnabled(Edge *edge) const +SearchAdj::searchThru(Edge *edge, + const Mode *) const { - return !edge->isDisabledLoop() - || (sta_->variables()->dynamicLoopBreaking() && hasPendingLoopPaths(edge)); + return searchThru(edge); } bool -SearchAdj::hasPendingLoopPaths(Edge *edge) const +SearchAdj::searchTo(const Vertex *) const { - if (tag_bldr_ && tag_bldr_->hasLoopTag()) { - const Graph *graph = sta_->graph(); - Search *search = sta_->search(); - Vertex *from_vertex = edge->from(graph); - TagGroup *prev_tag_group = search->tagGroup(from_vertex); - for (auto const [from_tag, path_index] : tag_bldr_->pathIndexMap()) { - if (from_tag->isLoop()) { - // Loop false path exceptions apply to rise/fall edges so to_rf - // does not matter. - Tag *to_tag = search->thruTag(from_tag, edge, RiseFall::rise(), nullptr); - if (to_tag - && (prev_tag_group == nullptr || !prev_tag_group->hasTag(from_tag))) - return true; - } - } - } - return false; + return true; } bool -SearchAdj::searchTo(const Vertex * /* to_vertex */, +SearchAdj::searchTo(const Vertex *, const Mode *) const { return true; @@ -236,8 +220,7 @@ Search::Search(StaState *sta) : StaState(sta), search_thru_(new SearchThru(this)), - search_adj_(new SearchAdj(nullptr, - this)), + search_adj_(new SearchAdj(this)), eval_pred_(new EvalPred(this)), invalid_arrivals_(makeVertexSet(this)), @@ -247,9 +230,7 @@ Search::Search(StaState *sta) : arrival_visitor_(new ArrivalVisitor(this)), invalid_requireds_(makeVertexSet(this)), - required_iter_(new BfsBkwdIterator(BfsIndex::required, - search_adj_, - this)), + required_iter_(new BfsBkwdIterator(BfsIndex::required, search_adj_, this)), invalid_tns_(makeVertexSet(this)), clk_info_set_(new ClkInfoSet(ClkInfoLess(this))), @@ -261,8 +242,8 @@ Search::Search(StaState *sta) : tag_group_capacity_(tag_capacity_), tag_groups_(new TagGroup *[tag_group_capacity_]), tag_group_set_(new TagGroupSet(tag_group_capacity_)), - pending_latch_outputs_(makeVertexSet(this)), - pending_clk_endpoints_(makeVertexSet(this)), + postponed_arrivals_(makeVertexSet(this)), + postponed_clk_endpoints_(makeVertexSet(this)), endpoints_(makeVertexSet(this)), invalid_endpoints_(makeVertexSet(this)), @@ -326,8 +307,8 @@ Search::clear() deletePathGroups(); deletePaths(); deleteTags(); - pending_latch_outputs_.clear(); - pending_clk_endpoints_.clear(); + postponed_arrivals_.clear(); + postponed_clk_endpoints_.clear(); deleteFilter(); found_downstream_clk_pins_ = false; } @@ -655,10 +636,10 @@ Search::findFilteredArrivals(bool thru_latches) int arrival_count = arrival_iter_->visitParallel(max_level, arrival_visitor_); debugPrint(debug_, "search", 1, "found {} arrivals", arrival_count); - have_pending_latch_outputs = !pending_latch_outputs_.empty(); - for (Vertex *latch_output : pending_latch_outputs_) + have_pending_latch_outputs = !postponed_arrivals_.empty(); + for (Vertex *latch_output : postponed_arrivals_) arrival_visitor_->visit(latch_output, true); - pending_latch_outputs_.clear(); + postponed_arrivals_.clear(); deleteTagsPrev(); } @@ -997,29 +978,30 @@ Search::findAllArrivals(bool thru_latches, findArrivals1(levelize_->maxLevel()); - have_pending_latch_outputs = !pending_latch_outputs_.empty(); - for (Vertex *latch_output : pending_latch_outputs_) + have_pending_latch_outputs = !postponed_arrivals_.empty(); + for (Vertex *latch_output : postponed_arrivals_) arrival_visitor_->visit(latch_output, true); - pending_latch_outputs_.clear(); + postponed_arrivals_.clear(); } } +// Pick up where the search stopped at the clock network boundary. void Search::enqueuePendingClkFanouts() { - for (Vertex *vertex : pending_clk_endpoints_) { + for (Vertex *vertex : postponed_clk_endpoints_) { debugPrint(debug_, "search", 2, "enqueue clk fanout {}", vertex->to_string(this)); arrival_iter_->enqueueAdjacentVertices(vertex, search_adj_); } - pending_clk_endpoints_.clear(); + postponed_clk_endpoints_.clear(); } void Search::postponeClkFanouts(Vertex *vertex) { - LockGuard lock(pending_clk_endpoints_lock_); - pending_clk_endpoints_.insert(vertex); + LockGuard lock(postponed_clk_endpoints_lock_); + postponed_clk_endpoints_.insert(vertex); } void @@ -1089,7 +1071,7 @@ ArrivalVisitor::init0() { tag_bldr_ = new TagGroupBldr(true, this); tag_bldr_no_crpr_ = new TagGroupBldr(false, this); - adj_pred_ = new SearchAdj(tag_bldr_, this); + adj_pred_ = new SearchAdj(this); } void @@ -1133,7 +1115,7 @@ void ArrivalVisitor::visit(Vertex *vertex) { if (network_->isLatchOutput(vertex->pin())) - search_->enqueueLatchOutput(vertex); + search_->postponeArrivals(vertex); else visit(vertex, false); } @@ -1167,15 +1149,25 @@ ArrivalVisitor::visit(Vertex *vertex, // previous eval pass enqueue the latch outputs to be re-evaled on the // next pass. if (arrivals_changed && network_->isLatchData(pin)) - search_->enqueueLatchDataOutputs(vertex); + search_->postponeLatchDataOutputs(vertex); if ((always_to_endpoints_ || arrivals_changed)) { if (clks_only_ && vertex->isRegClk()) { debugPrint(debug_, "search", 3, "postponing clk fanout"); search_->postponeClkFanouts(vertex); } - else - search_->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_); + else { + graph_->visitFanoutEdges(vertex, adj_pred_, + [this] (Edge *edge, + Vertex *fanout) { + if (edge->isDisabledLoop()) { + if (hasPendingLoopPaths(edge)) + search_->postponeArrivals(fanout); + } + else + search_->arrivalIterator()->enqueue(fanout); + }); + } } if (arrivals_changed) { debugPrint(debug_, "search", 4, "arrivals changed"); @@ -1185,6 +1177,26 @@ ArrivalVisitor::visit(Vertex *vertex, } } +bool +ArrivalVisitor::hasPendingLoopPaths(Edge *edge) const +{ + if (tag_bldr_ && tag_bldr_->hasLoopTag()) { + Vertex *from_vertex = edge->from(graph_); + TagGroup *prev_tag_group = search_->tagGroup(from_vertex); + for (auto const [from_tag, path_index] : tag_bldr_->pathIndexMap()) { + if (from_tag->isLoop()) { + // Loop false path exceptions apply to rise/fall edges so to_rf + // does not matter. + Tag *to_tag = search_->thruTag(from_tag, edge, RiseFall::rise(), nullptr); + if (to_tag + && (prev_tag_group == nullptr || !prev_tag_group->hasTag(from_tag))) + return true; + } + } + } + return false; +} + void ArrivalVisitor::seedArrivals(Vertex *vertex) { @@ -1385,24 +1397,24 @@ ArrivalVisitor::pruneCrprArrivals() } void -Search::enqueueLatchDataOutputs(Vertex *latch_data) +Search::postponeLatchDataOutputs(Vertex *latch_data) { VertexOutEdgeIterator edge_iter(latch_data, graph_); while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); if (edge->role() == TimingRole::latchDtoQ()) { Vertex *out_vertex = edge->to(graph_); - LockGuard lock(pending_latch_outputs_lock_); - pending_latch_outputs_.insert(out_vertex); + LockGuard lock(postponed_arrivals_lock_); + postponed_arrivals_.insert(out_vertex); } } } void -Search::enqueueLatchOutput(Vertex *vertex) +Search::postponeArrivals(Vertex *vertex) { - LockGuard lock(pending_latch_outputs_lock_); - pending_latch_outputs_.insert(vertex); + LockGuard lock(postponed_arrivals_lock_); + postponed_arrivals_.insert(vertex); } void @@ -1995,7 +2007,8 @@ PathVisitor::visitEdge(const Pin *from_pin, Path *from_path = from_iter.next(); const Mode *mode = from_path->mode(this); if (mode == prev_mode - || (pred_->searchFrom(from_vertex, mode) && pred_->searchThru(edge, mode) + || (pred_->searchFrom(from_vertex, mode) + && pred_->searchThru(edge, mode) && pred_->searchTo(to_vertex, mode))) { prev_mode = mode; const MinMax *min_max = from_path->minMax(this); From 7527553111c1f4233c5238cf4c0aee562d2b250e Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 24 Jun 2026 17:00:00 -0700 Subject: [PATCH 23/35] leak Signed-off-by: James Cherry --- liberty/TimingArc.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/liberty/TimingArc.cc b/liberty/TimingArc.cc index a8ec5516..8a03ae65 100644 --- a/liberty/TimingArc.cc +++ b/liberty/TimingArc.cc @@ -536,6 +536,9 @@ TimingArcSet::destroy() delete wire_timing_arc_set_; wire_timing_arc_set_ = nullptr; wire_timing_arc_attrs_ = nullptr; + + delete port_refpin_timing_arc_set_; + port_refpin_timing_arc_set_ = nullptr; } //////////////////////////////////////////////////////////////// From 2f26c1e21a1670ea44d099e582e9842372068a34 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 24 Jun 2026 18:02:47 -0700 Subject: [PATCH 24/35] make_net check for existing Signed-off-by: James Cherry --- search/Sta.cc | 12 +++++++++--- verilog/VerilogReader.cc | 9 +++------ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/search/Sta.cc b/search/Sta.cc index e159c7be..19f3d994 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -4407,9 +4407,15 @@ Sta::makeNet(const char *name, { NetworkEdit *network = networkCmdEdit(); std::string escaped = escapeBrackets(name, network); - Net *net = network->makeNet(escaped, parent); - // Sta notification unnecessary. - return net; + if (network->findNet(parent, escaped)) { + report_->warn(1557, "net {} already exists.", name); + return nullptr; + } + else { + Net *net = network->makeNet(escaped, parent); + // Sta notification unnecessary. + return net; + } } void diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index 5c6cd0f9..f3a0899d 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -1468,8 +1468,7 @@ VerilogReader::linkNetwork(std::string_view top_cell_name, while (net_name_iter->hasNext()) { const std::string &net_name = net_name_iter->next(); Port *port = network_->findPort(top_cell, net_name); - Net *net = - bindings.ensureNetBinding(net_name, top_instance, network_); + Net *net = bindings.ensureNetBinding(net_name, top_instance, network_); // Guard against repeated port name. if (network_->findPin(top_instance, port) == nullptr) { Pin *pin = network_->makePin(top_instance, port, nullptr); @@ -1521,13 +1520,11 @@ VerilogReader::makeModuleInstBody(VerilogModule *module, if (assign) mergeAssignNet(assign, module, inst, bindings); if (dir->isGround()) { - Net *net = - bindings->ensureNetBinding(arg->netName(), inst, network_); + Net *net = bindings->ensureNetBinding(arg->netName(), inst, network_); network_->addConstantNet(net, LogicValue::zero); } if (dir->isPower()) { - Net *net = - bindings->ensureNetBinding(arg->netName(), inst, network_); + Net *net = bindings->ensureNetBinding(arg->netName(), inst, network_); network_->addConstantNet(net, LogicValue::one); } } From 0b938d71eb6e66a4a24f9ad1f9849f90c2a93ffd Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 25 Jun 2026 10:04:39 -0700 Subject: [PATCH 25/35] SearchAdjLoop predicate Signed-off-by: James Cherry --- include/sta/Search.hh | 2 +- search/Search.cc | 55 ++++++++++++++++++++++++++++++------------- 2 files changed, 39 insertions(+), 18 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 1fff5663..7cfefde1 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -809,7 +809,7 @@ protected: bool clks_only_; TagGroupBldr *tag_bldr_; TagGroupBldr *tag_bldr_no_crpr_; - SearchPred *adj_pred_; + SearchPred *srch_adj_; bool crpr_active_; bool has_fanin_one_; }; diff --git a/search/Search.cc b/search/Search.cc index d1de9c1e..27d196e1 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -139,15 +139,15 @@ SearchThru::searchThru(Edge *edge, //////////////////////////////////////////////////////////////// -// SearchAdj is mode independent. Search unless +// SearchAdjLoop is mode independent. Search unless // latch D->Q edge // timing check edge // register set/clear // bidirect load->driver -class SearchAdj : public SearchPred +class SearchAdjLoop : public SearchPred { public: - SearchAdj(const StaState *sta); + SearchAdjLoop(const StaState *sta); bool searchFrom(const Vertex *from_vertex) const override; bool searchFrom(const Vertex *from_vertex, const Mode *mode) const override; @@ -162,27 +162,27 @@ protected: const StaState *sta_; }; -SearchAdj::SearchAdj(const StaState *sta) : +SearchAdjLoop::SearchAdjLoop(const StaState *sta) : SearchPred(sta), sta_(sta) { } bool -SearchAdj::searchFrom(const Vertex *) const +SearchAdjLoop::searchFrom(const Vertex *) const { return true; } bool -SearchAdj::searchFrom(const Vertex *, - const Mode *) const +SearchAdjLoop::searchFrom(const Vertex *, + const Mode *) const { return true; } bool -SearchAdj::searchThru(Edge *edge) const +SearchAdjLoop::searchThru(Edge *edge) const { const TimingRole *role = edge->role(); const Variables *variables = sta_->variables(); @@ -195,25 +195,46 @@ SearchAdj::searchThru(Edge *edge) const } bool -SearchAdj::searchThru(Edge *edge, - const Mode *) const +SearchAdjLoop::searchThru(Edge *edge, + const Mode *) const { return searchThru(edge); } bool -SearchAdj::searchTo(const Vertex *) const +SearchAdjLoop::searchTo(const Vertex *) const { return true; } bool -SearchAdj::searchTo(const Vertex *, - const Mode *) const +SearchAdjLoop::searchTo(const Vertex *, + const Mode *) const { return true; } +// SearchAdj is mode independent. Search unless +// SearchAdjLoop but not thru disabled loop edges. +class SearchAdj : public SearchAdjLoop +{ +public: + SearchAdj(const StaState *sta); + bool searchThru(Edge *edge) const override; +}; + +SearchAdj::SearchAdj(const StaState *sta) : + SearchAdjLoop(sta) +{ +} + +bool +SearchAdj::searchThru(Edge *edge) const +{ + return SearchAdjLoop::searchThru(edge) + && !edge->isDisabledLoop(); +} + //////////////////////////////////////////////////////////////// Search::Search(StaState *sta) : @@ -1071,7 +1092,7 @@ ArrivalVisitor::init0() { tag_bldr_ = new TagGroupBldr(true, this); tag_bldr_no_crpr_ = new TagGroupBldr(false, this); - adj_pred_ = new SearchAdj(this); + srch_adj_ = new SearchAdjLoop(this); } void @@ -1095,14 +1116,14 @@ void ArrivalVisitor::copyState(const StaState *sta) { StaState::copyState(sta); - adj_pred_->copyState(sta); + srch_adj_->copyState(sta); } ArrivalVisitor::~ArrivalVisitor() { delete tag_bldr_; delete tag_bldr_no_crpr_; - delete adj_pred_; + delete srch_adj_; } void @@ -1157,7 +1178,7 @@ ArrivalVisitor::visit(Vertex *vertex, search_->postponeClkFanouts(vertex); } else { - graph_->visitFanoutEdges(vertex, adj_pred_, + graph_->visitFanoutEdges(vertex, srch_adj_, [this] (Edge *edge, Vertex *fanout) { if (edge->isDisabledLoop()) { From bfdd2be0ee6214115b20cacdc0a071ca3c737fbb Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 25 Jun 2026 10:43:43 -0700 Subject: [PATCH 26/35] ArrivalVisitor::srch_adj_ -> search_adj_ Signed-off-by: James Cherry --- include/sta/Search.hh | 2 +- search/Search.cc | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 7cfefde1..539c9895 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -809,7 +809,7 @@ protected: bool clks_only_; TagGroupBldr *tag_bldr_; TagGroupBldr *tag_bldr_no_crpr_; - SearchPred *srch_adj_; + SearchPred *search_adj_; bool crpr_active_; bool has_fanin_one_; }; diff --git a/search/Search.cc b/search/Search.cc index 27d196e1..879c1247 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -1092,7 +1092,7 @@ ArrivalVisitor::init0() { tag_bldr_ = new TagGroupBldr(true, this); tag_bldr_no_crpr_ = new TagGroupBldr(false, this); - srch_adj_ = new SearchAdjLoop(this); + search_adj_ = new SearchAdjLoop(this); } void @@ -1116,14 +1116,14 @@ void ArrivalVisitor::copyState(const StaState *sta) { StaState::copyState(sta); - srch_adj_->copyState(sta); + search_adj_->copyState(sta); } ArrivalVisitor::~ArrivalVisitor() { delete tag_bldr_; delete tag_bldr_no_crpr_; - delete srch_adj_; + delete search_adj_; } void @@ -1178,7 +1178,7 @@ ArrivalVisitor::visit(Vertex *vertex, search_->postponeClkFanouts(vertex); } else { - graph_->visitFanoutEdges(vertex, srch_adj_, + graph_->visitFanoutEdges(vertex, search_adj_, [this] (Edge *edge, Vertex *fanout) { if (edge->isDisabledLoop()) { From 666b9214d01460024ece9edebb61986b7d084633 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 25 Jun 2026 16:50:43 -0700 Subject: [PATCH 27/35] LibertyWriter::writeBusDcls() resolves #436 Signed-off-by: James Cherry --- liberty/LibertyWriter.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liberty/LibertyWriter.cc b/liberty/LibertyWriter.cc index ab8b8177..695b2ccb 100644 --- a/liberty/LibertyWriter.cc +++ b/liberty/LibertyWriter.cc @@ -275,7 +275,7 @@ LibertyWriter::writeBusDcls() sta::print(stream_, " type (\"{}\") {{\n", dcl->name()); sta::print(stream_, " base_type : array;\n"); sta::print(stream_, " data_type : bit;\n"); - sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to() + 1)); + sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to()) + 1); sta::print(stream_, " bit_from : {};\n", dcl->from()); sta::print(stream_, " bit_to : {};\n", dcl->to()); sta::print(stream_, " }}\n"); From 37b0b20a624d2b9b9cf0eaa8557fcb13235e015b Mon Sep 17 00:00:00 2001 From: Deepashree Sengupta Date: Thu, 25 Jun 2026 19:55:29 -0400 Subject: [PATCH 28/35] fix missing path issue (#452) Signed-off-by: dsengupta0628 --- include/sta/Sdc.hh | 1 + sdc/Sdc.cc | 12 +++ search/Sta.cc | 2 + test/input_delay_ref_pin_rebuild.ok | 112 +++++++++++++++++++++++++++ test/input_delay_ref_pin_rebuild.tcl | 28 +++++++ test/regression_vars.tcl | 1 + 6 files changed, 156 insertions(+) create mode 100644 test/input_delay_ref_pin_rebuild.ok create mode 100644 test/input_delay_ref_pin_rebuild.tcl diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh index 1ba41f91..a93569fe 100644 --- a/include/sta/Sdc.hh +++ b/include/sta/Sdc.hh @@ -577,6 +577,7 @@ public: const RiseFall *clk_rf, const MinMaxAll *min_max); void ensureInputDelayRefPinEdges(); + void inputDelayRefPinEdgesInvalid(); void setOutputDelay(const Pin *pin, const RiseFallBoth *rf, const Clock *clk, diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 088cc967..9b30c470 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -2840,6 +2840,18 @@ Sdc::ensureInputDelayRefPinEdges() } } +// The ref_pin edges are owned by the graph. When the graph is deleted the +// edges go with it, so the existence flags must be reset to force them to be +// rebuilt by ensureInputDelayRefPinEdges() with the new graph. +void +Sdc::inputDelayRefPinEdgesInvalid() +{ + if (have_input_delay_ref_pins_) { + for (InputDelay *input_delay : input_delays_) + input_delay->setRefPinEdgesExist(false); + } +} + //////////////////////////////////////////////////////////////// void diff --git a/search/Sta.cc b/search/Sta.cc index 19f3d994..435b8867 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -544,6 +544,8 @@ Sta::clearNonSdc() for (Mode *mode : modes_) { mode->clkNetwork()->clkPinsInvalid(); mode->sim()->clear(); + // ref_pin edges are owned by the graph deleted below; force a rebuild. + mode->sdc()->inputDelayRefPinEdgesInvalid(); } search_->clear(); diff --git a/test/input_delay_ref_pin_rebuild.ok b/test/input_delay_ref_pin_rebuild.ok new file mode 100644 index 00000000..97a18d36 --- /dev/null +++ b/test/input_delay_ref_pin_rebuild.ok @@ -0,0 +1,112 @@ +=== before rebuild: in1 (ref_pin) === +Startpoint: in1 (input port clocked by clk) +Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in1 (in) + 0.00 100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R) + 100.00 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + -11.41 488.59 library setup time + 488.59 data required time +--------------------------------------------------------- + 488.59 data required time + -100.00 data arrival time +--------------------------------------------------------- + 388.59 slack (MET) + + +=== before rebuild: in2 (control) === +Startpoint: in2 (input port clocked by clk) +Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in2 (in) + 0.00 100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R) + 100.00 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + -13.11 486.89 library setup time + 486.89 data required time +--------------------------------------------------------- + 486.89 data required time + -100.00 data arrival time +--------------------------------------------------------- + 386.89 slack (MET) + + +=== after rebuild: in1 (ref_pin) === +Startpoint: in1 (input port clocked by clk) +Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in1 (in) + 0.00 100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R) + 100.00 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + -11.41 488.59 library setup time + 488.59 data required time +--------------------------------------------------------- + 488.59 data required time + -100.00 data arrival time +--------------------------------------------------------- + 388.59 slack (MET) + + +=== after rebuild: in2 (control) === +Startpoint: in2 (input port clocked by clk) +Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 100.00 100.00 ^ input external delay + 0.00 100.00 ^ in2 (in) + 0.00 100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R) + 100.00 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + -13.11 486.89 library setup time + 486.89 data required time +--------------------------------------------------------- + 486.89 data required time + -100.00 data arrival time +--------------------------------------------------------- + 386.89 slack (MET) + + diff --git a/test/input_delay_ref_pin_rebuild.tcl b/test/input_delay_ref_pin_rebuild.tcl new file mode 100644 index 00000000..dcf0ac14 --- /dev/null +++ b/test/input_delay_ref_pin_rebuild.tcl @@ -0,0 +1,28 @@ +# set_input_delay -reference_pin must survive a graph rebuild that keeps SDC +# (resizer-like: sta::network_changed_non_sdc deletes the graph but not the +# constraints). The ref_pin->input graph edge is owned by the graph; its +# existence flag (PortDelay::ref_pin_edges_exist_) must be reset on graph +# teardown so ensureInputDelayRefPinEdges() rebuilds the edge. Otherwise in1 +# loses its arrival seeding and reports "No paths found" after the rebuild. +# in2 is a plain input delay (no ref_pin) used as a control. +read_liberty asap7_small.lib.gz +read_verilog reg1_asap7.v +link_design top + +create_clock -name clk -period 500 {clk1 clk2 clk3} +set_input_delay -clock clk 100 -reference_pin r2/CLK [get_ports in1] +set_input_delay -clock clk 100 [get_ports in2] +set_input_transition 10 {in1 in2 clk1 clk2 clk3} +set_output_delay -clock clk 1 [get_ports out] + +puts "=== before rebuild: in1 (ref_pin) ===" +report_checks -from in1 -path_delay max +puts "=== before rebuild: in2 (control) ===" +report_checks -from in2 -path_delay max + +sta::network_changed_non_sdc + +puts "=== after rebuild: in1 (ref_pin) ===" +report_checks -from in1 -path_delay max +puts "=== after rebuild: in2 (control) ===" +report_checks -from in2 -path_delay max diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index bf7e9faa..d1e30064 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -148,6 +148,7 @@ record_public_tests { get_lib_pins_of_objects get_noargs get_objrefs + input_delay_ref_pin_rebuild liberty_arcs_one2one_1 liberty_arcs_one2one_2 liberty_backslash_eol From 1796b158a2f5e5d61d32db16615a044c221566b3 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Fri, 26 Jun 2026 20:20:09 -0700 Subject: [PATCH 29/35] Graph member alignment Signed-off-by: James Cherry --- graph/Graph.cc | 31 +++++++++++++++---------------- include/sta/Graph.hh | 35 +++++++++++++++++------------------ search/Bfs.cc | 12 ++---------- 3 files changed, 34 insertions(+), 44 deletions(-) diff --git a/graph/Graph.cc b/graph/Graph.cc index e2123cf2..589e1fa0 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -50,9 +50,9 @@ namespace sta { Graph::Graph(StaState *sta, DcalcAPIndex ap_count) : StaState(sta), - ap_count_(ap_count), period_check_annotations_(network_), - reg_clk_vertices_(makeVertexSet(this)) + reg_clk_vertices_(makeVertexSet(this)), + ap_count_(ap_count) { // For the benifit of reg_clk_vertices_ that references graph_. graph_ = this; @@ -1040,22 +1040,22 @@ Vertex::init(Pin *pin, bool is_reg_clk) { pin_ = pin; - is_reg_clk_ = is_reg_clk; - is_bidirect_drvr_ = is_bidirect_drvr; in_edges_ = edge_id_null; out_edges_ = edge_id_null; slews_ = nullptr; paths_ = nullptr; tag_group_index_ = tag_group_index_max; - slew_annotated_ = false; + bfs_in_queue_ = 0; + is_bidirect_drvr_ = is_bidirect_drvr; + is_reg_clk_ = is_reg_clk; has_checks_ = false; is_check_clk_ = false; has_downstream_clk_pin_ = false; - level_ = 0; visited1_ = false; visited2_ = false; has_sim_value_ = false; - bfs_in_queue_ = 0; + level_ = 0; + slew_annotated_ = false; } Vertex::~Vertex() @@ -1281,20 +1281,19 @@ Edge::init(VertexId from, VertexId to, TimingArcSet *arc_set) { - from_ = from; - to_ = to; arc_set_ = arc_set; - vertex_in_next_ = edge_id_null; - vertex_out_next_ = edge_id_null; - vertex_out_prev_ = edge_id_null; - is_bidirect_inst_path_ = false; - is_bidirect_net_path_ = false; - is_bidirect_port_path_ = false; - arc_delays_ = nullptr; arc_delay_annotated_is_bits_ = true; arc_delay_annotated_.bits_ = 0; + from_ = from; + to_ = to; + vertex_in_next_ = edge_id_null; + vertex_out_next_ = edge_id_null; + vertex_out_prev_ = edge_id_null; delay_annotation_is_incremental_ = false; + is_bidirect_inst_path_ = false; + is_bidirect_net_path_ = false; + is_bidirect_port_path_ = false; is_disabled_loop_ = false; has_sim_sense_ = false; has_disabled_cond_ = false; diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index abe38883..e4a1be0a 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -192,7 +192,7 @@ public: VertexSet ®ClkVertices() { return reg_clk_vertices_; } static constexpr int vertex_level_bits = 24; - static constexpr int vertex_level_max = (1< bfs_in_queue_; // 8 - int level_:Graph::vertex_level_bits; // 24 - unsigned int slew_annotated_:slew_annotated_bits; // 4 // Bidirect pins have two vertices. // This flag distinguishes the driver and load vertices. - bool is_bidirect_drvr_:1; - - bool is_reg_clk_:1; + unsigned int is_bidirect_drvr_:1; + unsigned int is_reg_clk_:1; // Constrained by timing check edge. - bool has_checks_:1; + unsigned int has_checks_:1; // Is the clock for a timing check. - bool is_check_clk_:1; - bool has_downstream_clk_pin_:1; - bool visited1_:1; - bool visited2_:1; - bool has_sim_value_:1; + unsigned int is_check_clk_:1; + unsigned int has_downstream_clk_pin_:1; + unsigned int visited1_:1; + unsigned int visited2_:1; + unsigned int has_sim_value_:1; + int level_:Graph::vertex_level_bits; // 24 + unsigned int slew_annotated_:slew_annotated_bits; // 4 private: friend class Graph; @@ -405,16 +404,16 @@ protected: static uintptr_t arcDelayAnnotateBit(size_t index); TimingArcSet *arc_set_; - VertexId from_; - VertexId to_; - EdgeId vertex_in_next_; // Vertex in edges list. - EdgeId vertex_out_next_; // Vertex out edges doubly linked list. - EdgeId vertex_out_prev_; float *arc_delays_; union { uintptr_t bits_; std::vector *seq_; } arc_delay_annotated_; + VertexId from_; + VertexId to_; + EdgeId vertex_in_next_; // Vertex in edges list. + EdgeId vertex_out_next_; // Vertex out edges doubly linked list. + EdgeId vertex_out_prev_; bool arc_delay_annotated_is_bits_:1; bool delay_annotation_is_incremental_:1; bool is_bidirect_inst_path_:1; diff --git a/search/Bfs.cc b/search/Bfs.cc index 69b9c28b..ee099344 100644 --- a/search/Bfs.cc +++ b/search/Bfs.cc @@ -343,11 +343,7 @@ BfsIterator::remove(Vertex *vertex) BfsFwdIterator::BfsFwdIterator(BfsIndex bfs_index, SearchPred *search_pred, StaState *sta) : - BfsIterator(bfs_index, - 0, - level_max, - search_pred, - sta) + BfsIterator(bfs_index, 0, Graph::vertex_level_max, search_pred, sta) { } @@ -415,11 +411,7 @@ BfsFwdIterator::enqueueAdjacentVertices(Vertex *vertex, BfsBkwdIterator::BfsBkwdIterator(BfsIndex bfs_index, SearchPred *search_pred, StaState *sta) : - BfsIterator(bfs_index, - level_max, - 0, - search_pred, - sta) + BfsIterator(bfs_index, Graph::vertex_level_max, 0, search_pred, sta) { } From c222b49a7a25b6c33211ee02c55a64a20352deff Mon Sep 17 00:00:00 2001 From: James Cherry Date: Fri, 26 Jun 2026 21:11:13 -0700 Subject: [PATCH 30/35] ConcreteNetwork/Library member alignment Signed-off-by: James Cherry --- include/sta/ConcreteLibrary.hh | 4 ++-- include/sta/ConcreteNetwork.hh | 2 +- network/ConcreteLibrary.cc | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index 75018056..6d291700 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -81,12 +81,12 @@ protected: void removeCell(ConcreteCell *cell); std::string name_; - ObjectId id_; std::string filename_; + ConcreteCellMap cell_map_; + ObjectId id_; bool is_liberty_; char bus_brkt_left_{'['}; char bus_brkt_right_{']'}; - ConcreteCellMap cell_map_; private: friend class ConcreteCell; diff --git a/include/sta/ConcreteNetwork.hh b/include/sta/ConcreteNetwork.hh index 593c444c..cbbce614 100644 --- a/include/sta/ConcreteNetwork.hh +++ b/include/sta/ConcreteNetwork.hh @@ -366,10 +366,10 @@ protected: ConcretePort *port_; ConcreteNet *net_; ConcreteTerm *term_{nullptr}; - ObjectId id_; // Doubly linked list of net pins. ConcretePin *net_next_{nullptr}; ConcretePin *net_prev_{nullptr}; + ObjectId id_; VertexId vertex_id_{vertex_id_null}; private: diff --git a/network/ConcreteLibrary.cc b/network/ConcreteLibrary.cc index 77b335a1..45eff5b6 100644 --- a/network/ConcreteLibrary.cc +++ b/network/ConcreteLibrary.cc @@ -42,8 +42,8 @@ ConcreteLibrary::ConcreteLibrary(std::string_view name, std::string_view filename, bool is_liberty) : name_(name), - id_(ConcreteNetwork::nextObjectId()), filename_(filename), + id_(ConcreteNetwork::nextObjectId()), is_liberty_(is_liberty) { } From 3f5f18cb9bebbdf4701c3e86aaa5463eb0f2b3d9 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 27 Jun 2026 20:43:49 -0700 Subject: [PATCH 31/35] doc Signed-off-by: James Cherry --- doc/OpenSTA.fodt | 2615 +++++++++++++++++++++++----------------------- 1 file changed, 1309 insertions(+), 1306 deletions(-) diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index 318b70a0..3b13720c 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,24 +1,24 @@ - Parallax STA documentationJames Cherry5282025-03-17T12:59:52.4638705382010-07-31T21:07:002026-03-21T12:31:10.522816000P123DT2H14M54SLibreOffice/26.2.1.2$MacOSX_AARCH64 LibreOffice_project/8399f6259d8c87f40e7255cdb3c9b958f5e08948PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry5292025-03-17T12:59:52.4638705382010-07-31T21:07:002026-06-27T19:17:53.216896000P123DT2H17M23SLibreOffice/26.2.1.2$MacOSX_AARCH64 LibreOffice_project/8399f6259d8c87f40e7255cdb3c9b958f5e08948PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 2413538 + 2006224 0 30134 - 17268 + 16491 true false view2 - 18244 - 2424328 + 10537 + 2015716 0 - 2413538 + 2006224 30133 - 2430805 + 2022713 0 1 false @@ -92,7 +92,7 @@ false true false - 27556207 + 27679403 0 false @@ -5405,1080 +5405,1083 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + @@ -6614,98 +6617,98 @@ Variables85 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. Use the report_units command to see the ccmmand units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. read_liberty nangate45_slow.lib.gzread_liberty nangate45_typ.lib.gzread_liberty nangate45_fast.lib.gzread_verilog example1.link_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}define_scene ss -liberty nangate45_slowdefine_scene tt -liberty nangate45_typdefine_scene ff -liberty nangate45_fast# report all scenesreport_checks -path_delay min_max# report typical scenereport_checks -scene tt This example can be found in examples/multi_corner.tcl. Other examples can be found in the examples directory. - Timing Analysis with Multiple Corners and Modes + Timing Analysis with Multiple Corners and Modes OpenSTA supports multi-corner, multi-mode analysis. Each corner/mode combination is called a “scene”. The SDC constraints in each mode describe a different operating mode, such as mission mode or scan mode. Each corner has min/max Liberty libraries and SPEF parasitics. A mode named “default” is initially created for SDC commands. It is deleted when a mode is defined with set_mode or read_sdc -mode. Similartly, a named “default” is initially created that is deleted when define_scene is used to define a scene. An example command script using two process corners two modes is shown below. read_liberty asap7_small_ff.lib.gzread_liberty asap7_small_ss.lib.gzread_verilog reg1_asap7.vlink_design topread_sdc -mode mode1 mcmm2_mode1.sdcread_sdc -mode mode2 mcmm2_mode2.sdcread_spef -name reg1_ff reg1_asap7.spefread_spef -name reg1_ss reg1_asap7_ss.spefdefine_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ffdefine_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ssreport_checks -scenes scene1report_checks -scenes scene2report_checks -group_path_count 4 - This example can be found in examples/mcmm3.tcl.In the example show above the SDC for the modes is in separate files. Alternatively, the SDC can be defined in the command file using the set_mode command between SDC command groups. + This example can be found in examples/mcmm3.tcl.In the example show above the SDC for each mode is in defined in a separate file. Alternatively, the SDC can be defined in the command file using the set_mode command between SDC command groups. set_mode mode1create_clock -name m1_clk -period 1000 {clk1 clk2 clk3}set_input_delay -clock m1_clk 100 {in1 in2}set_mode mode2create_clock -name m2_clk -period 500 {clk1 clk3}set_output_delay -clock m2_clk 100 out Statistical Timing Analysis - OpenSTA also supports statistical timing analysis with Liberty Variation Format (LVF) libraries. Statistical timing uses a probability distribution to represent a delay or slew rather than a single number. + OpenSTA also supports statistical timing analysis with Liberty Variation Format (LVF) libraries. Statistical timing uses a probability distribution to represent a delay or slew rather than a single number. Normal and skew normal probability distributions are supported. SSTA is enabled with the sta_pocv_mode variable. - set sta_pocv_mode scalar|normal|skew_normalscalar mode is for non-SSTA analysisnormal mode uses gaussian normal distributionsskew_normal mode is for skew normal LVF moment based distributions + set sta_pocv_mode scalar|normal|skew_normalscalar mode is for non-SSTA analysisnormal mode uses gaussian normal distributionsskew_normal mode is for skew normal LVF moment based distributions The target quantile of a delay probability distribution (confidence level) is set with the sta_pocv_quantile variable. - set sta_pocv_quantile <float> + set sta_pocv_quantile <float> The default value is 3 standard deviations, or sigma. - Use the variation field with the report_checks and report_check_types commands to see distribution parameters in timing reports. + Use the variation field with the report_checks and report_check_types commands to see distribution parameters in timing reports. A command file for analyzing a design with statistical timing is shown below. read_liberty lvf_library.lib.gzread_verilog design.vlink_design topcreate_clock -period 50 clkset_input_delay -clock clk 1 {in1 in2}set sta_pocv_mode skew_normalreport_checks -fields {slew variation input_pin} -digits 3 - Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)Path Group: clkPath Type: max Slew Delay Variation Time Description--------------------------------------------------------------------------- 0.000 0.000 0.000 clock clk (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 0.000 ^ r2/CK (FDPQ1) 12.026 mean 0.017 mean_shift 0.366 std_dev 0.000 skewness 4.648 12.409 12.409 v r2/Q (FFQ1) 4.648 0.000 12.409 v u1/A (BUF1) 6.084 mean 0.007 mean_shift 0.188 std_dev 0.000 skewness 2.513 6.137 18.546 v u1/X (BUF1) 2.513 0.000 18.546 v u2/A2 (AN21) 6.447 mean 0.008 mean_shift 0.191 std_dev 0.000 skewness 2.565 6.497 25.043 v u2/X (AN21) 2.565 0.000 25.043 v r3/D (FFQ1) 25.043 data arrival time 0.000 50.000 50.000 clock clk (rise edge) 0.000 50.000 clock network delay (ideal) 0.000 50.000 clock reconvergence pessimism 50.000 ^ r3/CK (FFQ1) -9.376 40.624 library setup time 40.624 data required time--------------------------------------------------------------------------- 40.624 data required time -25.043 data arrival time--------------------------------------------------------------------------- 15.581 slack (MET) - The standard deviation for normal distributions is specified with the following liberty timing groups. + Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)Path Group: clkPath Type: max Slew Delay Variation Time Description--------------------------------------------------------------------------- 0.000 0.000 0.000 clock clk (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 0.000 ^ r2/CK (FDPQ1) 12.026 mean 0.017 mean_shift 0.366 std_dev 0.000 skewness 4.648 12.409 12.409 v r2/Q (FFQ1) 4.648 0.000 12.409 v u1/A (BUF1) 6.084 mean 0.007 mean_shift 0.188 std_dev 0.000 skewness 2.513 6.137 18.546 v u1/X (BUF1) 2.513 0.000 18.546 v u2/A2 (AN21) 6.447 mean 0.008 mean_shift 0.191 std_dev 0.000 skewness 2.565 6.497 25.043 v u2/X (AN21) 2.565 0.000 25.043 v r3/D (FFQ1) 25.043 data arrival time 0.000 50.000 50.000 clock clk (rise edge) 0.000 50.000 clock network delay (ideal) 0.000 50.000 clock reconvergence pessimism 50.000 ^ r3/CK (FFQ1) -9.376 40.624 library setup time 40.624 data required time--------------------------------------------------------------------------- 40.624 data required time -25.043 data arrival time--------------------------------------------------------------------------- 15.581 slack (MET) + The standard deviation for normal distributions is specified with the following liberty timing groups. ocv_sigma_cell_riseocv_sigma_cell_fallocv_sigma_rise_transitionocv_sigma_fall_transitionocv_sigma_rise_constraintocv_sigma_fall_constraint LVF skew normal distributions are specified with liberty groups below. - ocv_std_dev_cell_riseocv_std_dev_cell_fallocv_mean_shift_cell_riseocv_mean_shift_cell_fallocv_skewness_cell_riseocv_skewness_cell_fallocv_std_dev_rise_transitionocv_std_dev_fall_transitionocv_skewness_rise_transitionocv_skewness_fall_transitionocv_mean_shift_rise_transitionocv_mean_shift_fall_transitionocv_std_dev_rise_constraintocv_std_dev_fall_constraintocv_skewness_rise_constraintocv_skewness_fall_constraintocv_mean_shift_rise_constraintocv_mean_shift_fall_constraint + ocv_std_dev_cell_riseocv_std_dev_cell_fallocv_mean_shift_cell_riseocv_mean_shift_cell_fallocv_skewness_cell_riseocv_skewness_cell_fallocv_std_dev_rise_transitionocv_std_dev_fall_transitionocv_skewness_rise_transitionocv_skewness_fall_transitionocv_mean_shift_rise_transitionocv_mean_shift_fall_transitionocv_std_dev_rise_constraintocv_std_dev_fall_constraintocv_skewness_rise_constraintocv_skewness_fall_constraintocv_mean_shift_rise_constraintocv_mean_shift_fall_constraint - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power - In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power + In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. Group Internal Switching Leakage Total Power Power Power Power (Watts)----------------------------------------------------------------Sequential 3.27e-04 7.87e-05 2.96e-10 4.06e-04 36.4%Combinational 2.34e-04 3.10e-04 6.95e-10 5.43e-04 48.7%Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 15.0%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%----------------------------------------------------------------Total 6.07e-04 5.09e-04 1.01e-09 1.12e-03 100.0% 54.4% 45.6% 0.0% - This example can be found in examples/power.tcl. - Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. + This example can be found in examples/power.tcl. + Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. iverilog -o gcd_tb gcd_tb.vvvp gcd_tb - The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power - This example can be found in examples/power_vcd.tcl. + The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power + This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-scene scene] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-scene scene] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. - report_checks -to out1 > path.logreport_checks -to out2 >> path.log - Debugging Timing + Many reporting commands support redirection of the output to a file much like a Unix shell. + report_checks -to out1 > path.logreport_checks -to out2 >> path.log + Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. Debugging timing problems generally involves using the following commands to follow the propagation of arrival times from a known arrival downstream to understand why the arrival times are not propagating: report_edgesreport_arrivalsreport_net - report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. + report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. No paths found - The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. + The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. % report_checks -unconstrained If the design is sequential (has registers or latches) and no paths are reported, it is likely that there is a problem with the clock propagation. Check the timing at an register in the design with the report_arrivals command. % report_arrivals r1/CP (clk ^) r 0.00:0.00 f INF:-INF (clk v) r INF:-INF f 5.00:5.00 - In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. + In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. The clock path should be positive or negative unate. Something is probably wrong with the clock network if it is non-unate. A non-unate clock path will report arrivals similar to the foillowing: % report_arrivals r1/CP (clk ^) r 0.00:0.00 f 0.00:0.00 (clk v) r 5.00:5.00 f 5.00:5.00 Notice that each clock edge causes both rise and fall arrivals at the register clock pin. - If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. + If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. % report_edges -to r1/CPi1/ZN -> CP wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. + This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. No path reported an endpoint - In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. + In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. % report_edges -to r1/DCP -> D hold ^ -> ^ -0.04:-0.04 ^ -> v -0.03:-0.03CP -> D setup ^ -> ^ 0.09:0.0 ^ -> v 0.08:0.08in1 -> D wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This reports the setup and hold checks for the D pin of r1. + This reports the setup and hold checks for the D pin of r1. Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6718,7 +6721,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6739,7 +6742,7 @@ - all_outputs + all_outputs @@ -6753,15 +6756,15 @@ - all_registers + all_registers - [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] + [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] - -clock clock_names + -clock clock_names A list of clock names. Only registers clocked by these clocks are returned. @@ -6824,21 +6827,21 @@ - The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. + The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. - check_setup + check_setup - [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] + [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] - -verbose + -verbose Show offending objects rather than just error counts. @@ -6846,7 +6849,7 @@ - -unconstrained_endpoints + -unconstrained_endpoints Check path endpoints for timing constraints (timing check or set_output_delay). @@ -6854,7 +6857,7 @@ - -multiple_clock + -multiple_clock Check register/latch clock pins for multiple clocks. @@ -6871,7 +6874,7 @@ - -no_input_delay + -no_input_delay Check for inputs that do not have a set_input_delay command. @@ -6894,16 +6897,16 @@ - The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. + The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. - connect_pin + connect_pin - netport|pin + netport|pin @@ -6931,7 +6934,7 @@ - The connect_pin command connects a port or instance pin to a net. + The connect_pin command connects a port or instance pin to a net. @@ -6972,7 +6975,7 @@ -add - Add this clock to the clocks on pin_list. + Add this clock to the clocks on pin_list. @@ -6985,7 +6988,7 @@ The create_clock command defines the waveform of a clock used by the design. - If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. + If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. If no clock name is specified the name of the first pin is used as the clock name. If a wavform is not specified the clock rises at zero and falls at half the clock period. The waveform is a list with time the clock rises as the first element and the time it falls as the second element. If a clock is already defined on a pin the clock is redefined using the new clock parameters. If multiple clocks drive the same pin, use the -add option to prevent the existing definition from being overwritten. @@ -6998,10 +7001,10 @@ - create_generated_clock + create_generated_clock - [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list + [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -7017,36 +7020,36 @@ -source master_pin - A pin or port in the fanout of the master clock that is the source of the generated clock. + A pin or port in the fanout of the master clock that is the source of the generated clock. - -master_clock master_clock + -master_clock master_clock - Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. + Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. - -divide_by divisor + -divide_by divisor - Divide the master clock period by divisor. + Divide the master clock period by divisor. - -multiply_by multiplier + -multiply_by multiplier - Multiply the master clock period by multiplier. + Multiply the master clock period by multiplier. - -duty_cycle duty_cycle + -duty_cycle duty_cycle The percent of the period that the generated clock is high (between 0 and 100). @@ -7063,15 +7066,15 @@ - -edges edge_list + -edges edge_list - List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. + List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. - -edge_shift shift_list + -edge_shift shift_list Not supported. @@ -7082,7 +7085,7 @@ -add - Add this clock to the existing clocks on pin_list. + Add this clock to the existing clocks on pin_list. @@ -7090,7 +7093,7 @@ pin_list - A list of pins driven by the generated clock. + A list of pins driven by the generated clock. @@ -7115,10 +7118,10 @@ - create_voltage_area + create_voltage_area - [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells + [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -7128,7 +7131,7 @@ - current_design + current_design [design] @@ -7141,7 +7144,7 @@ - current_instance + current_instance [instance] @@ -7162,23 +7165,23 @@ - define_scene + define_scene - -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file + -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file - mode_name + mode_name - The SDC mode to use. + The SDC mode to use. - liberty_files + liberty_files List of Liberty files to use. @@ -7193,18 +7196,18 @@ - The define_scene command defines a scene for a mode (SDC), liberty files and spef parasitics. Define scenes after reading Liberty libraries and SPEF parasitics.Liberty files are specifiec with the name of the liberty library or the filename of the liberty file. If a filename is used, it must be the same as the filename used to read the library with read_liberty.. - Use get_scenes to find defined scenes. + The define_scene command defines a scene for a mode (SDC), liberty files and spef parasitics. Define scenes after reading Liberty libraries and SPEF parasitics.Liberty files are specifiec with the name of the liberty library or the filename of the liberty file. If a filename is used, it must be the same as the filename used to read the library with read_liberty.. + Use get_scenes to find defined scenes. - delete_clock + delete_clock - [-all] clocks + [-all] clocks @@ -7222,7 +7225,7 @@ - delete_from_list + delete_from_list list objects @@ -7233,7 +7236,7 @@ list - A list of objects. + A list of objects. @@ -7251,10 +7254,10 @@ - delete_generated_clock + delete_generated_clock - [-all] clocks + [-all] clocks @@ -7272,7 +7275,7 @@ - delete_instance + delete_instance instance @@ -7283,7 +7286,7 @@ instance - Instance to delete. + Instance to delete. @@ -7293,7 +7296,7 @@ - delete_net + delete_net net @@ -7301,7 +7304,7 @@ - net + net Net to delete. @@ -7314,10 +7317,10 @@ - disconnect_pin + disconnect_pin - netport | pin | -all + netport | pin | -all @@ -7360,7 +7363,7 @@ - elapsed_run_time + elapsed_run_time @@ -7373,83 +7376,83 @@ - find_timing_paths + find_timing_paths - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] - -from from_list + -from from_list - Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Return paths through a list of instances, pins or nets. + Return paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Return rising paths through a list of instances, pins or nets. + Return rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Return falling paths through a list of instances, pins or nets. + Return falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Return paths to a list of clocks, instances, ports or pins. + Return paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Return rising paths to a list of clocks, instances, ports or pins. + Return rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Return falling paths to a list of clocks, instances, ports or pins. + Return falling paths to a list of clocks, instances, ports or pins. @@ -7457,7 +7460,7 @@ -unconstrained - Report unconstrained paths also. + Report unconstrained paths also. @@ -7518,18 +7521,18 @@ - -group_path_count path_count + -group_path_count path_count - The number of paths to return in each path group. + The number of paths to return in each path group. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to return for each endpoint. + The number of paths to return for each endpoint. @@ -7542,7 +7545,7 @@ - -scene scene + -scene scene Return paths for one process corner. @@ -7550,18 +7553,18 @@ - -slack_max max_slack + -slack_max max_slack - Return paths with slack less than max_slack. + Return paths with slack less than max_slack. - -slack_min min_slack + -slack_min min_slack - Return paths with slack greater than min_slack. + Return paths with slack greater than min_slack. @@ -7569,15 +7572,15 @@ -sort_by_slack - Sort paths by slack rather than slack within path groups. + Sort paths by slack rather than slack within path groups. - -path_group groups + -path_group groups - Return paths in path groups. Paths in all groups are returned if this option is not specified. + Return paths in path groups. Paths in all groups are returned if this option is not specified. @@ -7587,10 +7590,10 @@ - get_cells + get_cells - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7603,18 +7606,18 @@ - -hsc separator + -hsc separator - Character to use to separate hierarchical instance names in patterns. + Character to use to separate hierarchical instance names in patterns. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7622,7 +7625,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7643,7 +7646,7 @@ - -of_objects objects + -of_objects objects The name of a pin or net, a list of pins returned by get_pins, or a list of nets returned by get_nets. The –hierarchical option cannot be used with ‑of_objects. @@ -7664,10 +7667,10 @@ - get_clocks + get_clocks - [-regexp][-nocase][-filter expr][-quiet]patterns + [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7675,7 +7678,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7689,10 +7692,10 @@ - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7718,15 +7721,15 @@ - get_fanin + get_fanin - -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -to sink_list + -to sink_list List of pins, ports, or nets to find the fanin of. For nets, the fanin of driver pins on the nets are returned. @@ -7734,7 +7737,7 @@ - -flat + -flat With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. @@ -7742,7 +7745,7 @@ - -only_cells + -only_cells Return the instances connected to the pins in the fanin. @@ -7750,7 +7753,7 @@ - -startpoints_only + -startpoints_only Only return pins that are startpoints. @@ -7758,7 +7761,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7774,15 +7777,15 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled Only trace through timing arcs that are not disabled. @@ -7790,7 +7793,7 @@ - -trace_arcs all + -trace_arcs all Trace through all arcs, including disabled ones. @@ -7804,15 +7807,15 @@ - get_fanout + get_fanout - -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -from source_list + -from source_list List of pins, ports, or nets to find the fanout of. For nets, the fanout of load pins on the nets are returned. @@ -7820,7 +7823,7 @@ - -flat + -flat With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. @@ -7828,7 +7831,7 @@ - -only_cells + -only_cells Return the instances connected to the pins in the fanout. @@ -7836,7 +7839,7 @@ - -endpoints_only + -endpoints_only Only return pins that are endpoints. @@ -7844,7 +7847,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7860,15 +7863,15 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled Only trace through timing arcs that are not disabled. @@ -7876,7 +7879,7 @@ - -trace_arcs all + -trace_arcs all Trace through all arcs, including disabled ones. @@ -7889,7 +7892,7 @@ - get_full_name + get_full_name object @@ -7914,12 +7917,12 @@ get_lib_cells - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - -of_objects objects + -of_objects objects A list of instance objects. @@ -7930,15 +7933,15 @@ -hsc separator - Character that separates the library name and cell name in patterns. Defaults to ‘/’. + Character that separates the library name and cell name in patterns. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7946,7 +7949,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7967,7 +7970,7 @@ - patterns + patterns A list of library cell name patterns of the form library_name/cell_name. @@ -7980,18 +7983,18 @@ - get_lib_pins + get_lib_pins - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - -of_objects objects + -of_objects objects - A list of library cell objects. + A list of library cell objects. @@ -7999,16 +8002,16 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8016,7 +8019,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8050,18 +8053,18 @@ - get_libs + get_libs - [-filter expr][-regexp][-nocase][-quiet]patterns + [-filter expr][-regexp][-nocase][-quiet]patterns - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8069,7 +8072,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8097,17 +8100,17 @@ - The get_libs command returns a list of clocks that match patterns. + The get_libs command returns a list of clocks that match patterns. - get_nets + get_nets - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8123,15 +8126,15 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8139,7 +8142,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8181,7 +8184,7 @@ - get_name + get_name object @@ -8203,10 +8206,10 @@ - get_pins + get_pins - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8222,15 +8225,15 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8254,7 +8257,7 @@ -of_objects objects - The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. + The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. @@ -8274,19 +8277,19 @@ - get_ports + get_ports - [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8294,7 +8297,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8315,10 +8318,10 @@ - -of_objects objects + -of_objects objects - The name of net or a list of nets returned by get_nets. + The name of net or a list of nets returned by get_nets. @@ -8336,18 +8339,18 @@ - get_property + get_property - [-object_type object_type]objectproperty + [-object_type object_type]objectproperty - -object_type object_type + -object_type object_type - The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc + The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc @@ -8355,7 +8358,7 @@ object - An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. + An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. @@ -8369,28 +8372,28 @@ The properties for different objects types are shown below. cell (SDC lib_cell) - base_namefilenamefull_namelibraryname + base_namefilenamefull_namelibraryname clock - full_nameis_generatedis_propagatedis_virtualnameperiodsources + full_nameis_generatedis_propagatedis_virtualnameperiodsources edge - delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin - instance (SDC cell) - cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name - liberty_cell (SDC lib_cell) - areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname - liberty_port (SDC lib_pin) - capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname + delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin + instance (SDC cell) + cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name + liberty_cell (SDC lib_cell) + areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname + liberty_port (SDC lib_pin) + capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname library - filename (Liberty library only)namefull_name + filename (Liberty library only)namefull_name net - full_namename + full_namename path (PathEnd) endpointendpoint_clockendpoint_clock_pinslackstartpointstartpoint_clockpoints pin - activity (activity in transitions per second, duty cycle, origin)origin is one ofglobalset_power_activity -globalinputset_power_activity -inputuserset_power_activity -input_ports -pinsvcdread_vcdsaifread_saifpropagatedpropagated from upstream activitiesclockSDC create_clock or create_generated_clockconstantconstant pins propagated from verilog tie high/low, set_case_analysis, set_logic_one/zero/dc - slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + activity (activity in transitions per second, duty cycle, origin)origin is one ofglobalset_power_activity -globalinputset_power_activity -inputuserset_power_activity -input_ports -pinsvcdread_vcdsaifread_saifpropagatedpropagated from upstream activitiesclockSDC create_clock or create_generated_clockconstantconstant pins propagated from verilog tie high/low, set_case_analysis, set_logic_one/zero/dc + slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise port - activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise point (PathRef) arrivalpinrequiredslack @@ -8398,15 +8401,15 @@ - get_scenes + get_scenes - [-mode mode_name]scene_name + [-mode mode_name]scene_name - mode_name + mode_name Get the scenes for mode_name. @@ -8414,7 +8417,7 @@ - scene_name + scene_name A scene name pattern. @@ -8427,61 +8430,61 @@ - get_timing_edges + get_timing_edges - [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] + [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] - -from from_pin + -from from_pin - A list of pins. + A list of pins. - -to to_pin + -to to_pin - A list of pins. + A list of pins. - -of_objects objects + -of_objects objects - A list of instances or library cells. The –from and -to options cannot be used with –of_objects. + A list of instances or library cells. The –from and -to options cannot be used with –of_objects. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. + The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. - group_path + group_path - -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] + -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] - -name group_name + -name group_name The name of the path group. @@ -8489,7 +8492,7 @@ - -weight weight + -weight weight Not supported. @@ -8497,7 +8500,7 @@ - -critical_range range + -critical_range range Not supported. @@ -8505,74 +8508,74 @@ - -from from_list + -from from_list - Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Group paths through a list of instances, pins or nets. + Group paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Group rising paths through a list of instances, pins or nets. + Group rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Group falling paths through a list of instances, pins or nets. + Group falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Group paths to a list of clocks, instances, ports or pins. + Group paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Group rising paths to a list of clocks, instances, ports or pins. + Group rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Group falling paths to a list of clocks, instances, port-s or pins. + Group falling paths to a list of clocks, instances, port-s or pins. @@ -8590,15 +8593,15 @@ - include + include - [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] + [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] - -echo|-e + -echo|-e Print each command before evaluating it. @@ -8606,7 +8609,7 @@ - -verbose|-v + -verbose|-v Print each command before evaluating it as well as the result it returns. @@ -8622,7 +8625,7 @@ - > log_filename + > log_filename Redirect command output to log_filename. @@ -8630,7 +8633,7 @@ - >> log_filename + >> log_filename Redirect command output and append log_filename. @@ -8638,29 +8641,29 @@ Read STA/SDC/Tcl commands from filename. - The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. + The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. - link_design + link_design - [-no_black_boxes][cell_name] + [-no_black_boxes][cell_name] - -no_black_boxes + -no_black_boxes - Do not make empty “black box” cells for instances that reference undefined cells. + Do not make empty “black box” cells for instances that reference undefined cells. - cell_name + cell_name The top level module/cell name of the design hierarchy to link. @@ -8675,7 +8678,7 @@ - make_instance + make_instance inst_pathlib_cell @@ -8699,13 +8702,13 @@ - The make_instance command makes an instance of library cell lib_cell. + The make_instance command makes an instance of library cell lib_cell. - make_net + make_net net_name_list @@ -8726,18 +8729,18 @@ - read_liberty + read_liberty - [-corner corner][-min][-max][-infer_latches]filename + [-corner corner][-min][-max][-infer_latches]filename - -corner corner + -corner corner - Use the library for process corner corner delay calculation. + Use the library for process corner corner delay calculation. @@ -8761,12 +8764,12 @@ filename - The liberty file name to read. + The liberty file name to read. The read_liberty command reads a Liberty format library file. The first library that is read sets the units used by SDC/TCL commands and reporting. The include_file attribute is supported. - Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: + Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} In this example a positive level-sensitive latch is inferred. Files compressed with gzip are automatically uncompressed. @@ -8775,18 +8778,18 @@ - read_saif + read_saif - [-scope scope]filename + [-scope scope]filename - scope + scope - The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. @@ -8794,26 +8797,26 @@ filename - The name of the SAIF file to read. + The name of the SAIF file to read. - The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_sdc + read_sdc - [-mode mode_name][-echo]filename + [-mode mode_name][-echo]filename - mode_name + mode_name Mode for the SDC commands in the file. @@ -8845,15 +8848,15 @@ - read_sdf + read_sdf - [-scene scene][-unescaped_dividers]filename + [-scene scene][-unescaped_dividers]filename - scene + scene Scene delays to annotate. @@ -8861,7 +8864,7 @@ - -unescaped_dividers + -unescaped_dividers With this option path names in the SDF do not have to escape hierarchy dividers when the path name is escaped. For example, the escaped Verilog name "\inst1/inst2 " can be referenced as "inst1/inst2". The correct SDF name is "inst1\/inst2", since the divider does not represent a change in hierarchy in this case. @@ -8876,7 +8879,7 @@ - Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. + Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. Files compressed with gzip are automatically uncompressed. INCREMENT is supported as an alias for INCREMENTAL. The following SDF statements are not supported. @@ -8886,10 +8889,10 @@ - read_spef + read_spef - [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename + [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename @@ -8905,7 +8908,7 @@ path - Hierarchical block instance path to annotate with parasitics. + Hierarchical block instance path to annotate with parasitics. @@ -8921,7 +8924,7 @@ ‑coupling_reduction_factorfactor - Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. + Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. @@ -8933,29 +8936,29 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. - Separate min/max parasitics can be annotated for each scene mode/corner. - read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max + Separate min/max parasitics can be annotated for each scene mode/corner. + read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. The following SPEF constructs are ignored. *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - read_vcd + read_vcd - [-scope scope][-mode mode_name]filename + [-scope scope][-mode mode_name]filename - scope + scope The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. @@ -8974,17 +8977,17 @@ filename - The name of the VCD file to read. + The name of the VCD file to read. - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog filename @@ -8999,8 +9002,8 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. - Verilog 2001 module port declaratations are supported. An example is shown below. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -9008,16 +9011,16 @@ - replace_cell + replace_cell - instance_listreplacement_cell + instance_listreplacement_cell - instance_list + instance_list A list of instances to swap the cell. @@ -9025,57 +9028,57 @@ - replacement_cell + replacement_cell The replacement lib cell. - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. - replace_activity_annotation + replace_activity_annotation - [-report_unannotated][-report_annotated] + [-report_unannotated][-report_annotated] - -report_unannotated + -report_unannotated - Report unannotated pins. + Report unannotated pins. - -report_unannotated + -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check - [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] + [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] - -setup + -setup Report annotated setup checks. @@ -9083,7 +9086,7 @@ - -hold + -hold Report annotated hold checks. @@ -9091,7 +9094,7 @@ - -recovery + -recovery Report annotated recovery checks. @@ -9099,7 +9102,7 @@ - -removal + -removal Report annotated removal checks. @@ -9107,7 +9110,7 @@ - -nochange + -nochange Report annotated nochange checks. @@ -9115,7 +9118,7 @@ - -width + -width Report annotated width checks. @@ -9123,7 +9126,7 @@ - -period + -period Report annotated period checks. @@ -9131,7 +9134,7 @@ - -max_skew + -max_skew Report annotated max skew checks. @@ -9140,26 +9143,26 @@ - -max_line lines + -max_line lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9171,21 +9174,21 @@ - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] - -cell + -cell Report annotated cell delays. @@ -9193,7 +9196,7 @@ - -net + -net Report annotated internal net delays. @@ -9201,7 +9204,7 @@ - -from_in_ports + -from_in_ports Report annotated delays from input ports. @@ -9209,7 +9212,7 @@ - -to_out_ports + -to_out_ports Report annotated delays to output ports. @@ -9217,26 +9220,26 @@ - -max_lines lines + -max_lines lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9248,90 +9251,90 @@ - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] - -from from_list + -from from_list - Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Report paths through a list of instances, pins or nets. + Report paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Report rising paths through a list of instances, pins or nets. + Report rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Report falling paths through a list of instances, pins or nets. + Report falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Report paths to a list of clocks, instances, ports or pins. + Report paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Report rising paths to a list of clocks, instances, ports or pins. + Report rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Report falling paths to a list of clocks, instances, ports or pins. + Report falling paths to a list of clocks, instances, ports or pins. @@ -9339,7 +9342,7 @@ -unconstrained - Report unconstrained paths also. The unconstrained path group is not reported without this option. + Report unconstrained paths also. The unconstrained path group is not reported without this option. @@ -9400,7 +9403,7 @@ - -group_path_count path_count + -group_path_count path_count The number of paths to report in each path group. The default is 1. @@ -9408,7 +9411,7 @@ - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count The number of paths to report for each endpoint. The default is 1. @@ -9419,15 +9422,15 @@ ‑unique_paths_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. - ‑unique_edges_to_endpoint + ‑unique_edges_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. @@ -9435,7 +9438,7 @@ scenes - Report paths for one process corner. The default is to report paths for all process corners. + Report paths for one process corner. The default is to report paths for all process corners. @@ -9465,10 +9468,10 @@ - groups + groups - List of path groups to report. The default is to report all path groups. + List of path groups to report. The default is to report all path groups. @@ -9521,10 +9524,10 @@ - -format json + -format json - Report in json format. -fields is ignored. + Report in json format. -fields is ignored. @@ -9532,7 +9535,7 @@ fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variation + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variation @@ -9552,7 +9555,7 @@ - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. See set_false_path for a description of allowed from_list, through_list and to_list objects. @@ -9560,10 +9563,10 @@ - report_check_types + report_check_types - [-scenes scenes][-violators][-verbose][-fields fields][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] + [-scenes scenes][-violators][-verbose][-fields fields][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] @@ -9571,12 +9574,12 @@ scenes - Report checks for some scenes. The default value is all scenes. + Report checks for some scenes. The default value is all scenes. - -violators + -violators Report all violated timing and design rule constraints. @@ -9592,18 +9595,18 @@ - -format slack_only + -format slack_only - Report the minimum slack for each timing check. + Report the minimum slack for each timing check. - -format end + -format end - Report the endpoint for each check. + Report the endpoint for each check. @@ -9611,7 +9614,7 @@ fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variation + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variation @@ -9705,7 +9708,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9726,10 +9729,10 @@ - report_clock_latency + report_clock_latency - [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] @@ -9737,7 +9740,7 @@ clocks - The clocks to report. The default value is all c + The clocks to report. The default value is all c @@ -9745,7 +9748,7 @@ scenes - Report clocks for scenes. The default value is all clocks in scenes modes. + Report clocks for scenes. The default value is all clocks in scenes modes. @@ -9771,10 +9774,10 @@ - report_clock_min_period + report_clock_min_period - [-clocks clocks][-scenes scenes][-include_port_paths] + [-clocks clocks][-scenes scenes][-include_port_paths] @@ -9794,16 +9797,16 @@ - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. - report_clock_properties + report_clock_properties - [clock_names] + [clock_names] @@ -9821,15 +9824,15 @@ - report_clock_skew + report_clock_skew - [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] - -setup + -setup Report skew for setup checks. @@ -9848,7 +9851,7 @@ clocks - The clocks to report. The default value is all clocks in scenes modes. + The clocks to report. The default value is all clocks in scenes modes. @@ -9856,7 +9859,7 @@ scenes - Report clocks for scenes. The default value is all scenes. + Report clocks for scenes. The default value is all scenes. @@ -9869,23 +9872,23 @@ - -digits digits + -digits digits The number of digits to report for delays. - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc - [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] + [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] @@ -9893,7 +9896,7 @@ from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. @@ -9901,7 +9904,7 @@ to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. @@ -9910,28 +9913,28 @@ scene - Report paths for process scene. The -scene keyword is required if more than one process corner is defined. + Report paths for process scene. The -scene keyword is required if more than one process corner is defined. - -min + -min - Report delay calculation for min delays. + Report delay calculation for min delays. - -max + -max - Report delay calculation for max delays. + Report delay calculation for max delays. - -digits digits + -digits digits The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9944,7 +9947,7 @@ - report_disabled_edges + report_disabled_edges @@ -9952,16 +9955,16 @@ The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges - [-from from_pin][-to to_pin][-report_variation][-digits digits] + [-from from_pin][-to to_pin][-report_variation][-digits digits] @@ -9969,7 +9972,7 @@ from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. @@ -9977,7 +9980,7 @@ to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. @@ -9997,17 +10000,17 @@ - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance - instance_path[> filename][>> filename] + instance_path[> filename][>> filename] @@ -10025,10 +10028,10 @@ - report_lib_cell + report_lib_cell - cell_name[> filename][>> filename] + cell_name[> filename][>> filename] @@ -10040,16 +10043,16 @@ - Describe the liberty library cell cell_name. + Describe the liberty library cell cell_name. - report_net + report_net - [-digits digits]net_path[> filename][>> filename] + [-digits digits]net_path[> filename][>> filename] @@ -10075,10 +10078,10 @@ - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] @@ -10096,50 +10099,50 @@ - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] - -instances instances + -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_slews + report_slews - [-scenes scenes][-report_variation][-digits digits]pin + [-scenes scenes][-report_variation][-digits digits]pin @@ -10147,7 +10150,7 @@ scenes - Report slews for process for scenes process corners. + Report slews for process for scenes process corners. @@ -10160,10 +10163,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10182,10 +10185,10 @@ - report_tns + report_tns - [-min][-max][-digits digits] + [-min][-max][-digits digits] @@ -10193,7 +10196,7 @@ -max - Report the total max/setup slack. + Report the total max/setup slack. @@ -10201,12 +10204,12 @@ -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10219,24 +10222,24 @@ - report_units + report_units - Report the units used for command arguments and reporting. + Report the units used for command arguments and reporting. report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um - report_wns + report_wns - [-min][-max][-digits digits] + [-min][-max][-digits digits] @@ -10244,7 +10247,7 @@ -max - Report the worst max/setup slack. + Report the worst max/setup slack. @@ -10252,12 +10255,12 @@ -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10270,10 +10273,10 @@ - report_worst_slack + report_worst_slack - [-min][-max][-digits digits] + [-min][-max][-digits digits] @@ -10282,7 +10285,7 @@ -max - Report the worst max/setup slack. + Report the worst max/setup slack. @@ -10290,12 +10293,12 @@ -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10308,10 +10311,10 @@ - set_assigned_check + set_assigned_check - -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin + -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -10319,7 +10322,7 @@ -setup - Annotate setup timing checks. + Annotate setup timing checks. @@ -10327,7 +10330,7 @@ -hold - Annotate hold timing checks. + Annotate hold timing checks. @@ -10335,7 +10338,7 @@ -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. @@ -10343,7 +10346,7 @@ -removal - Annotate removal timing checks. + Annotate removal timing checks. @@ -10405,10 +10408,10 @@ - -clock rise|fall + -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. @@ -10416,7 +10419,7 @@ margin - The timing check margin. + The timing check margin. @@ -10426,10 +10429,10 @@ - set_assigned_delay + set_assigned_delay - -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay + -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay @@ -10520,10 +10523,10 @@ - set_assigned_transition + set_assigned_transition - [-rise][-fall][-scene scene][-min][-max]slewpin_list + [-rise][-fall][-scene scene][-min][-max]slewpin_list @@ -10547,7 +10550,7 @@ scene - Annotate delays for scene. + Annotate delays for scene. @@ -10589,10 +10592,10 @@ - set_case_analysis + set_case_analysis - 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list + 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10611,16 +10614,16 @@ - set_clock_gating_check + set_clock_gating_check - [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] + [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] - -setup setup_time + -setup setup_time Clock enable setup margin. @@ -10628,7 +10631,7 @@ - -hold hold_time + -hold hold_time Clock enable hold margin. @@ -10685,18 +10688,18 @@ - set_clock_groups + set_clock_groups - [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks + [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks - -name name + -name name - The clock group name. + The clock group name. @@ -10704,7 +10707,7 @@ -logically_exclusive - The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. + The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. @@ -10713,7 +10716,7 @@ -physically_exclusive - The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. + The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. @@ -10721,7 +10724,7 @@ -asynchronous - The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. + The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. @@ -10734,7 +10737,7 @@ - clocks + clocks A list of clocks in the group. @@ -10747,15 +10750,15 @@ - set_clock_latency + set_clock_latency - [-source][-clock clock][-rise][-fall][-min][-max]delayobjects + [-source][-clock clock][-rise][-fall][-min][-max]delayobjects - -source + -source The latency is at the clock source. @@ -10763,7 +10766,7 @@ - -clock clock + -clock clock If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. @@ -10818,16 +10821,16 @@ - The set_clock_latency command describes expected delays of the clock tree when anxsalyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function.set_clock_latency removes propagated clock properties for the clocks and pins objects. + The set_clock_latency command describes expected delays of the clock tree when anxsalyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function.set_clock_latency removes propagated clock properties for the clocks and pins objects. - set_clock_transition + set_clock_transition - [-rise][-fall][-min][-max]transitionclocks + [-rise][-fall][-min][-max]transitionclocks @@ -10835,7 +10838,7 @@ -rise - Set the transition time for the rising edge of the clock. + Set the transition time for the rising edge of the clock. @@ -10843,7 +10846,7 @@ -fall - Set the transition time for the falling edge of the clock. + Set the transition time for the falling edge of the clock. @@ -10851,7 +10854,7 @@ -min - Set the min transition time. + Set the min transition time. @@ -10859,7 +10862,7 @@ -max - Set the min transition time. + Set the min transition time. @@ -10885,15 +10888,15 @@ - set_clock_uncertainty + set_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] - -from from_clock + -from from_clock Inter-clock uncertainty source clock. @@ -10901,7 +10904,7 @@ - -to to_clock + -to to_clock Inter-clock uncertainty target clock. @@ -10912,7 +10915,7 @@ -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. @@ -10920,7 +10923,7 @@ -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. @@ -10928,7 +10931,7 @@ -setup - uncertainty is for setup checks. + uncertainty is for setup checks. @@ -10937,7 +10940,7 @@ -hold - uncertainty is for hold checks. + uncertainty is for hold checks. @@ -10957,26 +10960,26 @@ - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit The capacitance scale factor followed by 'f'. @@ -10984,7 +10987,7 @@ - -resistance res_unit + -resistance res_unit The resistance scale factor followed by 'ohm'. @@ -10992,7 +10995,7 @@ - -time time_unit + -time time_unit The time scale factor followed by 's'. @@ -11000,15 +11003,15 @@ - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit The current scale factor followed by 'A'. @@ -11016,7 +11019,7 @@ - -power power_unit + -power power_unit The power scale factor followed by 'w'. @@ -11024,14 +11027,14 @@ - -distance distance_unit + -distance distance_unit The distance scale factor followed by 'm'. - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -11041,15 +11044,15 @@ - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin A pin used as the timing check reference. @@ -11057,7 +11060,7 @@ - -to to_pin + -to to_pin A pin that the setup/hold check is applied to. @@ -11081,7 +11084,7 @@ - -clock clock + -clock clock The setup/hold check clock. @@ -11102,7 +11105,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -11117,21 +11120,21 @@ - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. - set_disable_timing + set_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects - -from from_port + -from from_port @@ -11139,7 +11142,7 @@ - -to to_port + -to to_port @@ -11150,12 +11153,12 @@ objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. - All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. + All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. set_disable_timing u2 The -from and -to options can be used to restrict the disabled path to those from, to or between specific pins on the instance. set_disable_timing -from A u2set_disable_timing -to Z u2set_disable_timing -from A -to Z u2 @@ -11168,10 +11171,10 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports @@ -11195,7 +11198,7 @@ -max - Set the maximum resistance. + Set the maximum resistance. @@ -11203,7 +11206,7 @@ -min - Set the minimum resistance. + Set the minimum resistance. @@ -11216,7 +11219,7 @@ - ports + ports A list of ports. @@ -11229,15 +11232,15 @@ - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports - -lib_cell cell_name + -lib_cell cell_name The driving cell. @@ -11245,10 +11248,10 @@ - -library library + -library library - The driving cell library. + The driving cell library. @@ -11256,7 +11259,7 @@ -rise - Set the driving cell for a rising edge. + Set the driving cell for a rising edge. @@ -11265,7 +11268,7 @@ -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. @@ -11273,7 +11276,7 @@ -max - Set the driving cell for max delays. + Set the driving cell for max delays. @@ -11281,12 +11284,12 @@ -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin The output port of the driving cell. @@ -11294,31 +11297,31 @@ - -from_pin from_pin + -from_pin from_pin - Use timing arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. - -input_transition_rise trans_rise + -input_transition_rise trans_rise - The transition time for a rising input at from_pin. + The transition time for a rising input at from_pin. - -input_transition_fall trans_fall + -input_transition_fall trans_fall - The transition time for a falling input at from_pin. + The transition time for a falling input at from_pin. - ports + ports A list of ports. @@ -11331,10 +11334,10 @@ - set_false_path + set_false_path - [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] + [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -11342,7 +11345,7 @@ -setup - Apply to setup checks. + Apply to setup checks. @@ -11350,7 +11353,7 @@ -hold - Apply to hold checks. + Apply to hold checks. @@ -11358,7 +11361,7 @@ -rise - Apply to rising path edges. + Apply to rising path edges. @@ -11366,7 +11369,7 @@ -fall - Apply to falling path edges. + Apply to falling path edges. @@ -11380,7 +11383,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11388,7 +11391,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11396,7 +11399,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11412,10 +11415,10 @@ - set_fanout_load + set_fanout_load - fanoutport_list + fanoutport_list @@ -11425,7 +11428,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11446,7 +11449,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11459,7 +11462,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11472,7 +11475,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11485,10 +11488,10 @@ - set_input_delay + set_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11496,7 +11499,7 @@ -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. @@ -11504,7 +11507,7 @@ -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. @@ -11512,7 +11515,7 @@ -max - Set the maximum arrival time. + Set the maximum arrival time. @@ -11520,15 +11523,15 @@ -min - Set the minimum arrival time. + Set the minimum arrival time. - -clock clock + -clock clock - The arrival time is from clock. + The arrival time is from clock. @@ -11536,12 +11539,12 @@ -clock_fall - The arrival time is from the falling edge of clock. + The arrival time is from the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin The arrival time is with respect to the clock that arrives at ref_pin. @@ -11552,7 +11555,7 @@ -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. @@ -11560,7 +11563,7 @@ -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. @@ -11589,21 +11592,21 @@ The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - set_input_transition + set_input_transition - [-rise][-fall][-max][-min]transitionport_list + [-rise][-fall][-max][-min]transitionport_list @@ -11611,7 +11614,7 @@ -rise - Set the rising edge transition. + Set the rising edge transition. @@ -11619,7 +11622,7 @@ -fall - Set the falling edge transition. + Set the falling edge transition. @@ -11627,7 +11630,7 @@ -max - Set the minimum transition time. + Set the minimum transition time. @@ -11635,7 +11638,7 @@ -min - Set the maximum transition time. + Set the maximum transition time. @@ -11661,10 +11664,10 @@ - set_level_shifter_strategy + set_level_shifter_strategy - [-rule rule_type] + [-rule rule_type] @@ -11675,10 +11678,10 @@ - set_level_shifter_threshold + set_level_shifter_threshold - [-voltage voltage] + [-voltage voltage] @@ -11688,10 +11691,10 @@ - set_load + set_load - [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects + [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11699,7 +11702,7 @@ -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). @@ -11707,7 +11710,7 @@ -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). @@ -11715,7 +11718,7 @@ -max - Set the max capacitance. + Set the max capacitance. @@ -11723,7 +11726,7 @@ -min - Set the min capacitance. + Set the min capacitance. @@ -11731,7 +11734,7 @@ -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. @@ -11767,24 +11770,24 @@ - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. @@ -11797,57 +11800,57 @@ - set_logic_one + set_logic_one - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - set_logic_zero + set_logic_zero - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area - area + area - area + area @@ -11860,15 +11863,15 @@ - set_max_capacitance + set_max_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance @@ -11877,7 +11880,7 @@ - objects + objects List of ports or cells. @@ -11890,10 +11893,10 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11901,7 +11904,7 @@ -rise - Set max delay for rising paths. + Set max delay for rising paths. @@ -11909,12 +11912,12 @@ -fall - Set max delay for falling paths. + Set max delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11922,7 +11925,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11930,7 +11933,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11946,7 +11949,7 @@ - -probe + -probe Do not break paths at internal pins (non startpoints). @@ -11976,10 +11979,10 @@ - set_max_dynamic_power + set_max_dynamic_power - power [unit] + power [unit] @@ -11989,15 +11992,15 @@ - set_max_fanout + set_max_fanout - fanoutobjects + fanoutobjects - fanout + fanout @@ -12005,7 +12008,7 @@ - objects + objects List of ports or cells. @@ -12018,10 +12021,10 @@ - set_max_leakage_power + set_max_leakage_power - power [unit] + power [unit] @@ -12031,15 +12034,15 @@ - set_max_time_borrow + set_max_time_borrow - delayobjects + delayobjects - delay + delay The maximum time the latches can borrow. @@ -12047,23 +12050,23 @@ - objects + objects List of clocks, instances or pins. - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition - [-data_path][-clock_path][-rise][-fall]transitionobjects + [-data_path][-clock_path][-rise][-fall]transitionobjects @@ -12101,22 +12104,22 @@ - transition + transition - The maximum slew/transition time. + The maximum slew/transition time. - objects + objects List of clocks, ports or designs. - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -12124,23 +12127,23 @@ - set_min_capacitance + set_min_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance - Minimum capacitance. + Minimum capacitance. - objects + objects List of ports or cells. @@ -12153,10 +12156,10 @@ - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -12164,7 +12167,7 @@ -rise - Set min delay for rising paths. + Set min delay for rising paths. @@ -12173,12 +12176,12 @@ -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12186,7 +12189,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12194,7 +12197,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12210,7 +12213,7 @@ - -probe + -probe Do not break paths at internal pins (non startpoints). @@ -12229,7 +12232,7 @@ delay - The minimum delay. + The minimum delay. @@ -12240,10 +12243,10 @@ - set_min_pulse_width + set_min_pulse_width - [-high][-low]min_widthobjects + [-high][-low]min_widthobjects @@ -12264,7 +12267,7 @@ - min_width + min_width @@ -12272,7 +12275,7 @@ - objects + objects List of pins, instances or clocks. @@ -12285,24 +12288,24 @@ - set_mode + set_mode - mode_name + mode_name - The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. + Set the mode for SDC commands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. - set_multicycle_path + set_multicycle_path - [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier + [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -12310,7 +12313,7 @@ -setup - Set cycle count for setup checks. + Set cycle count for setup checks. @@ -12318,7 +12321,7 @@ -hold - Set cycle count for hold checks. + Set cycle count for hold checks. @@ -12326,7 +12329,7 @@ -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. @@ -12334,7 +12337,7 @@ -fall - Set cycle count for falling path edges. + Set cycle count for falling path edges. @@ -12355,7 +12358,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12363,7 +12366,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12371,7 +12374,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12401,7 +12404,7 @@ - set_operating_conditions + set_operating_conditions [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] @@ -12433,7 +12436,7 @@ - -library lib + -library lib The name of the library that contains condition. @@ -12449,7 +12452,7 @@ - -min min_condition + -min min_condition The operating condition to use for min paths and hold checks. @@ -12457,7 +12460,7 @@ - -max max_condition + -max max_condition The operating condition to use for max paths and setup checks. @@ -12465,18 +12468,18 @@ - -min_library min_lib + -min_library min_lib - The name of the library that contains min_condition. + The name of the library that contains min_condition. - -max_library max_lib + -max_library max_lib - The name of the library that contains max_condition. + The name of the library that contains max_condition. @@ -12486,10 +12489,10 @@ - set_output_delay + set_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -12498,7 +12501,7 @@ -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. @@ -12506,7 +12509,7 @@ -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. @@ -12514,7 +12517,7 @@ -max - Set the maximum output delay. + Set the maximum output delay. @@ -12522,15 +12525,15 @@ -min - Set the minimum output delay. + Set the minimum output delay. - -clock clock + -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. @@ -12538,15 +12541,15 @@ -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. @@ -12554,7 +12557,7 @@ -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. @@ -12562,7 +12565,7 @@ delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. @@ -12574,33 +12577,33 @@ - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports - -min + -min - Set the min fanout. + Set the min fanout. - -max + -max - Set the max fanout. + Set the max fanout. @@ -12626,15 +12629,15 @@ - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global Set the activity/duty for all non-clock pins. @@ -12650,7 +12653,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -12658,7 +12661,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -12666,15 +12669,15 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -density density + -density density Transitions per library time unit. @@ -12682,30 +12685,30 @@ - -duty duty + -duty duty - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -clock clock + -clock clock The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock objects @@ -12727,11 +12730,11 @@ - set_pvt + set_pvt - [-min][-max][-process process][-voltage voltage] - [-temperature temperature]instances + [-min][-max][-process process][-voltage voltage] + [-temperature temperature]instances @@ -12739,7 +12742,7 @@ -min - Set the PVT values for max delays. + Set the PVT values for max delays. @@ -12747,12 +12750,12 @@ -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process A process value (float). @@ -12760,7 +12763,7 @@ - -voltage voltage + -voltage voltage A voltage value (float). @@ -12768,7 +12771,7 @@ - -temperature temperature + -temperature temperature A temperature value (float). @@ -12789,15 +12792,15 @@ - set_sense + set_sense - [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins + [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins - -type clock + -type clock Set the sense for clock paths. @@ -12805,7 +12808,7 @@ - -type data + -type data Set the sense for data paths (not supported). @@ -12813,35 +12816,35 @@ - -positive + -positive - The clock sense is positive unate. + The clock sense is positive unate. - -negative + -negative - The clock sense is negative unate. + The clock sense is negative unate. - -pulse pulse_type + -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. - -stop_propagation + -stop_propagation - Stop propagating clocks at pins. + Stop propagating clocks at pins. @@ -12849,7 +12852,7 @@ clocks - A list of clocks to apply the sense. + A list of clocks to apply the sense. @@ -12861,21 +12864,21 @@ - The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. + The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. - set_timing_derate + set_timing_derate - [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] + [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] - -rise + -rise Set the derating for rising delays. @@ -12883,7 +12886,7 @@ - -fall + -fall Set the derating for falling delays. @@ -12891,7 +12894,7 @@ - -early + -early Derate early (min) paths. @@ -12899,7 +12902,7 @@ - -late + -late Derate late (max) paths. @@ -12907,7 +12910,7 @@ - -clock + -clock Derate paths in the clock network. @@ -12915,7 +12918,7 @@ - -data + -data Derate data paths. @@ -12923,7 +12926,7 @@ - -net_delay + -net_delay Derate net (interconnect) delays. @@ -12932,7 +12935,7 @@ - -cell_delay + -cell_delay Derate cell delays. @@ -12940,7 +12943,7 @@ - -cell_check + -cell_check Derate cell timing check margins. @@ -12951,7 +12954,7 @@ derate - The derating factor to apply to delays. + The derating factor to apply to delays. @@ -12970,15 +12973,15 @@ - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets - -min + -min The resistance for minimum path delay calculation. @@ -12986,7 +12989,7 @@ - -max + -max The resistance for maximum path delay calculation. @@ -13002,7 +13005,7 @@ - nets + nets A list of nets. @@ -13015,10 +13018,10 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] @@ -13071,7 +13074,7 @@ - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -13081,7 +13084,7 @@ - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -13094,10 +13097,10 @@ - set_wire_load_mode + set_wire_load_mode - top|enclosed|segmented + top|enclosed|segmented @@ -13131,16 +13134,16 @@ - set_wire_load_model + set_wire_load_model - -name model_name[-library library][-max][-min][objects] + -name model_name[-library library][-max][-min][objects] - -name model_name + -name model_name The name of a wire load model. @@ -13148,7 +13151,7 @@ - -library library + -library library Library to look for model_name. @@ -13185,10 +13188,10 @@ - set_wire_load_selection_group + set_wire_load_selection_group - [-library library][-max][-min]group_name[objects] + [-library library][-max][-min]group_name[objects] @@ -13196,7 +13199,7 @@ library - Library to look for group_name. + Library to look for group_name. @@ -13220,7 +13223,7 @@ group_name - A wire load selection group name. + A wire load selection group name. @@ -13238,28 +13241,28 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -13280,18 +13283,18 @@ - unset_clock_latency + unset_clock_latency - [-source]objects + [-source]objects - -source + -source - Specifies source clock latency (clock insertion delay). + Specifies source clock latency (clock insertion delay). @@ -13309,7 +13312,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -13330,15 +13333,15 @@ - unset_clock_uncertainty + unset_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] - -from from_clock + -from from_clock @@ -13346,7 +13349,7 @@ - -to to_clock + -to to_clock @@ -13373,7 +13376,7 @@ -setup - uncertainty is the setup check uncertainty. + uncertainty is the setup check uncertainty. @@ -13381,7 +13384,7 @@ -hold - uncertainty is the hold uncertainty. + uncertainty is the hold uncertainty. @@ -13407,15 +13410,15 @@ - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] - -from from_object + -from from_object A pin used as the timing check reference. @@ -13460,7 +13463,7 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13475,16 +13478,16 @@ - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects @@ -13519,10 +13522,10 @@ - unset_input_delay + unset_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13530,7 +13533,7 @@ -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. @@ -13538,7 +13541,7 @@ -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. @@ -13546,7 +13549,7 @@ -max - Unset the minimum arrival time. + Unset the minimum arrival time. @@ -13554,7 +13557,7 @@ -min - Unset the maximum arrival time. + Unset the maximum arrival time. @@ -13562,7 +13565,7 @@ clock - Unset the arrival time from clock. + Unset the arrival time from clock. @@ -13570,7 +13573,7 @@ -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock @@ -13588,10 +13591,10 @@ - unset_output_delay + unset_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13640,7 +13643,7 @@ -clock_fall - The arrival time is from the falling edge of clock + The arrival time is from the falling edge of clock @@ -13658,10 +13661,10 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13669,7 +13672,7 @@ -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. @@ -13677,7 +13680,7 @@ -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. @@ -13685,7 +13688,7 @@ -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. @@ -13693,12 +13696,12 @@ -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13706,7 +13709,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13714,7 +13717,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13728,15 +13731,15 @@ - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global Set the activity/duty for all non-clock pins. @@ -13752,7 +13755,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -13761,7 +13764,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -13769,10 +13772,10 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. @@ -13782,7 +13785,7 @@ - unset_propagated_clock + unset_propagated_clock objects @@ -13803,7 +13806,7 @@ - unset_timing_derate + unset_timing_derate @@ -13816,28 +13819,28 @@ - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time @@ -13850,10 +13853,10 @@ - with_output_to_variable + with_output_to_variable - var { commands } + var { commands } @@ -13873,17 +13876,17 @@ - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. - write_path_spice + write_path_spice - -path_args path_args-spice_file spice_file-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_file spice_file-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] @@ -13896,10 +13899,10 @@ - spice_file + spice_file - Directory and path prefix for spice output files. + Directory and path prefix for spice output files. @@ -13915,7 +13918,7 @@ model_file - Transistor model definitions .included by spice_file. + Transistor model definitions .included by spice_file. @@ -13936,7 +13939,7 @@ - -simulator + -simulator Simulator that will read the spice netlist. @@ -13954,10 +13957,10 @@ - write_sdc + write_sdc - [-digits digits][-gzip][-no_timestamp]filename + [-digits digits][-gzip][-no_timestamp]filename @@ -13974,7 +13977,7 @@ -gzip - Compress the SDC with gzip. + Compress the SDC with gzip. @@ -14000,18 +14003,18 @@ - write_sdf + write_sdf - [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename + [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename - scene + scene - Write delays for scene. + Write delays for scene. @@ -14032,7 +14035,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default is 4. @@ -14043,7 +14046,7 @@ -gzip - Compress the SDF using gzip. + Compress the SDF using gzip. @@ -14067,43 +14070,43 @@ filename - The SDF filename to write. + The SDF filename to write. - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-scene scene]filename + [-library_name lib_name][-cell_name cell_name] + [-scene scene]filename - lib_name + lib_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty library. Defaults to cell_name. - cell_name + cell_name - The name to use for the liberty cell. Defaults to the top level module name. + The name to use for the liberty cell. Defaults to the top level module name. - scene + scene The scene to use for extracting the model. @@ -14114,16 +14117,16 @@ filename - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. - set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + set_input_delayset_output_delayset_loadset_timing_derate + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: - combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths + combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. @@ -14131,10 +14134,10 @@ - write_verilog + write_verilog - [-include_pwr_gnd][-remove_cells lib_cells]filename + [-include_pwr_gnd][-remove_cells lib_cells]filename @@ -14147,10 +14150,10 @@ - -remove_cells lib_cells + -remove_cells lib_cells - Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. + Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. @@ -14158,12 +14161,12 @@ filename - Filename for the liberty library. + Filename for the liberty library. - The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -14173,12 +14176,12 @@ property - Return objects with property value equal to 1. + Return objects with property value equal to 1. - property==value + property==value Return objects with property value equal to value. @@ -14186,7 +14189,7 @@ - property=~pattern + property=~pattern Return objects with property value that matches pattern. @@ -14194,7 +14197,7 @@ - property!=value + property!=value Return objects with property value not equal to value. @@ -14202,15 +14205,15 @@ - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. - expr1&&expr2 + expr1&&expr2 Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. @@ -14218,24 +14221,24 @@ - expr1||expr2 + expr1||expr2 Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. @@ -14245,37 +14248,37 @@ - sta_continue_on_error + sta_continue_on_error - 0|1 + 0|1 - The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. + The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. - sta_crpr_mode + sta_crpr_mode - same_pin|same_transition + same_pin|same_transition - When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled - 0|1 + 0|1 @@ -14285,10 +14288,10 @@ - sta_crpr_enabled + sta_crpr_enabled - 0|1 + 0|1 @@ -14298,10 +14301,10 @@ - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking - 0|1 + 0|1 @@ -14311,23 +14314,23 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled - 0|1 + 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock - 0|1 + 0|1 @@ -14337,10 +14340,10 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled - 0|1 + 0|1 @@ -14350,23 +14353,23 @@ - sta_pocv_mode + sta_pocv_mode - scalar|normal|skew_normal + scalar|normal|skew_normal - Enable parametric on chip variation using statistical timing analysis. The default value is scalar. + Enable parametric on chip variation using statistical timing analysis. The default value is scalar. - sta_pocv_quartile + sta_pocv_quartile - quartile + quartile @@ -14376,14 +14379,14 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks - 0|1 + 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] After all clocks have been defined. The default value is 0. @@ -14391,36 +14394,36 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable - 0|1 + 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled - 0|1 + 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - sta_report_default_digits + sta_report_default_digits - integer + integer @@ -14430,10 +14433,10 @@ - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled - 0|1 + 0|1 @@ -14642,7 +14645,7 @@ - Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. + Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. From 0fd2ad3217bf976e3775266f4a1b704018e7ad0b Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Mon, 29 Jun 2026 15:39:27 +0000 Subject: [PATCH 32/35] isSequential update Signed-off-by: dsengupta0628 --- liberty/test/cpp/TestLibertyClasses.cc | 2 +- liberty/test/cpp/TestLibertyStaBasics.cc | 6 +++--- liberty/test/cpp/TestLibertyStaBasicsB.cc | 4 ++-- liberty/test/cpp/TestLibertyStaCallbacks.cc | 4 ++-- power/test/cpp/TestPower.cc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/liberty/test/cpp/TestLibertyClasses.cc b/liberty/test/cpp/TestLibertyClasses.cc index 9201380c..27f5143c 100644 --- a/liberty/test/cpp/TestLibertyClasses.cc +++ b/liberty/test/cpp/TestLibertyClasses.cc @@ -3230,7 +3230,7 @@ TEST(TestCellTest, HasInferedRegTimingArcs) { TEST(TestCellTest, HasSequentials) { LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "CELL1", "test.lib"); - EXPECT_FALSE(cell.hasSequentials()); + EXPECT_FALSE(cell.isSequential()); } TEST(TestCellTest, SequentialsEmpty) { diff --git a/liberty/test/cpp/TestLibertyStaBasics.cc b/liberty/test/cpp/TestLibertyStaBasics.cc index a999e68b..7ed177bc 100644 --- a/liberty/test/cpp/TestLibertyStaBasics.cc +++ b/liberty/test/cpp/TestLibertyStaBasics.cc @@ -810,7 +810,7 @@ TEST_F(StaLibertyTest, LibraryDelayModelType) { TEST_F(StaLibertyTest, CellHasSequentials) { LibertyCell *dff = lib_->findLibertyCell("DFF_X1"); if (dff) { - EXPECT_TRUE(dff->hasSequentials()); + EXPECT_TRUE(dff->isSequential()); auto &seqs = dff->sequentials(); EXPECT_GT(seqs.size(), 0u); } @@ -3266,10 +3266,10 @@ TEST_F(StaLibertyTest, CellIsInverter2) { TEST_F(StaLibertyTest, CellHasSequentials2) { LibertyCell *buf = lib_->findLibertyCell("BUF_X1"); ASSERT_NE(buf, nullptr); - EXPECT_FALSE(buf->hasSequentials()); + EXPECT_FALSE(buf->isSequential()); LibertyCell *dff = lib_->findLibertyCell("DFF_X1"); if (dff) { - EXPECT_TRUE(dff->hasSequentials()); + EXPECT_TRUE(dff->isSequential()); } } diff --git a/liberty/test/cpp/TestLibertyStaBasicsB.cc b/liberty/test/cpp/TestLibertyStaBasicsB.cc index 0d72b5db..9834e42b 100644 --- a/liberty/test/cpp/TestLibertyStaBasicsB.cc +++ b/liberty/test/cpp/TestLibertyStaBasicsB.cc @@ -2166,14 +2166,14 @@ TEST_F(StaLibertyTest, CellSetClockGateType) { TEST_F(StaLibertyTest, CellHasSequentialsBuf) { LibertyCell *buf = lib_->findLibertyCell("BUF_X1"); ASSERT_NE(buf, nullptr); - EXPECT_FALSE(buf->hasSequentials()); + EXPECT_FALSE(buf->isSequential()); } // LibertyCell::hasSequentials on DFF TEST_F(StaLibertyTest, CellHasSequentialsDFF) { LibertyCell *dff = lib_->findLibertyCell("DFF_X1"); ASSERT_NE(dff, nullptr); - EXPECT_TRUE(dff->hasSequentials()); + EXPECT_TRUE(dff->isSequential()); } // LibertyCell::sequentials diff --git a/liberty/test/cpp/TestLibertyStaCallbacks.cc b/liberty/test/cpp/TestLibertyStaCallbacks.cc index 52f0d155..1b14c7c9 100644 --- a/liberty/test/cpp/TestLibertyStaCallbacks.cc +++ b/liberty/test/cpp/TestLibertyStaCallbacks.cc @@ -3688,7 +3688,7 @@ library(test_r11_latch) { LibertyCell *cell = lib->findLibertyCell("LATCH1"); EXPECT_NE(cell, nullptr); if (cell) { - EXPECT_TRUE(cell->hasSequentials()); + EXPECT_TRUE(cell->isSequential()); } } remove(tmp_path.c_str()); @@ -4338,7 +4338,7 @@ library(test_mbff_statetable) { // But it has a statetable, so it IS sequential. EXPECT_NE(mbff->statetable(), nullptr); // hasSequentials() must return true for statetable-only cells. - EXPECT_TRUE(mbff->hasSequentials()) + EXPECT_TRUE(mbff->isSequential()) << "MBFF2 uses statetable (no ff/latch) but hasSequentials() " "returned false — statetable cells are misclassified as " "combinational"; diff --git a/power/test/cpp/TestPower.cc b/power/test/cpp/TestPower.cc index f5ee8a83..e50ae4ef 100644 --- a/power/test/cpp/TestPower.cc +++ b/power/test/cpp/TestPower.cc @@ -1326,7 +1326,7 @@ TEST_F(PowerDesignTest, SequentialCellClassification) { Instance *inst = child_iter->next(); LibertyCell *cell = network->libertyCell(inst); ASSERT_NE(cell, nullptr); - if (cell->hasSequentials()) { + if (cell->isSequential()) { seq_count++; } else { comb_count++; From 310107acd8ceab51ef7cce438907f97d93281abf Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 30 Jun 2026 09:10:17 -0700 Subject: [PATCH 33/35] revert 458c277 resolves #455 Signed-off-by: James Cherry --- include/sta/Sta.hh | 1 + search/Sta.cc | 20 +++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index bded0b9a..da5da08b 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -1513,6 +1513,7 @@ protected: bool infer_latches); void delayCalcPreamble(); void delaysInvalidFrom(const Port *port); + void delaysInvalidFromFanin(const Port *port); void deleteEdge(Edge *edge); void netParasiticCaps(Net *net, const RiseFall *rf, diff --git a/search/Sta.cc b/search/Sta.cc index 435b8867..61f9a274 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -3967,7 +3967,7 @@ Sta::setPortExtPinCap(const Port *port, for (const MinMax *mm : min_max->range()) sdc->setPortExtPinCap(port, rf1, mm, cap); } - delaysInvalidFrom(port); + delaysInvalidFromFanin(port); } void @@ -4022,7 +4022,7 @@ Sta::setPortExtWireCap(const Port *port, for (const MinMax *mm : min_max->range()) sdc->setPortExtWireCap(port, rf1, mm, cap); } - delaysInvalidFrom(port); + delaysInvalidFromFanin(port); } void @@ -4040,7 +4040,7 @@ Sta::setPortExtFanout(const Port *port, { for (const MinMax *mm : min_max->range()) sdc->setPortExtFanout(port, mm, fanout); - delaysInvalidFrom(port); + delaysInvalidFromFanin(port); } void @@ -5025,6 +5025,20 @@ Sta::delaysInvalidFrom(Vertex *vertex) graph_delay_calc_->delayInvalid(vertex); } +void +Sta::delaysInvalidFromFanin(const Port *port) +{ + if (graph_) { + Instance *top_inst = network_->topInstance(); + Pin *pin = network_->findPin(top_inst, port); + Vertex *vertex, *bidirect_drvr_vertex; + graph_->pinVertices(pin, vertex, bidirect_drvr_vertex); + delaysInvalidFromFanin(vertex); + if (bidirect_drvr_vertex) + delaysInvalidFromFanin(bidirect_drvr_vertex); + } +} + void Sta::delaysInvalidFromFanin(const Pin *pin) { From 998806cb13302f4e59763d7caa76972683853eee Mon Sep 17 00:00:00 2001 From: Deepashree Sengupta Date: Tue, 30 Jun 2026 12:18:56 -0400 Subject: [PATCH 34/35] make mode/scene pass as tcl objects (#454) * make mode/scene pass as tcl objects Signed-off-by: dsengupta0628 * address review comments Signed-off-by: dsengupta0628 * address review comments take 2 Signed-off-by: dsengupta0628 * revert to using cmd mode name Signed-off-by: dsengupta0628 --------- Signed-off-by: dsengupta0628 --- include/sta/Property.hh | 6 +++ sdc/Sdc.tcl | 4 +- search/Property.cc | 27 ++++++++++ search/Property.i | 16 ++++++ search/Search.i | 14 ++++++ tcl/CmdArgs.tcl | 21 +++++--- tcl/Property.tcl | 4 ++ tcl/Sta.tcl | 19 +++++-- tcl/StaTclTypes.i | 106 +++++++++++++-------------------------- test/get_scenes.ok | 6 +++ test/get_scenes.tcl | 20 ++++++++ test/regression_vars.tcl | 1 + 12 files changed, 161 insertions(+), 83 deletions(-) create mode 100644 test/get_scenes.ok create mode 100644 test/get_scenes.tcl diff --git a/include/sta/Property.hh b/include/sta/Property.hh index 1bb1e149..57260cde 100644 --- a/include/sta/Property.hh +++ b/include/sta/Property.hh @@ -42,6 +42,8 @@ class PropertyValue; class Sta; class PropertyValue; +class Scene; +class Mode; template class PropertyRegistry @@ -86,6 +88,10 @@ public: std::string_view property); PropertyValue getProperty(const Clock *clk, std::string_view property); + PropertyValue getProperty(const Scene *scene, + std::string_view property); + PropertyValue getProperty(const Mode *mode, + std::string_view property); PropertyValue getProperty(PathEnd *end, std::string_view property); PropertyValue getProperty(Path *path, diff --git a/sdc/Sdc.tcl b/sdc/Sdc.tcl index 5588c8f1..e444eea8 100644 --- a/sdc/Sdc.tcl +++ b/sdc/Sdc.tcl @@ -45,7 +45,7 @@ proc_redirect read_sdc { if { [info exists keys(-mode)] } { set mode_name $keys(-mode) - set prev_mode [cmd_mode] + set prev_mode [cmd_mode_name] try { set_cmd_mode $mode_name include_file $filename $echo 0 @@ -69,7 +69,7 @@ proc write_sdc { args } { flags {-map_hpins -compatible -gzip -no_timestamp} check_argc_eq1 "write_sdc" $args - set mode [cmd_mode] + set mode [cmd_mode_name] if { [info exists keys(-mode)] } { set mode $keys(-mode) } diff --git a/search/Property.cc b/search/Property.cc index fe848d5e..6ecd9ab7 100644 --- a/search/Property.cc +++ b/search/Property.cc @@ -33,6 +33,7 @@ #include "Graph.hh" #include "Liberty.hh" #include "MinMax.hh" +#include "Mode.hh" #include "Network.hh" #include "Path.hh" #include "PathEnd.hh" @@ -1196,6 +1197,32 @@ Properties::getProperty(const Clock *clk, //////////////////////////////////////////////////////////////// +PropertyValue +Properties::getProperty(const Scene *scene, + std::string_view property) +{ + if (property == "name" + || property == "full_name") + return PropertyValue(scene->name()); + else + throw PropertyUnknown("scene", property); +} + +//////////////////////////////////////////////////////////////// + +PropertyValue +Properties::getProperty(const Mode *mode, + std::string_view property) +{ + if (property == "name" + || property == "full_name") + return PropertyValue(mode->name()); + else + throw PropertyUnknown("mode", property); +} + +//////////////////////////////////////////////////////////////// + PropertyValue Properties::getProperty(PathEnd *end, std::string_view property) diff --git a/search/Property.i b/search/Property.i index 01c8b4c1..2002f901 100644 --- a/search/Property.i +++ b/search/Property.i @@ -121,6 +121,22 @@ clock_property(Clock *clk, return properties.getProperty(clk, property); } +PropertyValue +scene_property(Scene *scene, + const char *property) +{ + Properties &properties = Sta::sta()->properties(); + return properties.getProperty(scene, property); +} + +PropertyValue +mode_property(Mode *mode, + const char *property) +{ + Properties &properties = Sta::sta()->properties(); + return properties.getProperty(mode, property); +} + PropertyValue path_end_property(PathEnd *end, const char *property) diff --git a/search/Search.i b/search/Search.i index 6f0376de..7adf097f 100644 --- a/search/Search.i +++ b/search/Search.i @@ -72,6 +72,20 @@ private: ~PathEnd(); }; +class Scene +{ +private: + Scene(); + ~Scene(); +}; + +class Mode +{ +private: + Mode(); + ~Mode(); +}; + %inline %{ using std::string; diff --git a/tcl/CmdArgs.tcl b/tcl/CmdArgs.tcl index fb962df6..71232ef1 100644 --- a/tcl/CmdArgs.tcl +++ b/tcl/CmdArgs.tcl @@ -536,14 +536,23 @@ proc parse_scenes_or_all { keys_var } { } } -proc find_scenes { scene_names } { +proc find_scenes { scenes_arg } { set scenes {} - foreach scene_name $scene_names { - set scene [find_scene $scene_name] - if { $scene == "NULL" } { - sta_error 134 "$scene_name is not the name of a scene." + foreach scene_arg $scenes_arg { + if { [is_object $scene_arg] } { + set object_type [object_type $scene_arg] + if { $object_type == "Scene" } { + lappend scenes $scene_arg + } else { + sta_error 135 "scene object type '$object_type' is not a scene." + } } else { - lappend scenes $scene + set scene [find_scene $scene_arg] + if { $scene == "NULL" } { + sta_error 134 "$scene_arg is not the name of a scene." + } else { + lappend scenes $scene + } } } return $scenes diff --git a/tcl/Property.tcl b/tcl/Property.tcl index 87e0d3c3..3f70adc6 100644 --- a/tcl/Property.tcl +++ b/tcl/Property.tcl @@ -57,6 +57,10 @@ proc get_object_property { object prop } { return [net_property $object $prop] } elseif { $object_type == "Clock" } { return [clock_property $object $prop] + } elseif { $object_type == "Scene" } { + return [scene_property $object $prop] + } elseif { $object_type == "Mode" } { + return [mode_property $object $prop] } elseif { $object_type == "Port" } { return [port_property $object $prop] } elseif { $object_type == "LibertyPort" } { diff --git a/tcl/Sta.tcl b/tcl/Sta.tcl index ee560962..0ec12a27 100644 --- a/tcl/Sta.tcl +++ b/tcl/Sta.tcl @@ -102,7 +102,12 @@ define_cmd_args "set_scene" {scene_name} proc set_scene { args } { check_argc_eq1 "set_scene" $args - set_cmd_scene [lindex $args 0] + set scene_name [lindex $args 0] + set scene [find_scene $scene_name] + if { $scene == "NULL" } { + sta_error 578 "$scene_name is not the name of a scene." + } + set_cmd_scene $scene } ################################################################ @@ -118,10 +123,16 @@ proc get_scenes { args } { } else { set scene_name [lindex $args 0] } - set mode_names {} if { [info exists keys(-modes)] } { - set mode_names $keys(-modes) - return [find_mode_scenes_matching $scene_name $mode_names] + set modes {} + foreach mode_name $keys(-modes) { + set mode [find_mode $mode_name] + if { $mode == "NULL" } { + sta_error 579 "$mode_name is not the name of a mode." + } + lappend modes $mode + } + return [find_mode_scenes_matching $scene_name $modes] } else { return [find_scenes_matching $scene_name] } diff --git a/tcl/StaTclTypes.i b/tcl/StaTclTypes.i index c5eb3420..c8c62584 100644 --- a/tcl/StaTclTypes.i +++ b/tcl/StaTclTypes.i @@ -1189,106 +1189,70 @@ using namespace sta; $1 = tclListSetConstChar($input, interp); } +%typemap(in) Mode* { + Tcl_Size length; + const char *arg = Tcl_GetStringFromObj($input, &length); + if (stringEqual(arg, "NULL")) + $1 = nullptr; + else { + void *obj; + if (SWIG_ConvertPtr($input, &obj, SWIGTYPE_p_Mode, false) != TCL_OK) { + tclArgError(interp, 2174, "{} is not a mode object.", arg); + return TCL_ERROR; + } + $1 = reinterpret_cast(obj); + } +} + %typemap(out) Mode* { - const Mode *mode = $1; - if (mode) - Tcl_SetResult(interp, const_cast($1->name().c_str()), TCL_VOLATILE); + Mode *mode = $1; + if (mode) { + Tcl_Obj *obj = SWIG_NewInstanceObj(mode, SWIGTYPE_p_Mode, false); + Tcl_SetObjResult(interp, obj); + } else Tcl_SetResult(interp, const_cast("NULL"), TCL_STATIC); } %typemap(in) ModeSeq { - Tcl_Size argc; - Tcl_Obj **argv; - - Sta *sta = Sta::sta(); - std::vector seq; - if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK - && argc > 0) { - for (int i = 0; i < argc; i++) { - Tcl_Size length; - const char *mode_name = Tcl_GetStringFromObj(argv[i], &length); - Mode *mode = sta->findMode(mode_name); - if (mode) - seq.push_back(mode); - else { - tclArgError(interp, 2174, "mode {} not found.", mode_name); - return TCL_ERROR; - } - } - } - $1 = seq; + $1 = tclListSeq($input, SWIGTYPE_p_Mode, interp); } %typemap(out) ModeSeq { - Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - ModeSeq &modes = $1; - for (Mode *mode : modes) { - const std::string &mode_name = mode->name(); - Tcl_Obj *obj = Tcl_NewStringObj(mode_name.c_str(), mode_name.size()); - Tcl_ListObjAppendElement(interp, list, obj); - } - Tcl_SetObjResult(interp, list); + seqTclList($1, SWIGTYPE_p_Mode, interp); } %typemap(in) Scene* { - sta::Sta *sta = Sta::sta(); Tcl_Size length; - std::string scene_name = Tcl_GetStringFromObj($input, &length); - // parse_scene_or_all support depreated 11/21/2025 - if (scene_name == "NULL") + const char *arg = Tcl_GetStringFromObj($input, &length); + if (stringEqual(arg, "NULL")) $1 = nullptr; else { - Scene *scene = sta->findScene(scene_name); - if (scene) - $1 = scene; - else { - tclArgError(interp, 2173, "scene {} not found.", scene_name.c_str()); + void *obj; + if (SWIG_ConvertPtr($input, &obj, SWIGTYPE_p_Scene, false) != TCL_OK) { + tclArgError(interp, 2173, "{} is not a scene object.", arg); return TCL_ERROR; } + $1 = reinterpret_cast(obj); } } %typemap(out) Scene* { - const Scene *scene = $1; - if (scene) - Tcl_SetResult(interp, const_cast($1->name().c_str()), TCL_VOLATILE); + Scene *scene = $1; + if (scene) { + Tcl_Obj *obj = SWIG_NewInstanceObj(scene, SWIGTYPE_p_Scene, false); + Tcl_SetObjResult(interp, obj); + } else Tcl_SetResult(interp, const_cast("NULL"), TCL_STATIC); } %typemap(in) SceneSeq { - Tcl_Size argc; - Tcl_Obj **argv; - - Sta *sta = Sta::sta(); - std::vector seq; - if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK - && argc > 0) { - for (int i = 0; i < argc; i++) { - Tcl_Size length; - const char *scene_name = Tcl_GetStringFromObj(argv[i], &length); - Scene *scene = sta->findScene(scene_name); - if (scene) - seq.push_back(scene); - else { - tclArgError(interp, 2172, "scene {} not found.", scene_name); - return TCL_ERROR; - } - } - } - $1 = seq; + $1 = tclListSeq($input, SWIGTYPE_p_Scene, interp); } %typemap(out) SceneSeq { - Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - SceneSeq &scenes = $1; - for (Scene *scene : scenes) { - const std::string &scene_name = scene->name(); - Tcl_Obj *obj = Tcl_NewStringObj(scene_name.c_str(), scene_name.size()); - Tcl_ListObjAppendElement(interp, list, obj); - } - Tcl_SetObjResult(interp, list); + seqTclList($1, SWIGTYPE_p_Scene, interp); } %typemap(in) PropertyValue { diff --git a/test/get_scenes.ok b/test/get_scenes.ok new file mode 100644 index 00000000..ab504b68 --- /dev/null +++ b/test/get_scenes.ok @@ -0,0 +1,6 @@ +[get_scenes *] +scene1 +scene2 +[get_modes *] +mode1 +mode2 diff --git a/test/get_scenes.tcl b/test/get_scenes.tcl new file mode 100644 index 00000000..396c32ce --- /dev/null +++ b/test/get_scenes.tcl @@ -0,0 +1,20 @@ +# get_scenes / get_modes return objects +read_liberty ../examples/asap7_small_ff.lib.gz +read_liberty ../examples/asap7_small_ss.lib.gz +read_verilog ../examples/reg1_asap7.v +link_design top + +read_sdc -mode mode1 ../examples/mcmm2_mode1.sdc +read_sdc -mode mode2 ../examples/mcmm2_mode2.sdc + +read_spef -name reg1_ff ../examples/reg1_asap7.spef +read_spef -name reg1_ss ../examples/reg1_asap7_ss.spef + +define_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ff +define_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ss + +puts {[get_scenes *]} +report_object_names [get_scenes *] + +puts {[get_modes *]} +report_object_names [get_modes *] diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index d1e30064..fcb2c291 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -147,6 +147,7 @@ record_public_tests { get_is_memory get_lib_pins_of_objects get_noargs + get_scenes get_objrefs input_delay_ref_pin_rebuild liberty_arcs_one2one_1 From 3ab3337d1b8f13bd15d80786ec771e1c6388d24a Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Tue, 30 Jun 2026 17:28:09 +0000 Subject: [PATCH 35/35] update test to accomodate mode/scene as tcl objects and not name string Signed-off-by: dsengupta0628 --- search/test/search_corner_skew.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/search/test/search_corner_skew.tcl b/search/test/search_corner_skew.tcl index ea36873e..1b77c43c 100644 --- a/search/test/search_corner_skew.tcl +++ b/search/test/search_corner_skew.tcl @@ -14,7 +14,7 @@ report_checks > /dev/null puts "--- Corner commands ---" set corner [sta::cmd_scene] -puts "Corner name: $corner" +puts "Corner name: [get_name $corner]" puts "Multi corner: [sta::multi_scene]" puts "--- ClkSkew report with propagated clock ---"