diff --git a/search/MakeTimingModel.cc b/search/MakeTimingModel.cc index 734c80f7..b73c7b89 100644 --- a/search/MakeTimingModel.cc +++ b/search/MakeTimingModel.cc @@ -515,14 +515,14 @@ MakeTimingModel::findClkInsertionDelays() { Instance *top_inst = network_->topInstance(); Cell *top_cell = network_->cell(top_inst); - CellPortIterator *port_iter = network_->portIterator(top_cell); + CellPortIterator *port_iter = network_->portBitIterator(top_cell); while (port_iter->hasNext()) { Port *port = port_iter->next(); if (network_->direction(port)->isInput()) { const char *port_name = network_->name(port); LibertyPort *lib_port = cell_->findLibertyPort(port_name); Pin *pin = network_->findPin(top_inst, port); - if (sdc_->isClock(pin)) { + if (pin && sdc_->isClock(pin)) { lib_port->setIsClock(true); ClockSet *clks = sdc_->findClocks(pin); size_t clk_count = clks->size(); diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index 870267b4..c2febea1 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -6032,15 +6032,15 @@ requireds_clk(const RiseFall *rf, const RiseFall *clk_rf) { Sta *sta = Sta::sta(); - FloatSeq requireds; + FloatSeq reqs; const ClockEdge *clk_edge = nullptr; if (clk) clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - requireds.push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge, - path_ap))); + reqs.push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge, + path_ap))); } - return requireds; + return reqs; } StringSeq @@ -6050,16 +6050,15 @@ requireds_clk_delays(const RiseFall *rf, int digits) { Sta *sta = Sta::sta(); - StringSeq requireds; + StringSeq reqs; const ClockEdge *clk_edge = nullptr; if (clk) clk_edge = clk->edge(clk_rf); for (auto path_ap : sta->corners()->pathAnalysisPts()) { - requireds.push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge, - path_ap), - sta, digits)); + reqs.push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge, path_ap), + sta, digits)); } - return requireds; + return reqs; } Slack