From bacb61feaa0976f86a20abbdf08017618a669d83 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 21 Mar 2026 10:18:55 -0700 Subject: [PATCH 01/22] regression -j Signed-off-by: James Cherry --- test/regression.tcl | 485 +++++++++++++++++++++++++++----------------- 1 file changed, 298 insertions(+), 187 deletions(-) diff --git a/test/regression.tcl b/test/regression.tcl index 447a85ad..8137fcc8 100755 --- a/test/regression.tcl +++ b/test/regression.tcl @@ -30,7 +30,8 @@ # # This notice may not be removed or altered from any source distribution. -# regression -help | [-threads threads] [-valgrind] [-report_stats] test1 [test2...] +# Usage: regression -help | [-threads threads] [-j jobs] [-valgrind] [-report_stats] +# test1 [test2...] proc regression_main {} { setup @@ -41,12 +42,13 @@ proc regression_main {} { } proc setup {} { - global result_dir diff_file failure_file errors + global result_dir diff_file failure_file errors failed_tests global use_valgrind valgrind_shared_lib_failure - global report_stats + global report_stats max_jobs app_path set use_valgrind 0 set report_stats 0 + set max_jobs 1 if { !([file exists $result_dir] && [file isdirectory $result_dir]) } { file mkdir $result_dir @@ -60,20 +62,28 @@ proc setup {} { set errors(fail) 0 set errors(no_cmd) 0 set errors(no_ok) 0 + set failed_tests {} set valgrind_shared_lib_failure 0 + + if { ![file exists $app_path] } { + error "$app_path not found." + } elseif { ![file executable $app_path] } { + error "$app_path is not executable." + } } proc parse_args {} { global argv app_options tests test_groups cmd_paths global use_valgrind global result_dir tests - global report_stats + global report_stats max_jobs while { $argv != {} } { set arg [lindex $argv 0] if { $arg == "help" || $arg == "-help" } { - puts {Usage: regression [-help] [-threads threads] [-valgrind] [-report_stats] tests...} + puts {Usage: regression [-help] [-threads threads] [-j jobs] [-valgrind] [-report_stats] tests...} puts " -threads max|integer - number of threads to use" + puts " -j jobs - number of parallel jobs (processes) to run" puts " -valgrind - run valgrind (linux memory checker)" puts " -report_stats - report run time and memory" puts " Wildcarding for test names is supported (enclose in \"'s)" @@ -84,12 +94,20 @@ proc parse_args {} { } elseif { $arg == "-threads" } { set threads [lindex $argv 1] if { !([string is integer $threads] || $threads == "max") } { - puts "Error: -threads arg $threads is not an integer or max." - exit 0 + puts "Error: -threads arg $threads is not an integer or max." + exit 0 } lappend app_options "-threads" lappend app_options $threads set argv [lrange $argv 2 end] + } elseif { $arg == "-j" } { + set jobs [lindex $argv 1] + if { ![string is integer $jobs] || $jobs < 1 } { + puts "Error: -j arg $jobs must be a positive integer." + exit 0 + } + set max_jobs $jobs + set argv [lrange $argv 2 end] } elseif { $arg == "-valgrind" } { if { ![find_valgrind] } { error "valgrind not found." @@ -131,7 +149,7 @@ proc expand_tests { argv } { if { [info exists test_groups($arg)] } { set tests [concat $tests $test_groups($arg)] } elseif { [string first "*" $arg] != -1 \ - || [string first "?" $arg] != -1 } { + || [string first "?" $arg] != -1 } { # Find wildcard matches. foreach test [group_tests "all"] { if [string match $arg $test] { @@ -143,200 +161,296 @@ proc expand_tests { argv } { } else { puts "Error: test $arg not found." incr errors(no_cmd) - } + } } return $tests } proc run_tests {} { - global tests errors app_path + global tests errors app_path max_jobs - foreach test $tests { - run_test $test + if { $max_jobs > 1 } { + run_tests_parallel + } else { + foreach test $tests { + run_test $test + } } - # Macos debug info generated by valgrind. - file delete -force "$app_path.dSYM" + write_failure_file + write_diff_file } proc run_test { test } { - global result_dir diff_file errors diff_options report_stats + global result_dir diff_file errors diff_options - set cmd_file [test_cmd_file $test] - if [file exists $cmd_file] { - set ok_file [test_ok_file $test] + puts -nonewline $test + flush stdout + set exit_code 0 + if { [test_cmd_file_exists $test] } { + set cmd [make_cmd_file $test] set log_file [test_log_file $test] - foreach file [glob -nocomplain [file join $result_dir $test.*]] { - file delete -force $file - } - puts -nonewline $test - flush stdout - set test_errors [run_test_app $test $cmd_file $log_file] - if { [lindex $test_errors 0] == "ERROR" } { - puts " *ERROR* [lrange $test_errors 1 end]" - append_failure $test - incr errors(error) - - # For some reason seg faults aren't echoed in the log - add them. - if { [llength $test_errors] > 1 && [file exists $log_file] } { - set log_ch [open $log_file "a"] - puts $log_ch $test_errors - close $log_ch - } - - # Report partial log diff anyway. - if [file exists $ok_file] { - catch [concat exec diff $diff_options $ok_file $log_file \ - >> $diff_file] - } - } else { - set error_msg "" - if { [lsearch $test_errors "MEMORY"] != -1 } { - append error_msg " *MEMORY*" - append_failure $test - incr errors(memory) - } - if { [lsearch $test_errors "LEAK"] != -1 } { - append error_msg " *LEAK*" - append_failure $test - incr errors(leak) - } - if { $report_stats } { - append error_msg " [test_stats_summary $test]" - } - - if [file exists $ok_file] { - # Filter dos '/r's from log file. - set tmp_file [file join $result_dir $test.tmp] - exec tr -d "\r" < $log_file > $tmp_file - file rename -force $tmp_file $log_file - if [catch [concat exec diff $diff_options $ok_file $log_file \ - >> $diff_file]] { - puts " *FAIL*$error_msg" - append_failure $test - incr errors(fail) - } else { - puts " pass$error_msg" - } + if { [catch [concat "exec" "$cmd >& $log_file"] result result_options] } { + set details [dict get $result_options -errorcode] + set exit_signal [lindex $details 2] + if { $exit_signal == "SIGSEGV" } { + set exit_code 139 } else { - puts " *NO OK FILE*" - append_failure $test - incr errors(no_ok) + set exit_code 128 } } - } else { - puts "$test *NO CMD FILE*" - incr errors(no_cmd) + } + puts " [test_status $test $exit_code]" +} + +################################################################ + +# Parallel runs use one pipeline per test; close() yields the real exit status. +# (Non-blocking channels must be switched to blocking before close - see Tcl manual.) +proc regression_parallel_close_pipe { fh } { + fconfigure $fh -blocking 1 + if { [catch {close $fh} err opts] } { + set ec [dict get $opts -errorcode] + if { [lindex $ec 0] == "CHILDSTATUS" } { + return [lindex $ec 2] + } + return 128 + } + return 0 +} + +proc regression_pipe_readable { fh test } { + global reg_parallel_active reg_parallel_job_done + + read $fh + if { [eof $fh] } { + fileevent $fh readable {} + set exit_code [regression_parallel_close_pipe $fh] + puts "$test [test_status $test $exit_code]" + incr reg_parallel_active -1 + incr reg_parallel_job_done } } -proc test_stats { test } { - if { ![catch {open [test_stats_file $test] r} stream] } { - gets $stream line1 - close $stream - return $line1 - } else { - return {} +proc open_test_pipeline { test } { + set cmd [make_cmd_file $test] + set log [test_log_file $test] + set inner [format {%s > %s 2>&1} $cmd [file nativename $log]] + set fh [open [format {|/bin/sh -c %s} [list $inner]] r] + fconfigure $fh -blocking 0 + return $fh +} + +proc run_tests_parallel {} { + global tests max_jobs reg_parallel_active reg_parallel_job_done + + set reg_parallel_active 0 + set reg_parallel_job_done 0 + set test_idx 0 + set test_count [llength $tests] + + while { $test_idx < $test_count || $reg_parallel_active > 0 } { + while { $reg_parallel_active < $max_jobs && $test_idx < $test_count } { + set test [lindex $tests $test_idx] + incr test_idx + if { ![test_cmd_file_exists $test] } { + puts -nonewline $test + flush stdout + puts " [test_status $test 0]" + continue + } + set fh [open_test_pipeline $test] + fileevent $fh readable [list regression_pipe_readable $fh $test] + incr reg_parallel_active + } + if { $reg_parallel_active > 0 } { + set before $reg_parallel_job_done + while { $reg_parallel_job_done == $before } { + vwait reg_parallel_job_done + } + } } } +proc make_cmd_file { test } { + global app_path app_options result_dir use_valgrind report_stats + + foreach file [glob -nocomplain [file join $result_dir $test.*]] { + file delete -force $file + } + + set cmd_file [test_cmd_file $test] + set ok_file [test_ok_file $test] + set log_file [test_log_file $test] + + set run_file [test_run_file $test] + set run_stream [open $run_file "w"] + puts $run_stream "cd [file dirname $cmd_file]" + puts $run_stream "include [file tail $cmd_file]" + if { $use_valgrind } { + puts $run_stream "sta::delete_all_memory" + } + if { $report_stats } { + puts $run_stream "sta::write_stats [test_stats_file $test]" + } + close $run_stream + + if { $use_valgrind } { + global valgrind_options + set cmd "valgrind $valgrind_options $app_path $app_options $run_file" + } else { + set cmd "$app_path $app_options $run_file" + } + return $cmd +} + +proc test_cmd_file_exists { test } { + set cmd_file [test_cmd_file $test] + return [file exists $cmd_file] +} + +proc test_status { test exit_code } { + global result_dir diff_options errors + global use_valgrind report_stats test_status + + set test_status {} + if { ![test_cmd_file_exists $test] } { + test_failed $test "no_cmd" + } else { + set log_file [test_log_file $test] + + if { [file exists $log_file] } { + # Check log file for error patterns + set log_ch [open $log_file "r"] + set log_content [read $log_ch] + close $log_ch + + # Check if exit code indicates a segfault or signal termination + # Exit codes >= 128 typically indicate termination by a signal + # 139 = 128 + 11 (SIGSEGV), 134 = 128 + 6 (SIGABRT), etc. + if { $exit_code >= 128 + || [string match "*Segmentation fault*" $log_content] \ + || [string match "*DEADLYSIGNAL*" $log_content] \ + || [string match "*Abort*" $log_content] \ + || [string match "*Fatal*" $log_content] } { + test_failed $test "error" + } elseif { [string match "*heap-use-after-free*" $log_content] } { + # ASAN error + test_failed $test "memory" + } + set ok_file [test_ok_file $test] + if { [file exists $ok_file] } { + if { $use_valgrind } { + cleanse_valgrind_logfile $test + } + if { [catch [concat exec diff $diff_options $ok_file $log_file]] } { + if { $test_status == "" } { + test_failed $test "fail" + } + } + } else { + if { $test_status == "" } { + test_failed $test "no_ok" + } + } + } else { + # Log file doesn't exist, likely an error + test_failed $test "error" "*ERROR* no log file" + } + } + if { $test_status == {} } { + append test_status "pass" + } + if { $report_stats } { + append test_status " [test_stats_summary $test]" + } + return $test_status +} + +proc test_exit_code { test } { + # Read exit code + set test_error "" + set exit_code_file [test_exit_code_file $test] + if { [file exists $exit_code_file] } { + set exit_code_ch [open $exit_code_file "r"] + set exit_code [string trim [read $exit_code_ch]] + close $exit_code_ch + + if { [string is integer $exit_code] } { + return $exit_code + } + } + return 0 +} + proc test_stats_summary { test } { - set stats [test_stats $test] - set elapsed_time [lindex $stats 0] - set user_time [lindex $stats 1] - set memory [lindex $stats 2] - if { [string is double $elapsed_time] } { - set elapsed [format "%.1fe" $elapsed_time] - } else { - set elapsed "?" - } - if { [string is double $user_time] } { - set user [format "%.1fu" $user_time] - } else { - set user "?" - } - if { [string is double $memory] } { - set mem [format "%.0fmb" [expr $memory * 1e-6]] - } else { - set mem "?" - } - return "$elapsed $user $mem" -} + if { ![catch {open [test_stats_file $test] r} stream] } { + gets $stream stats + close $stream -proc append_failure { test } { - global failure_file - set fail_ch [open $failure_file "a"] - puts $fail_ch $test - close $fail_ch -} - -# Return error. -proc run_test_app { test cmd_file log_file } { - global app_path errorCode use_valgrind - if { $use_valgrind } { - return [run_test_valgrind $test $cmd_file $log_file] - } else { - return [run_test_plain $test $cmd_file $log_file] - } -} - -proc run_test_plain { test cmd_file log_file } { - global app_path app_options result_dir errorCode - global report_stats - - if { ![file exists $app_path] } { - return "ERROR $app_path not found." - } elseif { ![file executable $app_path] } { - return "ERROR $app_path is not executable." - } else { - set run_file [test_run_file $test] - set run_stream [open $run_file "w"] - puts $run_stream "cd [file dirname $cmd_file]" - puts $run_stream "include [file tail $cmd_file]" - if { $report_stats } { - set stat_file [file normalize [test_stats_file $test]] - puts $run_stream "sta::write_stats $stat_file" + set elapsed_time [lindex $stats 0] + set user_time [lindex $stats 1] + set memory [lindex $stats 2] + if { [string is double $elapsed_time] } { + set elapsed [format "%.1fe" $elapsed_time] + } else { + set elapsed "?" } - close $run_stream - - if { [catch [concat exec $app_path $app_options $run_file >& $log_file]] } { - set signal [lindex $errorCode 2] - set error [lindex $errorCode 3] - # Error strings are not consistent across platforms but signal - # names are. - if { $signal == "SIGSEGV" } { - # Save corefiles to regression results directory. - set pid [lindex $errorCode 1] - set sys_corefile [test_sys_core_file $test $pid] - if { [file exists $sys_corefile] } { - file copy $sys_corefile [test_core_file $test] - } - } - return "ERROR $error" + if { [string is double $user_time] } { + set user [format "%.1fu" $user_time] + } else { + set user "?" } - file delete $run_file + if { [string is double $memory] } { + set mem [format "%.0fmb" [expr $memory * 1e-6]] + } else { + set mem "?" + } + return "$elapsed $user $mem" + } else { return "" } } -proc run_test_valgrind { test cmd_file log_file } { - global app_path app_options valgrind_options result_dir errorCode +proc test_failed { test reason } { + global errors test_status failed_tests - set vg_cmd_file [test_valgrind_cmd_file $test] - set vg_stream [open $vg_cmd_file "w"] - puts $vg_stream "cd [file dirname $cmd_file]" - puts $vg_stream "include [file tail $cmd_file]" - puts $vg_stream "sta::delete_all_memory" - close $vg_stream - - set cmd [concat exec valgrind $valgrind_options \ - $app_path $app_options $vg_cmd_file >& $log_file] - set error_msg "" - if { [catch $cmd] } { - set error_msg "ERROR [lindex $errorCode 3]" + if { $reason == "error" } { + set test_status "*ERROR*" + } elseif { $reason == "no_cmd" } { + set test_status "*NO CMD FILE*" + } elseif { $reason == "memory" } { + set test_status "*MEMORY*" + } elseif { $reason == "leak" } { + set test_status "*LEAK*" + } elseif { $reason == "fail" } { + set test_status "*FAIL*" + } elseif { $reason == "no_ok" } { + set test_status "*NO OK FILE*" + } else { + error "unknown test failure reason $reason" + } + lappend failed_tests $test + incr errors($reason) +} + +proc write_failure_file {} { + global failure_file failed_tests + + set ch [open $failure_file "w"] + foreach test $failed_tests { + puts $ch $test + } + close $ch +} + +proc write_diff_file {} { + global diff_file diff_options failed_tests + + foreach test $failed_tests { + set log_file [test_log_file $test] + set ok_file [test_ok_file $test] + catch [concat exec diff $diff_options $ok_file $log_file >> $diff_file] } - file delete $vg_cmd_file - set error_msg [concat $error_msg [cleanse_valgrind_logfile $test $log_file]] - return $error_msg } # Error messages can be found in "valgrind/memcheck/mc_errcontext.c". @@ -363,25 +477,26 @@ set valgrind_shared_lib_failure_regexp "No malloc'd blocks -- no leaks are possi # Scan the log file to separate valgrind notifications and check for # valgrind errors. -proc cleanse_valgrind_logfile { test log_file } { +proc cleanse_valgrind_logfile { test } { global valgrind_mem_regexp valgrind_leak_regexp global valgrind_shared_lib_failure_regexp - global valgrind_shared_lib_failure + global valgrind_shared_lib_failure error + set log_file [test_log_file $test] set tmp_file [test_tmp_file $test] set valgrind_log_file [test_valgrind_file $test] file copy -force $log_file $tmp_file set tmp [open $tmp_file "r"] set log [open $log_file "w"] set valgrind [open $valgrind_log_file "w"] - set leaks 0 + set leak 0 set mem_errors 0 gets $tmp line while { ![eof $tmp] } { if {[regexp "^==" $line]} { puts $valgrind $line if {[regexp $valgrind_leak_regexp $line]} { - set leaks 1 + set leak 1 } if {[regexp $valgrind_mem_regexp $line]} { set mem_errors 1 @@ -399,16 +514,12 @@ proc cleanse_valgrind_logfile { test log_file } { close $log close $tmp close $valgrind - file delete $tmp_file - set errors {} if { $mem_errors } { - lappend errors "MEMORY" + test_failed $test "memory" + } elseif { $leak } { + test_failed $test "leak" } - if { $leaks } { - lappend errors "LEAK" - } - return $errors } ################################################################ @@ -533,11 +644,6 @@ proc test_tmp_file { test } { return [file join $result_dir $test.tmp] } -proc test_valgrind_cmd_file { test } { - global result_dir - return [file join $result_dir $test.vg_cmd] -} - proc test_valgrind_file { test } { global result_dir return [file join $result_dir $test.valgrind] @@ -563,6 +669,11 @@ proc test_sys_core_file { test pid } { return [file join [test_cmd_dir $test] "core"] } +proc test_exit_code_file { test } { + global result_dir + return [file join $result_dir "$test.exitcode"] +} + ################################################################ # Local Variables: From 420519c5d9f25a9a64dd8bc51f3a5f52b2ff973d Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 21 Mar 2026 12:32:10 -0700 Subject: [PATCH 02/22] write_path_spice Signed-off-by: James Cherry --- doc/ChangeLog.txt | 7 + doc/OpenSTA.fodt | 3453 +++++++++++++++++++++--------------------- doc/OpenSTA.pdf | Bin 1419896 -> 1443585 bytes spice/WriteSpice.tcl | 19 +- 4 files changed, 1747 insertions(+), 1732 deletions(-) diff --git a/doc/ChangeLog.txt b/doc/ChangeLog.txt index bebf05b6..b6238246 100644 --- a/doc/ChangeLog.txt +++ b/doc/ChangeLog.txt @@ -4,6 +4,13 @@ OpenSTA Timing Analyzer Release Notes This file summarizes user visible changes for each release. See ApiChangeLog.txt for changes to the STA api. +2026/03/23 +---------- + +The write_path_spice command -spice_directory has been changed to +-spice_file, which is a prefix for the spice filenames. Successive +paths are written in files name _.sp. + Release 3.0.1 2026/03/12 ------------------------ diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index 56bfdfc2..e0d25e48 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,30 +1,31 @@ - Parallax STA documentationJames Cherry5272025-03-17T12:59:52.4638705382010-07-31T21:07:002026-03-13T08:23:12.816774000P123DT2H11M52SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry5282025-03-17T12:59:52.4638705382010-07-31T21:07:002026-03-21T12:31:10.522816000P123DT2H14M54SLibreOffice/26.2.1.2$MacOSX_AARCH64 LibreOffice_project/8399f6259d8c87f40e7255cdb3c9b958f5e08948PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 138335 - 12 - 21890 - 20512 + 2413538 + 0 + 30134 + 17268 true false view2 - 5793 - 99330 - 12 - 138335 - 21900 - 158845 + 18244 + 2424328 + 0 + 2413538 + 30133 + 2430805 0 1 false 90 false false + 172,145,1382,863;1;,,,; true true false @@ -45,11 +46,13 @@ false false + true false false false false false + false false false false @@ -89,7 +92,7 @@ false true false - 27526206 + 27556207 0 false @@ -4029,8 +4032,8 @@ - - + + @@ -4141,7 +4144,7 @@ - + @@ -4200,7 +4203,7 @@ - + @@ -4824,540 +4827,544 @@ + + + + - + - - - - + + + + - + - - - - - + + + + + - + - - - - - + + + + + - + - - - - + - + + + + - + - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - + - + + + + + - + - + + + + + - + - - - - - + - + - - + + - + + + + + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + - + + + + + - + - + - + - - - - - + - + - + - + + + + + - + - + - - - - - + + + + + - + - - - - - + + + + + - - - - + + + + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + @@ -5404,940 +5411,940 @@ - - - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + - + - + - + - + @@ -6607,24 +6614,24 @@ Variables85 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. Use the report_units command to see the ccmmand units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. read_liberty nangate45_slow.lib.gzread_liberty nangate45_typ.lib.gzread_liberty nangate45_fast.lib.gzread_verilog example1.link_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}define_scene ss -liberty nangate45_slowdefine_scene tt -liberty nangate45_typdefine_scene ff -liberty nangate45_fast# report all scenesreport_checks -path_delay min_max# report typical scenereport_checks -scene tt This example can be found in examples/multi_corner.tcl. Other examples can be found in the examples directory. - Timing Analysis with Multiple Corners and Modes + Timing Analysis with Multiple Corners and Modes OpenSTA supports multi-corner, multi-mode analysis. Each corner/mode combination is called a “scene”. The SDC constraints in each mode describe a different operating mode, such as mission mode or scan mode. Each corner has min/max Liberty libraries and SPEF parasitics. A mode named “default” is initially created for SDC commands. It is deleted when a mode is defined with set_mode or read_sdc -mode. Similartly, a named “default” is initially created that is deleted when define_scene is used to define a scene. An example command script using two process corners two modes is shown below. @@ -6633,72 +6640,72 @@ set_mode mode1create_clock -name m1_clk -period 1000 {clk1 clk2 clk3}set_input_delay -clock m1_clk 100 {in1 in2}set_mode mode2create_clock -name m2_clk -period 500 {clk1 clk3}set_output_delay -clock m2_clk 100 out Statistical Timing Analysis OpenSTA also supports statistical timing .anallysis with Liberty Variation Format (LVF) libraries. Statistical timing uses a probaility distribution to represent a delay or slew ranther than a single number. - Normal and skew normal probability distributions are supported. SSTA is enabled with the sta_pocv_mode variaable. - set sta_pocv_mode scalar|normal|skew_normalscalar mode is for non-SSTA analysisnormal mode uses gaussian normal distributionsskew_normal mode is for skew normal LVF moment based distributions - The target quantile of a delay probability distribution (confidence level) is set with the sta_pocv_quantile variable. - set sta_pocv_quantile <float> + Normal and skew normal probability distributions are supported. SSTA is enabled with the sta_pocv_mode variaable. + set sta_pocv_mode scalar|normal|skew_normalscalar mode is for non-SSTA analysisnormal mode uses gaussian normal distributionsskew_normal mode is for skew normal LVF moment based distributions + The target quantile of a delay probability distribution (confidence level) is set with the sta_pocv_quantile variable. + set sta_pocv_quantile <float> The default value is 3 standard deviations, or sigma. - Use the variance field with the report_checks and report_check_types commands to see distribution parameters in timing reports. - A command file for analyzing a design with statisical timing is shown below. - read_liberty lvf_library.lib.gzread_verilog design.vlink_design topcreate_clock -period 50 clkset_input_delay -clock clk 1 {in1 in2}set sta_pocv_mode skew_normalreport_checks -fields {slew variation input_pin variation} -digits 3 - Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)Path Group: clkPath Type: max Slew Delay Variation Time Description--------------------------------------------------------------------------- 0.000 0.000 0.000 clock clk (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 0.000 ^ r2/CK (FDPQ1) 12.026 mean 0.017 mean_shift 0.366 std_dev 0.000 skewness 4.648 12.409 12.409 v r2/Q (FFQ1) 4.648 0.000 12.409 v u1/A (BUF1) 6.084 mean 0.007 mean_shift 0.188 std_dev 0.000 skewness 2.513 6.137 18.546 v u1/X (BUF1) 2.513 0.000 18.546 v u2/A2 (AN21) 6.447 mean 0.008 mean_shift 0.191 std_dev 0.000 skewness 2.565 6.497 25.043 v u2/X (AN21) 2.565 0.000 25.043 v r3/D (FFQ1) 25.043 data arrival time 0.000 50.000 50.000 clock clk (rise edge) 0.000 50.000 clock network delay (ideal) 0.000 50.000 clock reconvergence pessimism 50.000 ^ r3/CK (FFQ1) -9.376 40.624 library setup time 40.624 data required time--------------------------------------------------------------------------- 40.624 data required time -25.043 data arrival time--------------------------------------------------------------------------- 15.581 slack (MET) + Use the variance field with the report_checks and report_check_types commands to see distribution parameters in timing reports. + A command file for analyzing a design with statisical timing is shown below. + read_liberty lvf_library.lib.gzread_verilog design.vlink_design topcreate_clock -period 50 clkset_input_delay -clock clk 1 {in1 in2}set sta_pocv_mode skew_normalreport_checks -fields {slew variation input_pin variation} -digits 3 + Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)Path Group: clkPath Type: max Slew Delay Variation Time Description--------------------------------------------------------------------------- 0.000 0.000 0.000 clock clk (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 0.000 ^ r2/CK (FDPQ1) 12.026 mean 0.017 mean_shift 0.366 std_dev 0.000 skewness 4.648 12.409 12.409 v r2/Q (FFQ1) 4.648 0.000 12.409 v u1/A (BUF1) 6.084 mean 0.007 mean_shift 0.188 std_dev 0.000 skewness 2.513 6.137 18.546 v u1/X (BUF1) 2.513 0.000 18.546 v u2/A2 (AN21) 6.447 mean 0.008 mean_shift 0.191 std_dev 0.000 skewness 2.565 6.497 25.043 v u2/X (AN21) 2.565 0.000 25.043 v r3/D (FFQ1) 25.043 data arrival time 0.000 50.000 50.000 clock clk (rise edge) 0.000 50.000 clock network delay (ideal) 0.000 50.000 clock reconvergence pessimism 50.000 ^ r3/CK (FFQ1) -9.376 40.624 library setup time 40.624 data required time--------------------------------------------------------------------------- 40.624 data required time -25.043 data arrival time--------------------------------------------------------------------------- 15.581 slack (MET) The standard deviation for normal distributions is specified with the following liberty timing groups. ocv_sigma_cell_riseocv_sigma_cell_fallocv_sigma_rise_transitionocv_sigma_fall_transitionocv_sigma_rise_constraintocv_sigma_fall_constraint LVF skew normal distributions are specified with liberty groups below. ocv_std_dev_cell_riseocv_std_dev_cell_fallocv_mean_shift_cell_riseocv_mean_shift_cell_fallocv_skewness_cell_riseocv_skewness_cell_fallocv_std_dev_rise_transitionocv_std_dev_fall_transitionocv_skewness_rise_transitionocv_skewness_fall_transitionocv_mean_shift_rise_transitionocv_mean_shift_fall_transitionocv_std_dev_rise_constraintocv_std_dev_fall_constraintocv_skewness_rise_constraintocv_skewness_fall_constraintocv_mean_shift_rise_constraintocv_mean_shift_fall_constraint - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power - In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power + In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. Group Internal Switching Leakage Total Power Power Power Power (Watts)----------------------------------------------------------------Sequential 3.27e-04 7.87e-05 2.96e-10 4.06e-04 36.4%Combinational 2.34e-04 3.10e-04 6.95e-10 5.43e-04 48.7%Clock 4.68e-05 1.20e-04 2.30e-11 1.67e-04 15.0%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%----------------------------------------------------------------Total 6.07e-04 5.09e-04 1.01e-09 1.12e-03 100.0% 54.4% 45.6% 0.0% - This example can be found in examples/power.tcl. - Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. + This example can be found in examples/power.tcl. + Gate level simulation results can be used to get a more accurate power estimate. For example, the Icarus verilog simulator can be used to run the the test bench examples/gcd_tb.v for the gcd design in the previous example. iverilog -o gcd_tb gcd_tb.vvvp gcd_tb - The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. - read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power - This example can be found in examples/power_vcd.tcl. + The test bench writes the VCD (Value Change Data) file gcd_sky130hd.vcd which can then be read with the read_vcd command. + read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power + This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-scene scene] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-scene scene] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. - report_checks -to out1 > path.logreport_checks -to out2 >> path.log - Debugging Timing + Many reporting commands support redirection of the output to a file much like a Unix shell. + report_checks -to out1 > path.logreport_checks -to out2 >> path.log + Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. Debugging timing problems generally involves using the following commands to follow the propagation of arrival times from a known arrival downstream to understand why the arrival times are not propagating: report_edgesreport_arrivalsreport_net - report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. + report_edges -from can be used to walk forward and report_edges -to to walk backward in the netlist/timing graph. report_arrivals shows the min/max rise/fall arrival times with respect to each clock that has a path to the pin. report_net shows connections to a net across hierarchy levels. No paths found - The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. + The report_checks command only reports paths that are constrained by timing checks or SDC commands such as set_output_delay. If the design has only combinational logic (no registers or latches), there are no timing checks, so no paths are reported. Use the -unconstrained option to report_checks to see unconstrained paths. % report_checks -unconstrained If the design is sequential (has registers or latches) and no paths are reported, it is likely that there is a problem with the clock propagation. Check the timing at an register in the design with the report_arrivals command. % report_arrivals r1/CP (clk ^) r 0.00:0.00 f INF:-INF (clk v) r INF:-INF f 5.00:5.00 - In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. + In this example the rising edge of the clock "clk" causes the rising arrival min:max time at 0.00, and the falling edge arrives at 5.00. Since the rising edge of the clock causes the rising edge of the register clock pin, the clock path is positive unate. The clock path should be positive or negative unate. Something is probably wrong with the clock network if it is non-unate. A non-unate clock path will report arrivals similar to the foillowing: % report_arrivals r1/CP (clk ^) r 0.00:0.00 f 0.00:0.00 (clk v) r 5.00:5.00 f 5.00:5.00 Notice that each clock edge causes both rise and fall arrivals at the register clock pin. - If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. + If there are no paths to the register clock pin, nothing is printed. Use the report_edges -to command to find the gate driving the clock pin. % report_edges -to r1/CPi1/ZN -> CP wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. + This shows that the gate/pin i1/ZN is driving the clock pin. The report_edges -to commond can be used to walk backward or forward through the netlist one gate/net at a time. By checking the arrivals with the report_arrival command you can determine where the path is broken. No path reported an endpoint - In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. + In order for a timing check to be reported, there must be an arrival time at the data pin (the constrained pin) as well as the timing check clock pin. If report_checks -to a register input does not report any paths, check that the input is constrained by a timing check with report_edges -to. % report_edges -to r1/DCP -> D hold ^ -> ^ -0.04:-0.04 ^ -> v -0.03:-0.03CP -> D setup ^ -> ^ 0.09:0.0 ^ -> v 0.08:0.08in1 -> D wire ^ -> ^ 0.00:0.00 v -> v 0.00:0.00 - This reports the setup and hold checks for the D pin of r1. + This reports the setup and hold checks for the D pin of r1. Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6711,7 +6718,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6732,7 +6739,7 @@ - all_outputs + all_outputs @@ -6746,15 +6753,15 @@ - all_registers + all_registers - [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] + [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] - -clock clock_names + -clock clock_names A list of clock names. Only registers clocked by these clocks are returned. @@ -6817,21 +6824,21 @@ - The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. + The all_registers command returns a list of register instances or register pins in the design. Options allow the list of registers to be restricted in various ways. The -clock keyword restrcts the registers to those that are clocked by a set of clocks. The -cells option returns the list of registers or latches (the default). The -‑data_pins, -clock_pins, -async_pins and -output_pins options cause all_registers to return a list of register pins rather than instances. - check_setup + check_setup - [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] + [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] - -verbose + -verbose Show offending objects rather than just error counts. @@ -6839,7 +6846,7 @@ - -unconstrained_endpoints + -unconstrained_endpoints Check path endpoints for timing constraints (timing check or set_output_delay). @@ -6847,7 +6854,7 @@ - -multiple_clock + -multiple_clock Check register/latch clock pins for multiple clocks. @@ -6864,7 +6871,7 @@ - -no_input_delay + -no_input_delay Check for inputs that do not have a set_input_delay command. @@ -6887,16 +6894,16 @@ - The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. + The check_setup command performs sanity checks on the design. Individual checks can be performed with the keywords. If no check keywords are specified all checks are performed. Checks that fail are reported as warnings. If no checks fail nothing is reported. The command returns 1 if there are no warnings for use in scripts. - connect_pin + connect_pin - netport|pin + netport|pin @@ -6924,7 +6931,7 @@ - The connect_pin command connects a port or instance pin to a net. + The connect_pin command connects a port or instance pin to a net. @@ -6965,7 +6972,7 @@ -add - Add this clock to the clocks on pin_list. + Add this clock to the clocks on pin_list. @@ -6978,7 +6985,7 @@ The create_clock command defines the waveform of a clock used by the design. - If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. + If no pin_list is specified the clock is virtual. A virtual clock can be refered to by name in input arrival and departure time commands but is not attached to any pins in the design. If no clock name is specified the name of the first pin is used as the clock name. If a wavform is not specified the clock rises at zero and falls at half the clock period. The waveform is a list with time the clock rises as the first element and the time it falls as the second element. If a clock is already defined on a pin the clock is redefined using the new clock parameters. If multiple clocks drive the same pin, use the -add option to prevent the existing definition from being overwritten. @@ -6991,10 +6998,10 @@ - create_generated_clock + create_generated_clock - [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list + [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -7010,36 +7017,36 @@ -source master_pin - A pin or port in the fanout of the master clock that is the source of the generated clock. + A pin or port in the fanout of the master clock that is the source of the generated clock. - -master_clock master_clock + -master_clock master_clock - Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. + Use -master_clock to specify which source clock to use when multiple clocks are present on master_pin. - -divide_by divisor + -divide_by divisor - Divide the master clock period by divisor. + Divide the master clock period by divisor. - -multiply_by multiplier + -multiply_by multiplier - Multiply the master clock period by multiplier. + Multiply the master clock period by multiplier. - -duty_cycle duty_cycle + -duty_cycle duty_cycle The percent of the period that the generated clock is high (between 0 and 100). @@ -7056,15 +7063,15 @@ - -edges edge_list + -edges edge_list - List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. + List of master clock edges to use in the generated clock. Edges are numbered from 1. edge_list must be 3 edges long. - -edge_shift shift_list + -edge_shift shift_list Not supported. @@ -7075,7 +7082,7 @@ -add - Add this clock to the existing clocks on pin_list. + Add this clock to the existing clocks on pin_list. @@ -7083,7 +7090,7 @@ pin_list - A list of pins driven by the generated clock. + A list of pins driven by the generated clock. @@ -7108,10 +7115,10 @@ - create_voltage_area + create_voltage_area - [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells + [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -7121,7 +7128,7 @@ - current_design + current_design [design] @@ -7134,7 +7141,7 @@ - current_instance + current_instance [instance] @@ -7155,23 +7162,23 @@ - define_scene + define_scene - -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file + -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file - mode_name + mode_name - The SDC mode to use. + The SDC mode to use. - liberty_files + liberty_files List of Liberty files to use. @@ -7186,18 +7193,18 @@ - The define_scene command defines a scene for a mode (SDC), liberty files and spef parasitics. Define scenes after reading Liberty libraries and SPEF parasitics.Liberty files are specifiec with the name of the liberty library or the filename of the liberty file. If a filename is used, it must be the same as the filename used to read the library with read_liberty.. - Use get_scenes to find defined scenes. + The define_scene command defines a scene for a mode (SDC), liberty files and spef parasitics. Define scenes after reading Liberty libraries and SPEF parasitics.Liberty files are specifiec with the name of the liberty library or the filename of the liberty file. If a filename is used, it must be the same as the filename used to read the library with read_liberty.. + Use get_scenes to find defined scenes. - delete_clock + delete_clock - [-all] clocks + [-all] clocks @@ -7215,7 +7222,7 @@ - delete_from_list + delete_from_list list objects @@ -7226,7 +7233,7 @@ list - A list of objects. + A list of objects. @@ -7244,10 +7251,10 @@ - delete_generated_clock + delete_generated_clock - [-all] clocks + [-all] clocks @@ -7265,7 +7272,7 @@ - delete_instance + delete_instance instance @@ -7276,7 +7283,7 @@ instance - Instance to delete. + Instance to delete. @@ -7286,7 +7293,7 @@ - delete_net + delete_net net @@ -7294,7 +7301,7 @@ - net + net Net to delete. @@ -7307,10 +7314,10 @@ - disconnect_pin + disconnect_pin - netport | pin | -all + netport | pin | -all @@ -7353,7 +7360,7 @@ - elapsed_run_time + elapsed_run_time @@ -7366,83 +7373,83 @@ - find_timing_paths + find_timing_paths - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] - -from from_list + -from from_list - Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Return paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Return paths through a list of instances, pins or nets. + Return paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Return rising paths through a list of instances, pins or nets. + Return rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Return falling paths through a list of instances, pins or nets. + Return falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Return paths to a list of clocks, instances, ports or pins. + Return paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Return rising paths to a list of clocks, instances, ports or pins. + Return rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Return falling paths to a list of clocks, instances, ports or pins. + Return falling paths to a list of clocks, instances, ports or pins. @@ -7450,7 +7457,7 @@ -unconstrained - Report unconstrained paths also. + Report unconstrained paths also. @@ -7511,18 +7518,18 @@ - -group_path_count path_count + -group_path_count path_count - The number of paths to return in each path group. + The number of paths to return in each path group. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to return for each endpoint. + The number of paths to return for each endpoint. @@ -7535,7 +7542,7 @@ - -scene scene + -scene scene Return paths for one process corner. @@ -7543,18 +7550,18 @@ - -slack_max max_slack + -slack_max max_slack - Return paths with slack less than max_slack. + Return paths with slack less than max_slack. - -slack_min min_slack + -slack_min min_slack - Return paths with slack greater than min_slack. + Return paths with slack greater than min_slack. @@ -7562,15 +7569,15 @@ -sort_by_slack - Sort paths by slack rather than slack within path groups. + Sort paths by slack rather than slack within path groups. - -path_group groups + -path_group groups - Return paths in path groups. Paths in all groups are returned if this option is not specified. + Return paths in path groups. Paths in all groups are returned if this option is not specified. @@ -7580,10 +7587,10 @@ - get_cells + get_cells - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7596,18 +7603,18 @@ - -hsc separator + -hsc separator - Character to use to separate hierarchical instance names in patterns. + Character to use to separate hierarchical instance names in patterns. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7615,7 +7622,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7636,7 +7643,7 @@ - -of_objects objects + -of_objects objects The name of a pin or net, a list of pins returned by get_pins, or a list of nets returned by get_nets. The –hierarchical option cannot be used with ‑of_objects. @@ -7657,10 +7664,10 @@ - get_clocks + get_clocks - [-regexp][-nocase][-filter expr][-quiet]patterns + [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7668,7 +7675,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7682,10 +7689,10 @@ - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7711,15 +7718,15 @@ - get_fanin + get_fanin - -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -to sink_list + -to sink_list List of pins, ports, or nets to find the fanin of. For nets, the fanin of driver pins on the nets are returned. @@ -7727,7 +7734,7 @@ - -flat + -flat With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. @@ -7735,7 +7742,7 @@ - -only_cells + -only_cells Return the instances connected to the pins in the fanin. @@ -7743,7 +7750,7 @@ - -startpoints_only + -startpoints_only Only return pins that are startpoints. @@ -7751,7 +7758,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7767,15 +7774,15 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled Only trace through timing arcs that are not disabled. @@ -7783,7 +7790,7 @@ - -trace_arcs all + -trace_arcs all Trace through all arcs, including disabled ones. @@ -7797,15 +7804,15 @@ - get_fanout + get_fanout - -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] + -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] - -from source_list + -from source_list List of pins, ports, or nets to find the fanout of. For nets, the fanout of load pins on the nets are returned. @@ -7813,7 +7820,7 @@ - -flat + -flat With –flat pins in the fanin at any hierarchy level are returned. Without ‑flat only pins at the same hierarchy level as the sinks are returned. @@ -7821,7 +7828,7 @@ - -only_cells + -only_cells Return the instances connected to the pins in the fanout. @@ -7829,7 +7836,7 @@ - -endpoints_only + -endpoints_only Only return pins that are endpoints. @@ -7837,7 +7844,7 @@ - -level level_count + -level level_count Only return pins within level_count instance traversals. @@ -7853,15 +7860,15 @@ - -trace_arcs timing + -trace_arcs timing - Only trace through timing arcs that are not disabled. + Only trace through timing arcs that are not disabled. - -trace_arcs enabled + -trace_arcs enabled Only trace through timing arcs that are not disabled. @@ -7869,7 +7876,7 @@ - -trace_arcs all + -trace_arcs all Trace through all arcs, including disabled ones. @@ -7882,7 +7889,7 @@ - get_full_name + get_full_name object @@ -7907,12 +7914,12 @@ get_lib_cells - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - -of_objects objects + -of_objects objects A list of instance objects. @@ -7923,15 +7930,15 @@ -hsc separator - Character that separates the library name and cell name in patterns. Defaults to ‘/’. + Character that separates the library name and cell name in patterns. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -7939,7 +7946,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -7960,7 +7967,7 @@ - patterns + patterns A list of library cell name patterns of the form library_name/cell_name. @@ -7973,18 +7980,18 @@ - get_lib_pins + get_lib_pins - [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns + [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns - -of_objects objects + -of_objects objects - A list of library cell objects. + A list of library cell objects. @@ -7992,16 +7999,16 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8009,7 +8016,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8043,18 +8050,18 @@ - get_libs + get_libs - [-filter expr][-regexp][-nocase][-quiet]patterns + [-filter expr][-regexp][-nocase][-quiet]patterns - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8062,7 +8069,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8090,17 +8097,17 @@ - The get_libs command returns a list of clocks that match patterns. + The get_libs command returns a list of clocks that match patterns. - get_nets + get_nets - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8116,15 +8123,15 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8132,7 +8139,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8174,7 +8181,7 @@ - get_name + get_name object @@ -8196,10 +8203,10 @@ - get_pins + get_pins - [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8215,15 +8222,15 @@ -hsc separator - Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. + Character that separates the library name, cell name and port name in pattern. Defaults to ‘/’. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8247,7 +8254,7 @@ -of_objects objects - The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. + The name of a net or instance, a list of nets returned by get_nets, or a list of instances returned by get_cells. The –hierarchical option cannot be used with –of_objects. @@ -8267,19 +8274,19 @@ - get_ports + get_ports - [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] + [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. @@ -8287,7 +8294,7 @@ -regexp - Use regular expression matching instead of glob pattern matching. + Use regular expression matching instead of glob pattern matching. @@ -8308,10 +8315,10 @@ - -of_objects objects + -of_objects objects - The name of net or a list of nets returned by get_nets. + The name of net or a list of nets returned by get_nets. @@ -8329,18 +8336,18 @@ - get_property + get_property - [-object_type object_type]objectproperty + [-object_type object_type]objectproperty - -object_type object_type + -object_type object_type - The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc + The type of object when it is specified as a name.cell|pin|net|port|clock|library|library_cell|library_pin|timing_arc @@ -8348,7 +8355,7 @@ object - An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. + An object returned by get_cells, get_pins, get_nets, get_ports, get_clocks, get_libs, get_lib_cells, get_lib_pins, or get_timing_arcs, or object name. ‑object_type is required if object is a name. @@ -8362,28 +8369,28 @@ The properties for different objects types are shown below. cell (SDC lib_cell) - base_namefilenamefull_namelibraryname + base_namefilenamefull_namelibraryname clock - full_nameis_generatedis_propagatedis_virtualnameperiodsources + full_nameis_generatedis_propagatedis_virtualnameperiodsources edge - delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin - instance (SDC cell) - cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name - liberty_cell (SDC lib_cell) - areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname - liberty_port (SDC lib_pin) - capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname + delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin + instance (SDC cell) + cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name + liberty_cell (SDC lib_cell) + areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname + liberty_port (SDC lib_pin) + capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname library - filename (Liberty library only)namefull_name + filename (Liberty library only)namefull_name net - full_namename + full_namename path (PathEnd) endpointendpoint_clockendpoint_clock_pinslackstartpointstartpoint_clockpoints pin - activity (activity in transitions per second, duty cycle, origin)origin is one ofglobalset_power_activity -globalinputset_power_activity -inputuserset_power_activity -input_ports -pinsvcdread_vcdsaifread_saifpropagatedpropagated from upstream activitiesclockSDC create_clock or create_generated_clockconstantconstant pins propagated from verilog tie high/low, set_case_analysis, set_logic_one/zero/dc - slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + activity (activity in transitions per second, duty cycle, origin)origin is one ofglobalset_power_activity -globalinputset_power_activity -inputuserset_power_activity -input_ports -pinsvcdread_vcdsaifread_saifpropagatedpropagated from upstream activitiesclockSDC create_clock or create_generated_clockconstantconstant pins propagated from verilog tie high/low, set_case_analysis, set_logic_one/zero/dc + slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise port - activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise point (PathRef) arrivalpinrequiredslack @@ -8391,15 +8398,15 @@ - get_scenes + get_scenes - [-mode mode_name]scene_name + [-mode mode_name]scene_name - mode_name + mode_name Get the scenes for mode_name. @@ -8407,7 +8414,7 @@ - scene_name + scene_name A scene name pattern. @@ -8420,61 +8427,61 @@ - get_timing_edges + get_timing_edges - [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] + [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] - -from from_pin + -from from_pin - A list of pins. + A list of pins. - -to to_pin + -to to_pin - A list of pins. + A list of pins. - -of_objects objects + -of_objects objects - A list of instances or library cells. The –from and -to options cannot be used with –of_objects. + A list of instances or library cells. The –from and -to options cannot be used with –of_objects. - -filter expr + -filter expr - A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. + A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. + The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. - group_path + group_path - -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] + -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] - -name group_name + -name group_name The name of the path group. @@ -8482,7 +8489,7 @@ - -weight weight + -weight weight Not supported. @@ -8490,7 +8497,7 @@ - -critical_range range + -critical_range range Not supported. @@ -8498,74 +8505,74 @@ - -from from_list + -from from_list - Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Group paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Group paths through a list of instances, pins or nets. + Group paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Group rising paths through a list of instances, pins or nets. + Group rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Group falling paths through a list of instances, pins or nets. + Group falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Group paths to a list of clocks, instances, ports or pins. + Group paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Group rising paths to a list of clocks, instances, ports or pins. + Group rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Group falling paths to a list of clocks, instances, port-s or pins. + Group falling paths to a list of clocks, instances, port-s or pins. @@ -8583,15 +8590,15 @@ - include + include - [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] + [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] - -echo|-e + -echo|-e Print each command before evaluating it. @@ -8599,7 +8606,7 @@ - -verbose|-v + -verbose|-v Print each command before evaluating it as well as the result it returns. @@ -8615,7 +8622,7 @@ - > log_filename + > log_filename Redirect command output to log_filename. @@ -8623,7 +8630,7 @@ - >> log_filename + >> log_filename Redirect command output and append log_filename. @@ -8631,29 +8638,29 @@ Read STA/SDC/Tcl commands from filename. - The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. + The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. - link_design + link_design - [-no_black_boxes][cell_name] + [-no_black_boxes][cell_name] - -no_black_boxes + -no_black_boxes - Do not make empty “black box” cells for instances that reference undefined cells. + Do not make empty “black box” cells for instances that reference undefined cells. - cell_name + cell_name The top level module/cell name of the design hierarchy to link. @@ -8668,7 +8675,7 @@ - make_instance + make_instance inst_pathlib_cell @@ -8692,13 +8699,13 @@ - The make_instance command makes an instance of library cell lib_cell. + The make_instance command makes an instance of library cell lib_cell. - make_net + make_net net_name_list @@ -8719,18 +8726,18 @@ - read_liberty + read_liberty - [-corner corner][-min][-max][-infer_latches]filename + [-corner corner][-min][-max][-infer_latches]filename - -corner corner + -corner corner - Use the library for process corner corner delay calculation. + Use the library for process corner corner delay calculation. @@ -8754,12 +8761,12 @@ filename - The liberty file name to read. + The liberty file name to read. The read_liberty command reads a Liberty format library file. The first library that is read sets the units used by SDC/TCL commands and reporting. The include_file attribute is supported. - Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: + Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} In this example a positive level-sensitive latch is inferred. Files compressed with gzip are automatically uncompressed. @@ -8768,18 +8775,18 @@ - read_saif + read_saif - [-scope scope]filename + [-scope scope]filename - scope + scope - The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. @@ -8787,26 +8794,26 @@ filename - The name of the SAIF file to read. + The name of the SAIF file to read. - The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_sdc + read_sdc - [-mode mode_name][-echo]filename + [-mode mode_name][-echo]filename - mode_name + mode_name Mode for the SDC commands in the file. @@ -8838,15 +8845,15 @@ - read_sdf + read_sdf - [-scene scene][-unescaped_dividers]filename + [-scene scene][-unescaped_dividers]filename - scene + scene Scene delays to annotate. @@ -8854,7 +8861,7 @@ - -unescaped_dividers + -unescaped_dividers With this option path names in the SDF do not have to escape hierarchy dividers when the path name is escaped. For example, the escaped Verilog name "\inst1/inst2 " can be referenced as "inst1/inst2". The correct SDF name is "inst1\/inst2", since the divider does not represent a change in hierarchy in this case. @@ -8869,7 +8876,7 @@ - Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. + Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. Files compressed with gzip are automatically uncompressed. INCREMENT is supported as an alias for INCREMENTAL. The following SDF statements are not supported. @@ -8879,10 +8886,10 @@ - read_spef + read_spef - [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename + [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename @@ -8898,7 +8905,7 @@ path - Hierarchical block instance path to annotate with parasitics. + Hierarchical block instance path to annotate with parasitics. @@ -8914,7 +8921,7 @@ ‑coupling_reduction_factorfactor - Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. + Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. @@ -8926,29 +8933,29 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. - Separate min/max parasitics can be annotated for each scene mode/corner. - read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max + Separate min/max parasitics can be annotated for each scene mode/corner. + read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. The following SPEF constructs are ignored. *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - read_vcd + read_vcd - [-scope scope][-mode mode_name]filename + [-scope scope][-mode mode_name]filename - scope + scope The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. @@ -8967,17 +8974,17 @@ filename - The name of the VCD file to read. + The name of the VCD file to read. - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog filename @@ -8992,8 +8999,8 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. - Verilog 2001 module port declaratations are supported. An example is shown below. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -9001,16 +9008,16 @@ - replace_cell + replace_cell - instance_listreplacement_cell + instance_listreplacement_cell - instance_list + instance_list A list of instances to swap the cell. @@ -9018,57 +9025,57 @@ - replacement_cell + replacement_cell The replacement lib cell. - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. - replace_activity_annotation + replace_activity_annotation - [-report_unannotated][-report_annotated] + [-report_unannotated][-report_annotated] - -report_unannotated + -report_unannotated - Report unannotated pins. + Report unannotated pins. - -report_unannotated + -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check - [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] + [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] - -setup + -setup Report annotated setup checks. @@ -9076,7 +9083,7 @@ - -hold + -hold Report annotated hold checks. @@ -9084,7 +9091,7 @@ - -recovery + -recovery Report annotated recovery checks. @@ -9092,7 +9099,7 @@ - -removal + -removal Report annotated removal checks. @@ -9100,7 +9107,7 @@ - -nochange + -nochange Report annotated nochange checks. @@ -9108,7 +9115,7 @@ - -width + -width Report annotated width checks. @@ -9116,7 +9123,7 @@ - -period + -period Report annotated period checks. @@ -9124,7 +9131,7 @@ - -max_skew + -max_skew Report annotated max skew checks. @@ -9133,26 +9140,26 @@ - -max_line lines + -max_line lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9164,21 +9171,21 @@ - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] - -cell + -cell Report annotated cell delays. @@ -9186,7 +9193,7 @@ - -net + -net Report annotated internal net delays. @@ -9194,7 +9201,7 @@ - -from_in_ports + -from_in_ports Report annotated delays from input ports. @@ -9202,7 +9209,7 @@ - -to_out_ports + -to_out_ports Report annotated delays to output ports. @@ -9210,26 +9217,26 @@ - -max_lines lines + -max_lines lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9241,90 +9248,90 @@ - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] - -from from_list + -from from_list - Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Report paths through a list of instances, pins or nets. + Report paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Report rising paths through a list of instances, pins or nets. + Report rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Report falling paths through a list of instances, pins or nets. + Report falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Report paths to a list of clocks, instances, ports or pins. + Report paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Report rising paths to a list of clocks, instances, ports or pins. + Report rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Report falling paths to a list of clocks, instances, ports or pins. + Report falling paths to a list of clocks, instances, ports or pins. @@ -9332,7 +9339,7 @@ -unconstrained - Report unconstrained paths also. The unconstrained path group is not reported without this option. + Report unconstrained paths also. The unconstrained path group is not reported without this option. @@ -9393,7 +9400,7 @@ - -group_path_count path_count + -group_path_count path_count The number of paths to report in each path group. The default is 1. @@ -9401,7 +9408,7 @@ - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count The number of paths to report for each endpoint. The default is 1. @@ -9412,15 +9419,15 @@ ‑unique_paths_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. - ‑unique_edges_to_endpoint + ‑unique_edges_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. @@ -9428,7 +9435,7 @@ scenes - Report paths for one process corner. The default is to report paths for all process corners. + Report paths for one process corner. The default is to report paths for all process corners. @@ -9458,10 +9465,10 @@ - groups + groups - List of path groups to report. The default is to report all path groups. + List of path groups to report. The default is to report all path groups. @@ -9514,10 +9521,10 @@ - -format json + -format json - Report in json format. -fields is ignored. + Report in json format. -fields is ignored. @@ -9525,7 +9532,7 @@ fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variance + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variance @@ -9545,7 +9552,7 @@ - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. See set_false_path for a description of allowed from_list, through_list and to_list objects. @@ -9553,10 +9560,10 @@ - report_check_types + report_check_types - [-scenes scenes][-violators][-verbose][-fields fields][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] + [-scenes scenes][-violators][-verbose][-fields fields][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] @@ -9564,12 +9571,12 @@ scenes - Report checks for some scenes. The default value is all scenes. + Report checks for some scenes. The default value is all scenes. - -violators + -violators Report all violated timing and design rule constraints. @@ -9585,18 +9592,18 @@ - -format slack_only + -format slack_only - Report the minimum slack for each timing check. + Report the minimum slack for each timing check. - -format end + -format end - Report the endpoint for each check. + Report the endpoint for each check. @@ -9604,7 +9611,7 @@ fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variance + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr|variance @@ -9698,7 +9705,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9719,10 +9726,10 @@ - report_clock_latency + report_clock_latency - [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] @@ -9730,7 +9737,7 @@ clocks - The clocks to report. The default value is all c + The clocks to report. The default value is all c @@ -9738,7 +9745,7 @@ scenes - Report clocks for scenes. The default value is all clocks in scenes modes. + Report clocks for scenes. The default value is all clocks in scenes modes. @@ -9764,10 +9771,10 @@ - report_clock_min_period + report_clock_min_period - [-clocks clocks][-scenes scenes][-include_port_paths] + [-clocks clocks][-scenes scenes][-include_port_paths] @@ -9787,16 +9794,16 @@ - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. - report_clock_properties + report_clock_properties - [clock_names] + [clock_names] @@ -9814,15 +9821,15 @@ - report_clock_skew + report_clock_skew - [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] - -setup + -setup Report skew for setup checks. @@ -9841,7 +9848,7 @@ clocks - The clocks to report. The default value is all clocks in scenes modes. + The clocks to report. The default value is all clocks in scenes modes. @@ -9849,7 +9856,7 @@ scenes - Report clocks for scenes. The default value is all scenes. + Report clocks for scenes. The default value is all scenes. @@ -9862,23 +9869,23 @@ - -digits digits + -digits digits The number of digits to report for delays. - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc - [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] + [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] @@ -9886,7 +9893,7 @@ from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. @@ -9894,7 +9901,7 @@ to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. @@ -9903,28 +9910,28 @@ scene - Report paths for process scene. The -scene keyword is required if more than one process corner is defined. + Report paths for process scene. The -scene keyword is required if more than one process corner is defined. - -min + -min - Report delay calculation for min delays. + Report delay calculation for min delays. - -max + -max - Report delay calculation for max delays. + Report delay calculation for max delays. - -digits digits + -digits digits The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9937,7 +9944,7 @@ - report_disabled_edges + report_disabled_edges @@ -9945,16 +9952,16 @@ The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges - [-from from_pin][-to to_pin][-report_variation][-digits digits] + [-from from_pin][-to to_pin][-report_variation][-digits digits] @@ -9962,7 +9969,7 @@ from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. @@ -9970,12 +9977,12 @@ to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. - -report_variation + -report_variation @@ -9986,21 +9993,21 @@ digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance - instance_path[> filename][>> filename] + instance_path[> filename][>> filename] @@ -10018,10 +10025,10 @@ - report_lib_cell + report_lib_cell - cell_name[> filename][>> filename] + cell_name[> filename][>> filename] @@ -10033,24 +10040,24 @@ - Describe the liberty library cell cell_name. + Describe the liberty library cell cell_name. - report_net + report_net - [-digits digits]net_path[> filename][>> filename] + [-digits digits]net_path[> filename][>> filename] - digits + digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10062,77 +10069,77 @@ - Report the connections and capacitance of a net. + Report the connections and capacitance of a net. - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] - -report_unannotated + -report_unannotated - Report unannotated and partially annotated nets. + Report unannotated and partially annotated nets. - Report SPEF parasitic annotation completeness. + Report SPEF parasitic annotation completeness. - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] - -instances instances + -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_slews + report_slews - [-scenes scenes][-report_variation][-digits digits]pin + [-scenes scenes][-report_variation][-digits digits]pin @@ -10140,133 +10147,133 @@ scenes - Report slews for process for scenes process corners. + Report slews for process for scenes process corners. - -report_variation + -report_variation - Report SSTA distribution parameters. + Report SSTA distribution parameters. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - pin + pin - + - Report the slews at pin + Report the slews at pin - report_tns + report_tns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the total max/setup slack. + Report the total max/setup slack. - -min + -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the total negative slack. + Report the total negative slack. - report_units + report_units - Report the units used for command arguments and reporting. + Report the units used for command arguments and reporting. report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um - report_wns + report_wns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the worst max/setup slack. + Report the worst max/setup slack. - -min + -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the worst negative slack. If the worst slack is positive, zero is reported. + Report the worst negative slack. If the worst slack is positive, zero is reported. - report_worst_slack + report_worst_slack - [-min][-max][-digits digits] + [-min][-max][-digits digits] @@ -10275,7 +10282,7 @@ -max - Report the worst max/setup slack. + Report the worst max/setup slack. @@ -10283,12 +10290,12 @@ -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10301,10 +10308,10 @@ - set_assigned_check + set_assigned_check - -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin + -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -10312,7 +10319,7 @@ -setup - Annotate setup timing checks. + Annotate setup timing checks. @@ -10320,7 +10327,7 @@ -hold - Annotate hold timing checks. + Annotate hold timing checks. @@ -10328,7 +10335,7 @@ -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. @@ -10336,7 +10343,7 @@ -removal - Annotate removal timing checks. + Annotate removal timing checks. @@ -10357,10 +10364,10 @@ - scene + scene - The name of a scene. The -scene keyword is required if more than one scene is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. @@ -10398,10 +10405,10 @@ - -clock rise|fall + -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. @@ -10409,7 +10416,7 @@ margin - The timing check margin. + The timing check margin. @@ -10419,10 +10426,10 @@ - set_assigned_delay + set_assigned_delay - -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay + -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay @@ -10459,10 +10466,10 @@ - scene + scene - The name of a scene. The -scene keyword is required if more than one scene is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. @@ -10513,10 +10520,10 @@ - set_assigned_transition + set_assigned_transition - [-rise][-fall][-scene scene][-min][-max]slewpin_list + [-rise][-fall][-scene scene][-min][-max]slewpin_list @@ -10537,10 +10544,10 @@ - scene + scene - Annotate delays for scene. + Annotate delays for scene. @@ -10582,10 +10589,10 @@ - set_case_analysis + set_case_analysis - 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list + 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10598,22 +10605,22 @@ The set_case_analysis command sets the signal on a port or pin to a constant logic value. No paths are propagated from constant pins. Constant values set with the set_case_analysis command are propagated through downstream gates. - Conditional timing arcs with mode groups are controlled by logic values on the instance pins. + Conditional timing arcs with mode groups are controlled by logic values on the instance pins. - set_clock_gating_check + set_clock_gating_check - [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] + [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] - -setup setup_time + -setup setup_time Clock enable setup margin. @@ -10621,7 +10628,7 @@ - -hold hold_time + -hold hold_time Clock enable hold margin. @@ -10678,18 +10685,18 @@ - set_clock_groups + set_clock_groups - [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks + [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks - -name name + -name name - The clock group name. + The clock group name. @@ -10697,7 +10704,7 @@ -logically_exclusive - The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. + The clocks in different groups do not interact logically but can be physically present on the same chip. Paths between clock groups are considered for noise analysis. @@ -10706,7 +10713,7 @@ -physically_exclusive - The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. + The clocks in different groups cannot be present at the same time on a chip. Paths between clock groups are not considered for noise analysis. @@ -10714,7 +10721,7 @@ -asynchronous - The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. + The clock groups are asynchronous. Paths between clock groups are considered for noise analysis. @@ -10727,7 +10734,7 @@ - clocks + clocks A list of clocks in the group. @@ -10740,15 +10747,15 @@ - set_clock_latency + set_clock_latency - [-source][-clock clock][-rise][-fall][-min][-max]delayobjects + [-source][-clock clock][-rise][-fall][-min][-max]delayobjects - -source + -source The latency is at the clock source. @@ -10756,7 +10763,7 @@ - -clock clock + -clock clock If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. @@ -10811,16 +10818,16 @@ - The set_clock_latency command describes expected delays of the clock tree when anxsalyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function.set_clock_latency removes propagated clock properties for the clocks and pins objects. + The set_clock_latency command describes expected delays of the clock tree when anxsalyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function.set_clock_latency removes propagated clock properties for the clocks and pins objects. - set_clock_transition + set_clock_transition - [-rise][-fall][-min][-max]transitionclocks + [-rise][-fall][-min][-max]transitionclocks @@ -10828,7 +10835,7 @@ -rise - Set the transition time for the rising edge of the clock. + Set the transition time for the rising edge of the clock. @@ -10836,7 +10843,7 @@ -fall - Set the transition time for the falling edge of the clock. + Set the transition time for the falling edge of the clock. @@ -10844,7 +10851,7 @@ -min - Set the min transition time. + Set the min transition time. @@ -10852,7 +10859,7 @@ -max - Set the min transition time. + Set the min transition time. @@ -10878,26 +10885,26 @@ - set_clock_uncertainty + set_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] - -from from_clock + -from from_clock - Inter-clock uncertainty source clock. + Inter-clock uncertainty source clock. - -to to_clock + -to to_clock - Inter-clock uncertainty target clock. + Inter-clock uncertainty target clock. @@ -10905,7 +10912,7 @@ -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. @@ -10913,7 +10920,7 @@ -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. @@ -10921,7 +10928,7 @@ -setup - uncertainty is for setup checks. + uncertainty is for setup checks. @@ -10930,12 +10937,12 @@ -hold - uncertainty is for hold checks. + uncertainty is for hold checks. - uncertainty + uncertainty Clock uncertainty. @@ -10950,81 +10957,81 @@ - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - -distance distance_unit + -distance distance_unit - The distance scale factor followed by 'm'. + The distance scale factor followed by 'm'. - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -11034,15 +11041,15 @@ - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin A pin used as the timing check reference. @@ -11050,7 +11057,7 @@ - -to to_pin + -to to_pin A pin that the setup/hold check is applied to. @@ -11074,7 +11081,7 @@ - -clock clock + -clock clock The setup/hold check clock. @@ -11095,7 +11102,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -11110,32 +11117,32 @@ - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. - set_disable_timing + set_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects - -from from_port + -from from_port - + - -to to_port + -to to_port - + @@ -11143,12 +11150,12 @@ objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. - All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. + All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. set_disable_timing u2 The -from and -to options can be used to restrict the disabled path to those from, to or between specific pins on the instance. set_disable_timing -from A u2set_disable_timing -to Z u2set_disable_timing -from A -to Z u2 @@ -11161,10 +11168,10 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports @@ -11172,7 +11179,7 @@ -rise - Set the drive rise resistance. + Set the drive rise resistance. @@ -11180,7 +11187,7 @@ -fall - Set the drive fall resistance. + Set the drive fall resistance. @@ -11188,7 +11195,7 @@ -max - Set the maximum resistance. + Set the maximum resistance. @@ -11196,7 +11203,7 @@ -min - Set the minimum resistance. + Set the minimum resistance. @@ -11209,7 +11216,7 @@ - ports + ports A list of ports. @@ -11222,26 +11229,26 @@ - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports - -lib_cell cell_name + -lib_cell cell_name - The driving cell. + The driving cell. - -library library + -library library - The driving cell library. + The driving cell library. @@ -11249,7 +11256,7 @@ -rise - Set the driving cell for a rising edge. + Set the driving cell for a rising edge. @@ -11258,7 +11265,7 @@ -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. @@ -11266,7 +11273,7 @@ -max - Set the driving cell for max delays. + Set the driving cell for max delays. @@ -11274,12 +11281,12 @@ -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin The output port of the driving cell. @@ -11287,31 +11294,31 @@ - -from_pin from_pin + -from_pin from_pin - Use timing arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. - -input_transition_rise trans_rise + -input_transition_rise trans_rise - The transition time for a rising input at from_pin. + The transition time for a rising input at from_pin. - -input_transition_fall trans_fall + -input_transition_fall trans_fall - The transition time for a falling input at from_pin. + The transition time for a falling input at from_pin. - ports + ports A list of ports. @@ -11324,10 +11331,10 @@ - set_false_path + set_false_path - [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] + [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -11335,7 +11342,7 @@ -setup - Apply to setup checks. + Apply to setup checks. @@ -11343,7 +11350,7 @@ -hold - Apply to hold checks. + Apply to hold checks. @@ -11351,7 +11358,7 @@ -rise - Apply to rising path edges. + Apply to rising path edges. @@ -11359,7 +11366,7 @@ -fall - Apply to falling path edges. + Apply to falling path edges. @@ -11373,7 +11380,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11381,7 +11388,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11389,7 +11396,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11405,10 +11412,10 @@ - set_fanout_load + set_fanout_load - fanoutport_list + fanoutport_list @@ -11418,7 +11425,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11439,7 +11446,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11452,7 +11459,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11465,7 +11472,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11478,10 +11485,10 @@ - set_input_delay + set_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11489,7 +11496,7 @@ -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. @@ -11497,7 +11504,7 @@ -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. @@ -11505,7 +11512,7 @@ -max - Set the maximum arrival time. + Set the maximum arrival time. @@ -11513,15 +11520,15 @@ -min - Set the minimum arrival time. + Set the minimum arrival time. - -clock clock + -clock clock - The arrival time is from clock. + The arrival time is from clock. @@ -11529,12 +11536,12 @@ -clock_fall - The arrival time is from the falling edge of clock. + The arrival time is from the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin The arrival time is with respect to the clock that arrives at ref_pin. @@ -11545,7 +11552,7 @@ -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. @@ -11553,7 +11560,7 @@ -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. @@ -11581,22 +11588,22 @@ - The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. - set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] - The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + The set_input_delay command is used to specify the arrival time of an input signal. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + set_input_delay -clock clk1 1.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - set_input_transition + set_input_transition - [-rise][-fall][-max][-min]transitionport_list + [-rise][-fall][-max][-min]transitionport_list @@ -11604,7 +11611,7 @@ -rise - Set the rising edge transition. + Set the rising edge transition. @@ -11612,7 +11619,7 @@ -fall - Set the falling edge transition. + Set the falling edge transition. @@ -11620,7 +11627,7 @@ -max - Set the minimum transition time. + Set the minimum transition time. @@ -11628,7 +11635,7 @@ -min - Set the maximum transition time. + Set the maximum transition time. @@ -11654,10 +11661,10 @@ - set_level_shifter_strategy + set_level_shifter_strategy - [-rule rule_type] + [-rule rule_type] @@ -11668,10 +11675,10 @@ - set_level_shifter_threshold + set_level_shifter_threshold - [-voltage voltage] + [-voltage voltage] @@ -11681,10 +11688,10 @@ - set_load + set_load - [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects + [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11692,7 +11699,7 @@ -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). @@ -11700,7 +11707,7 @@ -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). @@ -11708,7 +11715,7 @@ -max - Set the max capacitance. + Set the max capacitance. @@ -11716,7 +11723,7 @@ -min - Set the min capacitance. + Set the min capacitance. @@ -11724,7 +11731,7 @@ -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. @@ -11760,24 +11767,24 @@ - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. @@ -11790,57 +11797,57 @@ - set_logic_one + set_logic_one - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - set_logic_zero + set_logic_zero - port_list + port_list - port_pin_list + port_pin_list List of ports or pins. - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area - area + area - area + area @@ -11853,15 +11860,15 @@ - set_max_capacitance + set_max_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance @@ -11870,7 +11877,7 @@ - objects + objects List of ports or cells. @@ -11883,10 +11890,10 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11894,7 +11901,7 @@ -rise - Set max delay for rising paths. + Set max delay for rising paths. @@ -11902,12 +11909,12 @@ -fall - Set max delay for falling paths. + Set max delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11915,7 +11922,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11923,7 +11930,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11939,10 +11946,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -11969,10 +11976,10 @@ - set_max_dynamic_power + set_max_dynamic_power - power [unit] + power [unit] @@ -11982,15 +11989,15 @@ - set_max_fanout + set_max_fanout - fanoutobjects + fanoutobjects - fanout + fanout @@ -11998,7 +12005,7 @@ - objects + objects List of ports or cells. @@ -12011,10 +12018,10 @@ - set_max_leakage_power + set_max_leakage_power - power [unit] + power [unit] @@ -12024,15 +12031,15 @@ - set_max_time_borrow + set_max_time_borrow - delayobjects + delayobjects - delay + delay The maximum time the latches can borrow. @@ -12040,76 +12047,76 @@ - objects + objects List of clocks, instances or pins. - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition - [-data_path][-clock_path][-rise][-fall]transitionobjects + [-data_path][-clock_path][-rise][-fall]transitionobjects - -data_path + -data_path - Set the max slew for data paths. + Set the max slew for data paths. - -clock_path + -clock_path - Set the max slew for clock paths. + Set the max slew for clock paths. - -rise + -rise - Set the max slew for rising paths. + Set the max slew for rising paths. - -fall + -fall - Set the max slew for falling paths. + Set the max slew for falling paths. - transition + transition - The maximum slew/transition time. + The maximum slew/transition time. - objects + objects List of clocks, ports or designs. - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -12117,23 +12124,23 @@ - set_min_capacitance + set_min_capacitance - capacitanceobjects + capacitanceobjects - capacitance + capacitance - Minimum capacitance. + Minimum capacitance. - objects + objects List of ports or cells. @@ -12146,10 +12153,10 @@ - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -12157,7 +12164,7 @@ -rise - Set min delay for rising paths. + Set min delay for rising paths. @@ -12166,12 +12173,12 @@ -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12179,7 +12186,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12187,7 +12194,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12203,10 +12210,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -12222,7 +12229,7 @@ delay - The minimum delay. + The minimum delay. @@ -12233,10 +12240,10 @@ - set_min_pulse_width + set_min_pulse_width - [-high][-low]min_widthobjects + [-high][-low]min_widthobjects @@ -12257,7 +12264,7 @@ - min_width + min_width @@ -12265,7 +12272,7 @@ - objects + objects List of pins, instances or clocks. @@ -12278,24 +12285,24 @@ - set_mode + set_mode - mode_name + mode_name - The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. + The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. - set_multicycle_path + set_multicycle_path - [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier + [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -12303,7 +12310,7 @@ -setup - Set cycle count for setup checks. + Set cycle count for setup checks. @@ -12311,7 +12318,7 @@ -hold - Set cycle count for hold checks. + Set cycle count for hold checks. @@ -12319,7 +12326,7 @@ -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. @@ -12327,7 +12334,7 @@ -fall - Set cycle count for falling path edges. + Set cycle count for falling path edges. @@ -12348,7 +12355,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12356,7 +12363,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12364,7 +12371,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12394,15 +12401,15 @@ - set_operating_conditions + set_operating_conditions - [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] + [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] - -analysis_type single + -analysis_type single Use one operating condition for min and max paths. @@ -12410,7 +12417,7 @@ - -analysis_type bc_wc + -analysis_type bc_wc Best case, worst case analysis. Setup checks use max_condition for clock and data paths. Hold checks use the min_condition for clock and data paths. @@ -12418,7 +12425,7 @@ - ‑analysis_type on_chip_variation + ‑analysis_type on_chip_variation The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. @@ -12426,7 +12433,7 @@ - -library lib + -library lib The name of the library that contains condition. @@ -12442,7 +12449,7 @@ - -min min_condition + -min min_condition The operating condition to use for min paths and hold checks. @@ -12450,7 +12457,7 @@ - -max max_condition + -max max_condition The operating condition to use for max paths and setup checks. @@ -12458,18 +12465,18 @@ - -min_library min_lib + -min_library min_lib - The name of the library that contains min_condition. + The name of the library that contains min_condition. - -max_library max_lib + -max_library max_lib - The name of the library that contains max_condition. + The name of the library that contains max_condition. @@ -12479,10 +12486,10 @@ - set_output_delay + set_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -12491,7 +12498,7 @@ -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. @@ -12499,7 +12506,7 @@ -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. @@ -12507,7 +12514,7 @@ -max - Set the maximum output delay. + Set the maximum output delay. @@ -12515,15 +12522,15 @@ -min - Set the minimum output delay. + Set the minimum output delay. - -clock clock + -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. @@ -12531,15 +12538,15 @@ -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. @@ -12547,7 +12554,7 @@ -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. @@ -12555,7 +12562,7 @@ delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. @@ -12567,33 +12574,33 @@ - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports - -min + -min - Set the min fanout. + Set the min fanout. - -max + -max - Set the max fanout. + Set the max fanout. @@ -12613,21 +12620,21 @@ - Set the external fanout for ports. + Set the external fanout for ports. - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global Set the activity/duty for all non-clock pins. @@ -12643,7 +12650,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -12651,7 +12658,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -12659,46 +12666,46 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -density density + -density density - Transitions per library time unit. + Transitions per library time unit. - -duty duty + -duty duty - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -clock clock + -clock clock - The clock to use for the period with -activity. This option is ignored if -density is used. + The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock objects @@ -12720,11 +12727,11 @@ - set_pvt + set_pvt - [-min][-max][-process process][-voltage voltage] - [-temperature temperature]instances + [-min][-max][-process process][-voltage voltage] + [-temperature temperature]instances @@ -12732,7 +12739,7 @@ -min - Set the PVT values for max delays. + Set the PVT values for max delays. @@ -12740,12 +12747,12 @@ -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process A process value (float). @@ -12753,7 +12760,7 @@ - -voltage voltage + -voltage voltage A voltage value (float). @@ -12761,7 +12768,7 @@ - -temperature temperature + -temperature temperature A temperature value (float). @@ -12782,59 +12789,59 @@ - set_sense + set_sense - [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins + [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins - -type clock + -type clock - Set the sense for clock paths. + Set the sense for clock paths. - -type data + -type data - Set the sense for data paths (not supported). + Set the sense for data paths (not supported). - -positive + -positive - The clock sense is positive unate. + The clock sense is positive unate. - -negative + -negative - The clock sense is negative unate. + The clock sense is negative unate. - -pulse pulse_type + -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. - -stop_propagation + -stop_propagation - Stop propagating clocks at pins. + Stop propagating clocks at pins. @@ -12842,7 +12849,7 @@ clocks - A list of clocks to apply the sense. + A list of clocks to apply the sense. @@ -12854,37 +12861,37 @@ - The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. + The set_sense command is used to modify the propagation of a clock signal. The clock sense is set with the ‑positive and –negative flags. Use the –stop_propagation flag to stop the clock from propagating beyond a pin. The –positive, -negative, -stop_propagation, and –pulse options are mutually exclusive. If the –clock option is not used the command applies to all clocks that traverse pins. The –pulse option is currently not supported. - set_timing_derate + set_timing_derate - [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] + [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] - -rise + -rise - Set the derating for rising delays. + Set the derating for rising delays. - -fall + -fall - Set the derating for falling delays. + Set the derating for falling delays. - -early + -early Derate early (min) paths. @@ -12892,7 +12899,7 @@ - -late + -late Derate late (max) paths. @@ -12900,7 +12907,7 @@ - -clock + -clock Derate paths in the clock network. @@ -12908,7 +12915,7 @@ - -data + -data Derate data paths. @@ -12916,7 +12923,7 @@ - -net_delay + -net_delay Derate net (interconnect) delays. @@ -12925,7 +12932,7 @@ - -cell_delay + -cell_delay Derate cell delays. @@ -12933,7 +12940,7 @@ - -cell_check + -cell_check Derate cell timing check margins. @@ -12944,7 +12951,7 @@ derate - The derating factor to apply to delays. + The derating factor to apply to delays. @@ -12963,15 +12970,15 @@ - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets - -min + -min The resistance for minimum path delay calculation. @@ -12979,7 +12986,7 @@ - -max + -max The resistance for maximum path delay calculation. @@ -12995,7 +13002,7 @@ - nets + nets A list of nets. @@ -13008,73 +13015,73 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. - M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 + M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm + set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -13087,10 +13094,10 @@ - set_wire_load_mode + set_wire_load_mode - top|enclosed|segmented + top|enclosed|segmented @@ -13124,16 +13131,16 @@ - set_wire_load_model + set_wire_load_model - -name model_name[-library library][-max][-min][objects] + -name model_name[-library library][-max][-min][objects] - -name model_name + -name model_name The name of a wire load model. @@ -13141,7 +13148,7 @@ - -library library + -library library Library to look for model_name. @@ -13178,10 +13185,10 @@ - set_wire_load_selection_group + set_wire_load_selection_group - [-library library][-max][-min]group_name[objects] + [-library library][-max][-min]group_name[objects] @@ -13189,7 +13196,7 @@ library - Library to look for group_name. + Library to look for group_name. @@ -13213,7 +13220,7 @@ group_name - A wire load selection group name. + A wire load selection group name. @@ -13231,28 +13238,28 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -13273,18 +13280,18 @@ - unset_clock_latency + unset_clock_latency - [-source]objects + [-source]objects - -source + -source - Specifies source clock latency (clock insertion delay). + Specifies source clock latency (clock insertion delay). @@ -13302,7 +13309,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -13323,15 +13330,15 @@ - unset_clock_uncertainty + unset_clock_uncertainty - [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] + [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] - -from from_clock + -from from_clock @@ -13339,7 +13346,7 @@ - -to to_clock + -to to_clock @@ -13366,7 +13373,7 @@ -setup - uncertainty is the setup check uncertainty. + uncertainty is the setup check uncertainty. @@ -13374,12 +13381,12 @@ -hold - uncertainty is the hold uncertainty. + uncertainty is the hold uncertainty. - uncertainty + uncertainty Clock uncertainty. @@ -13400,15 +13407,15 @@ - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] - -from from_object + -from from_object A pin used as the timing check reference. @@ -13416,7 +13423,7 @@ - -to to_object + -to to_object A pin that the setup/hold check is applied to. @@ -13440,7 +13447,7 @@ - clock + clock The setup/hold check clock. @@ -13453,7 +13460,7 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13468,16 +13475,16 @@ - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing - [-from from_port][-to to_port]objects + [-from from_port][-to to_port]objects @@ -13485,7 +13492,7 @@ from_port - + @@ -13493,7 +13500,7 @@ to_port - + @@ -13512,10 +13519,10 @@ - unset_input_delay + unset_input_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13523,7 +13530,7 @@ -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. @@ -13531,7 +13538,7 @@ -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. @@ -13539,7 +13546,7 @@ -max - Unset the minimum arrival time. + Unset the minimum arrival time. @@ -13547,7 +13554,7 @@ -min - Unset the maximum arrival time. + Unset the maximum arrival time. @@ -13555,7 +13562,7 @@ clock - Unset the arrival time from clock. + Unset the arrival time from clock. @@ -13563,7 +13570,7 @@ -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock @@ -13581,10 +13588,10 @@ - unset_output_delay + unset_output_delay - [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list + [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13633,7 +13640,7 @@ -clock_fall - The arrival time is from the falling edge of clock + The arrival time is from the falling edge of clock @@ -13651,10 +13658,10 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13662,7 +13669,7 @@ -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. @@ -13670,7 +13677,7 @@ -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. @@ -13678,7 +13685,7 @@ -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. @@ -13686,12 +13693,12 @@ -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13699,7 +13706,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13707,7 +13714,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13715,67 +13722,67 @@ The unset_path_exceptions command removes any matching set_false_path, set_multicycle_path, set_max_delay, and set_min_delay exceptions. - + - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global - Set the activity/duty for all non-clock pins. + Set the activity/duty for all non-clock pins. - -input + -input - Set the default input port activity/duty. + Set the default input port activity/duty. - -input_ports input_ports + -input_ports input_ports - Set the input port activity/duty. + Set the input port activity/duty. - -pins pins + -pins pins - Set the pin activity/duty. + Set the pin activity/duty. - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - The unset_power_activity_command is used to undo the effects of the set_power_activity command. + The unset_power_activity_command is used to undo the effects of the set_power_activity command. - unset_propagated_clock + unset_propagated_clock objects @@ -13796,41 +13803,41 @@ - unset_timing_derate + unset_timing_derate - Remove all derating factors set with the set_timing_derate command. + Remove all derating factors set with the set_timing_derate command. - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time @@ -13843,10 +13850,10 @@ - with_output_to_variable + with_output_to_variable - var { commands } + var { commands } @@ -13866,22 +13873,22 @@ - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. - write_path_spice + write_path_spice - -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_file spice_file-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] - path_args + path_args -from|-through|-to arguments as in report_checks. @@ -13889,15 +13896,15 @@ - spice_directory + spice_file - Directory for spice to write output files. + Directory and path prefix for spice output files. - lib_subckts_file + lib_subckts_file Cell transistor level subckts. @@ -13905,15 +13912,15 @@ - model_file + model_file - Transistor model definitions .included by spice_file. + Transistor model definitions .included by spice_file. - power + power Voltage supply name in voltage_map of the default liberty library. @@ -13921,7 +13928,7 @@ - ground + ground Ground supply name in voltage_map of the default liberty library. @@ -13929,28 +13936,28 @@ - -simulator + -simulator - Simulator that will read the spice netlist. + Simulator that will read the spice netlist. The write_path_spice command writes a spice netlist for timing paths. Use path_args to specify -from/-through/-to as arguments to the find_timing_paths command. For each path, a spice netlist and the subckts referenced by the path are written in spice_directory. The spice netlist is written in path_<id>.sp and subckt file is path_<id>.subckt. The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. - Example command: - write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS - When the simulator is hspice, .measure statements will be added to the spice netlist. - When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. + Example command: + write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS + When the simulator is hspice, .measure statements will be added to the spice netlist. + When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. - write_sdc + write_sdc - [-digits digits][-gzip][-no_timestamp]filename + [-digits digits][-gzip][-no_timestamp]filename @@ -13993,15 +14000,15 @@ - write_sdf + write_sdf - [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename + [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename - scene + scene Write delays for scene. @@ -14025,7 +14032,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default is 4. @@ -14064,75 +14071,75 @@ - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-scene scene]filename + [-library_name lib_name][-cell_name cell_name] + [-scene scene]filename - lib_name + lib_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty library. Defaults to cell_name. - cell_name + cell_name - The name to use for the liberty cell. Defaults to the top level module name. + The name to use for the liberty cell. Defaults to the top level module name. - scene + scene - The scene to use for extracting the model. + The scene to use for extracting the model. - filename + filename - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths - Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. + Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. - write_verilog + write_verilog - [-include_pwr_gnd][-remove_cells lib_cells]filename + [-include_pwr_gnd][-remove_cells lib_cells]filename - -include_pwr_gnd + -include_pwr_gnd Include power and ground pins on instances. @@ -14140,7 +14147,7 @@ - -remove_cells lib_cells + -remove_cells lib_cells Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. @@ -14148,16 +14155,16 @@ - filename + filename Filename for the liberty library. - The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions - The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions + The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -14166,39 +14173,39 @@ property - Return objects with property value equal to 1. + Return objects with property value equal to 1. - property==value + property==value - Return objects with property value equal to value. + Return objects with property value equal to value. - property=~pattern + property=~pattern - Return objects with property value that matches pattern. + Return objects with property value that matches pattern. - property!=value + property!=value - Return objects with property value not equal to value. + Return objects with property value not equal to value. - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. @@ -14206,7 +14213,7 @@ expr1&&expr2 - Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. @@ -14214,21 +14221,21 @@ expr1||expr2 - Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. @@ -14238,10 +14245,10 @@ - sta_continue_on_error + sta_continue_on_error - 0|1 + 0|1 @@ -14251,24 +14258,24 @@ - sta_crpr_mode + sta_crpr_mode - same_pin|same_transition + same_pin|same_transition - When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled - 0|1 + 0|1 @@ -14278,10 +14285,10 @@ - sta_crpr_enabled + sta_crpr_enabled - 0|1 + 0|1 @@ -14291,10 +14298,10 @@ - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking - 0|1 + 0|1 @@ -14304,23 +14311,23 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled - 0|1 + 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock - 0|1 + 0|1 @@ -14330,10 +14337,10 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled - 0|1 + 0|1 @@ -14343,10 +14350,10 @@ - sta_pocv_mode + sta_pocv_mode - scalar|normal|skew_normal + scalar|normal|skew_normal @@ -14356,7 +14363,7 @@ - sta_pocv_quartile + sta_pocv_quartile quartile @@ -14369,14 +14376,14 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks - 0|1 + 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] After all clocks have been defined. The default value is 0. @@ -14384,36 +14391,36 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable - 0|1 + 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled - 0|1 + 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - sta_report_default_digits + sta_report_default_digits - integer + integer @@ -14423,10 +14430,10 @@ - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled - 0|1 + 0|1 @@ -14456,186 +14463,186 @@ - Alphabetical Index + Alphabetical Index - all_clocks7 - all_inputs7 - all_outputs8 - all_registers8 - check_setup9 - Command Line Arguments1 - Commands7 - connect_pin9 - create_generated_clock11 - create_voltage_area12 - current_design12 - current_instance13 - define_scene13 - delete_clock13 - delete_from_list13 - delete_generated_clock14 - delete_instance14 - delete_net14 - disconnect_pin14 - elapsed_run_time14 - Example Command Scripts1 - Filter Expressions84 - find_timing_paths15 - get_cells17 - get_clocks17 - get_fanin18 - get_fanout19 - get_full_name19 - get_lib_pins20 - get_libs21 - get_name22 - get_nets22 - get_pins23 - get_ports23 - get_property24 - get_scenes28 - get_timing_edges28 - group_path29 - hierarchy_separator85 - include30 - link_design30 - make_instance30 - make_net31 - Power Analysis3 - read_liberty31 - read_saif32 - read_sdc33 - read_sdf33 - read_spef34 - read_vcd35 - read_verilog35 - redirection5 - replace_activity_annotation36 - replace_cell35 - report_annotated_check36 - report_annotated_delay37 - report_check_types41 - report_checks38 - report_clock_latency42 - report_clock_min_period42 - report_clock_properties43 - report_clock_skew43 - report_dcalc43 - report_disabled_edges44 - report_edges44 - report_instance44 - report_lib_cell44 - report_net45 - report_parasitic_annotation45 - report_power45 - report_slews46 - report_tns46 - report_units46 - report_wns47 - report_worst_slack47 - set_assigned_check48 - set_assigned_delay49 - set_assigned_transition49 - set_case_analysis50 - set_clock_gating_check50 - set_clock_groups51 - set_clock_latency52 - set_clock_transition52 - set_clock_uncertainty53 - set_cmd_units54 - set_data_check55 - set_disable_inferred_clock_gating55 - set_disable_timing55 - set_drive56 - set_driving_cell57 - set_false_path58 - set_fanout_load59 - set_hierarchy_separator59 - set_ideal_latency59 - set_ideal_network59 - set_ideal_transition59 - set_input_delay59 - set_input_transition61 - set_level_shifter_strategy61 - set_level_shifter_threshold61 - set_load61 - set_logic_dc62 - set_logic_one62 - set_logic_zero63 - set_max_area63 - set_max_capacitance63 - set_max_delay63 - set_max_dynamic_power64 - set_max_fanout64 - set_max_leakage_power64 - set_max_time_borrow64 - set_max_transition65 - set_min_capacitance65 - set_min_delay66 - set_min_pulse_width67 - set_mode67 - set_multicycle_path67 - set_operating_conditions68 - set_output_delay69 - set_port_fanout_number70 - set_power_activity70 - set_propagated_clock71 - set_pvt71 - set_resistance73 - set_sense72 - set_timing_derate73 - set_units74 - set_wire_load_min_block_size75 - set_wire_load_mode75 - set_wire_load_model75 - set_wire_load_selection_group75 - SPEF34 - sta_cond_default_arcs_enabled85 - sta_continue_on_error85 - sta_crpr_enabled85 - sta_crpr_mode85 - sta_dynamic_loop_breaking85 - sta_gated_clock_checks_enabled85 - sta_input_port_default_clock86 - sta_internal_bidirect_instance_paths_enabled86 - sta_pocv_enabled86 - sta_preset_clear_arcs_enabled87 - sta_propagate_all_clocks86 - sta_propagate_gated_clock_enable86 - sta_recovery_removal_checks_enabled86 - sta_report_default_digits86 - suppress_msg76 - TCL Interpreter5 - Timing Analysis using SDF2 - Timing Analysis with Multiple Corners and Modes3 - Timing Analysis with Multiple Process Corners2 - unset_case_analysis76 - unset_clock_latency76 - unset_clock_transition76 - unset_clock_uncertainty77 - unset_data_check77 - unset_disable_inferred_clock_gating78 - unset_disable_timing78 - unset_input_delay78 - unset_output_delay79 - unset_path_exceptions79 - unset_power_activity80 - unset_propagated_clock80 - unset_timing_derate80 - unsuppress_msg81 - user_run_time81 - Variables85 - verilog netlist35 - with_output_to_variable81 - write_path_spice81 - write_sdc82 - write_sdf82 - write_timing_model83 - write_verilog84 + all_clocks7 + all_inputs7 + all_outputs8 + all_registers8 + check_setup9 + Command Line Arguments1 + Commands7 + connect_pin9 + create_generated_clock11 + create_voltage_area12 + current_design12 + current_instance13 + define_scene13 + delete_clock13 + delete_from_list13 + delete_generated_clock14 + delete_instance14 + delete_net14 + disconnect_pin14 + elapsed_run_time14 + Example Command Scripts1 + Filter Expressions84 + find_timing_paths15 + get_cells17 + get_clocks17 + get_fanin18 + get_fanout19 + get_full_name19 + get_lib_pins20 + get_libs21 + get_name22 + get_nets22 + get_pins23 + get_ports23 + get_property24 + get_scenes28 + get_timing_edges28 + group_path29 + hierarchy_separator85 + include30 + link_design30 + make_instance30 + make_net31 + Power Analysis3 + read_liberty31 + read_saif32 + read_sdc33 + read_sdf33 + read_spef34 + read_vcd35 + read_verilog35 + redirection5 + replace_activity_annotation36 + replace_cell35 + report_annotated_check36 + report_annotated_delay37 + report_check_types41 + report_checks38 + report_clock_latency42 + report_clock_min_period42 + report_clock_properties43 + report_clock_skew43 + report_dcalc43 + report_disabled_edges44 + report_edges44 + report_instance44 + report_lib_cell44 + report_net45 + report_parasitic_annotation45 + report_power45 + report_slews46 + report_tns46 + report_units46 + report_wns47 + report_worst_slack47 + set_assigned_check48 + set_assigned_delay49 + set_assigned_transition49 + set_case_analysis50 + set_clock_gating_check50 + set_clock_groups51 + set_clock_latency52 + set_clock_transition52 + set_clock_uncertainty53 + set_cmd_units54 + set_data_check55 + set_disable_inferred_clock_gating55 + set_disable_timing55 + set_drive56 + set_driving_cell57 + set_false_path58 + set_fanout_load59 + set_hierarchy_separator59 + set_ideal_latency59 + set_ideal_network59 + set_ideal_transition59 + set_input_delay59 + set_input_transition61 + set_level_shifter_strategy61 + set_level_shifter_threshold61 + set_load61 + set_logic_dc62 + set_logic_one62 + set_logic_zero63 + set_max_area63 + set_max_capacitance63 + set_max_delay63 + set_max_dynamic_power64 + set_max_fanout64 + set_max_leakage_power64 + set_max_time_borrow64 + set_max_transition65 + set_min_capacitance65 + set_min_delay66 + set_min_pulse_width67 + set_mode67 + set_multicycle_path67 + set_operating_conditions68 + set_output_delay69 + set_port_fanout_number70 + set_power_activity70 + set_propagated_clock71 + set_pvt71 + set_resistance73 + set_sense72 + set_timing_derate73 + set_units74 + set_wire_load_min_block_size75 + set_wire_load_mode75 + set_wire_load_model75 + set_wire_load_selection_group75 + SPEF34 + sta_cond_default_arcs_enabled85 + sta_continue_on_error85 + sta_crpr_enabled85 + sta_crpr_mode85 + sta_dynamic_loop_breaking85 + sta_gated_clock_checks_enabled85 + sta_input_port_default_clock86 + sta_internal_bidirect_instance_paths_enabled86 + sta_pocv_enabled86 + sta_preset_clear_arcs_enabled87 + sta_propagate_all_clocks86 + sta_propagate_gated_clock_enable86 + sta_recovery_removal_checks_enabled86 + sta_report_default_digits86 + suppress_msg76 + TCL Interpreter5 + Timing Analysis using SDF2 + Timing Analysis with Multiple Corners and Modes3 + Timing Analysis with Multiple Process Corners2 + unset_case_analysis76 + unset_clock_latency76 + unset_clock_transition76 + unset_clock_uncertainty77 + unset_data_check77 + unset_disable_inferred_clock_gating78 + unset_disable_timing78 + unset_input_delay78 + unset_output_delay79 + unset_path_exceptions79 + unset_power_activity80 + unset_propagated_clock80 + unset_timing_derate80 + unsuppress_msg81 + user_run_time81 + Variables85 + verilog netlist35 + with_output_to_variable81 + write_path_spice81 + write_sdc82 + write_sdf82 + write_timing_model83 + write_verilog84 - - Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. + + Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. 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zv!WvRMXkc0Fa0!lVW8(8ok9ILU$~No96U3^a*w#GR>otoJvX@lIS&eI&f}EAT?+*( z`%t2oeaI2cKHkJlk5W_WFLxKvJVTKec-0CE5I=F zC$7LS#lY64;|Eg2JNp2OZ2%UX5G;KguViKUGnlf5U5l!L%qv9Sae2Sd_rmYbVtVtv z-%NC_hxUcE6123%U5eGB`t{@2e17C!@+;?2yFybRm+1u?K7O$6c?OnRMzGWm(r7NRdDaXz zGU~?d+k0SgCUzfU6QkQ2mpX9#lvr5&aRrS$zj3PAW_>DyMqb{y&2bg0aDkt4^HVKm6hIfBxJ5{P>w<*H54S@u#1DxxdJi&;Iz~^MCx$zx;In zVh^u>zx(W8KKsKrKYaYnH`;c5OF#JP(|45o-+cSU58wa(%OAe@miyqluRr|%Lq7Z0 z51)Vc)1SZn>yLl_x4-|_e|+}&RcT_e-+uX>)F;k`?>~P3&G(!F|M1;6-+cSKk3W3) j`s)vW|K(3V|MK5I|M-^=gq)hh-+uVjufG4MA3ppqiRbD) diff --git a/spice/WriteSpice.tcl b/spice/WriteSpice.tcl index 7cbb9be2..a4452662 100644 --- a/spice/WriteSpice.tcl +++ b/spice/WriteSpice.tcl @@ -25,7 +25,7 @@ namespace eval sta { define_cmd_args "write_path_spice" { -path_args path_args\ - -spice_directory spice_directory\ + -spice_file spice_file\ -lib_subckt_file lib_subckts_file\ -model_file model_file\ -power power\ @@ -34,12 +34,13 @@ define_cmd_args "write_path_spice" { -path_args path_args\ proc write_path_spice { args } { parse_key_args "write_path_spice" args \ - keys {-spice_directory -lib_subckt_file -model_file \ + keys {-spice_file -lib_subckt_file -model_file \ -power -ground -path_args -simulator} \ flags {} - if { [info exists keys(-spice_directory)] } { - set spice_dir [file nativename $keys(-spice_directory)] + if { [info exists keys(-spice_file)] } { + set spice_file [file nativename $keys(-spice_file)] + set spice_dir [file dirname $spice_file] if { ![file exists $spice_dir] } { sta_error 1920 "Directory $spice_dir not found." } @@ -50,7 +51,7 @@ proc write_path_spice { args } { sta_error 1922 "Cannot write in $spice_dir." } } else { - sta_error 1923 "No -spice_directory specified." + sta_error 1923 "No -spice_file specified." } if { [info exists keys(-lib_subckt_file)] } { @@ -96,10 +97,10 @@ proc write_path_spice { args } { set path_index 1 foreach path_end $path_ends { set path [$path_end path] - set path_name "path_$path_index" - set spice_file [file join $spice_dir "$path_name.sp"] - set subckt_file [file join $spice_dir "$path_name.subckt"] - write_path_spice_cmd $path $spice_file $subckt_file \ + set path_file "${spice_file}_$path_index" + set spice_file1 ${path_file}.sp + set subckt_file ${path_file}.subckt + write_path_spice_cmd $path $spice_file1 $subckt_file \ $lib_subckt_file $model_file $power $ground $ckt_sim incr path_index } From 7b0281014e6f9dc8dcbf295b0564e39b34f9c9b0 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sun, 22 Mar 2026 10:13:57 -0700 Subject: [PATCH 03/22] regression usage Signed-off-by: James Cherry --- test/regression.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/regression.tcl b/test/regression.tcl index 8137fcc8..dcf0057b 100755 --- a/test/regression.tcl +++ b/test/regression.tcl @@ -30,7 +30,7 @@ # # This notice may not be removed or altered from any source distribution. -# Usage: regression -help | [-threads threads] [-j jobs] [-valgrind] [-report_stats] +# Usage: regression -help | [-j jobs] [-threads threads] [-valgrind] [-report_stats] # test1 [test2...] proc regression_main {} { @@ -82,8 +82,8 @@ proc parse_args {} { set arg [lindex $argv 0] if { $arg == "help" || $arg == "-help" } { puts {Usage: regression [-help] [-threads threads] [-j jobs] [-valgrind] [-report_stats] tests...} - puts " -threads max|integer - number of threads to use" - puts " -j jobs - number of parallel jobs (processes) to run" + puts " -j jobs - number of parallel test jobs (processes) to run" + puts " -threads max|integer - number of threads the STA uses" puts " -valgrind - run valgrind (linux memory checker)" puts " -report_stats - report run time and memory" puts " Wildcarding for test names is supported (enclose in \"'s)" From ed19ed80dffb5c03372cffd5f9a02a93a9084fcc Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sun, 22 Mar 2026 19:34:51 -0700 Subject: [PATCH 04/22] power fmt Signed-off-by: James Cherry --- power/Power.cc | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/power/Power.cc b/power/Power.cc index d4dd239c..cd5312b0 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -1427,8 +1427,12 @@ Power::findSwitchingPower(const Instance *inst, float volt = portVoltage(scene_cell, to_port, scene, MinMax::max()); float switching = .5 * load_cap * volt * volt * activity.density(); debugPrint(debug_, "power", 2, - "switching {}/{} activity = {:.2e} volt = {:.2f} {:.3e}", cell->name(), - to_port->name(), activity.density(), volt, switching); + "switching {}/{} activity = {:.2e} volt = {:.2f} {:.3e}", + cell->name(), + to_port->name(), + activity.density(), + volt, + switching); result.incrSwitching(switching); } } @@ -1477,14 +1481,18 @@ Power::findLeakagePower(const Instance *inst, for (const LeakagePower &pwr : scene_cell->leakagePowers()) { LibertyPort *pg_port = pwr.relatedPgPort(); if (pg_port == nullptr || pg_port->pwrGndType() == PwrGndType::primary_power) { + std::string pg_name = pg_port ? pg_port->name() : "?"; LeakageSummary &sum = leakage_summaries[pg_port]; float leakage = pwr.power(); FuncExpr *when = pwr.when(); if (when) { LogicValue when_value = sim->evalExpr(when, inst); if (when_value == LogicValue::one) { - debugPrint(debug_, "power", 2, "leakage {}/{} {}=1 {:.3e}", cell->name(), - pg_port->name(), when->to_string(), leakage); + debugPrint(debug_, "power", 2, "leakage {}/{} {}=1 {:.3e}", + cell->name(), + pg_name, + when->to_string(), + leakage); sum.cond_true_leakage = leakage; sum.cond_true_exists = true; } @@ -1492,7 +1500,9 @@ Power::findLeakagePower(const Instance *inst, PwrActivity cond_activity = evalActivity(when, inst); float cond_duty = cond_activity.duty(); debugPrint(debug_, "power", 2, "leakage {} {} {} {:.3e} * {:.2f}", - cell->name(), pg_port->name(), when->to_string(), + cell->name(), + pg_name, + when->to_string(), leakage, cond_duty); // Leakage power average weighted by duty. sum.cond_leakage += leakage * cond_duty; @@ -1502,8 +1512,10 @@ Power::findLeakagePower(const Instance *inst, } } else { - debugPrint(debug_, "power", 2, "leakage {} {} -- {:.3e}", cell->name(), - pg_port->name(), leakage); + debugPrint(debug_, "power", 2, "leakage {} {} -- {:.3e}", + cell->name(), + pg_name, + leakage); sum.uncond_leakage = leakage; sum.uncond_exists = true; } @@ -1529,8 +1541,10 @@ Power::findLeakagePower(const Instance *inst, // Ignore unconditional leakage unless there are no conditional leakage groups. else if (sum.uncond_exists) leakage = sum.uncond_leakage; - debugPrint(debug_, "power", 2, "leakage {}/{} {:.3e}", cell->name(), - pg_port->name(), leakage); + debugPrint(debug_, "power", 2, "leakage {}/{} {:.3e}", + cell->name(), + pg_port ? pg_port->name() : "?", + leakage); result.incrLeakage(leakage); } } From 04f4528c2c8b1080338549ab68012c3b80ad6408 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sun, 22 Mar 2026 19:34:59 -0700 Subject: [PATCH 05/22] ccs ceff pocv Signed-off-by: James Cherry --- dcalc/CcsCeffDelayCalc.cc | 64 +++++++++++++++++++-------------------- dcalc/CcsCeffDelayCalc.hh | 9 +----- 2 files changed, 33 insertions(+), 40 deletions(-) diff --git a/dcalc/CcsCeffDelayCalc.cc b/dcalc/CcsCeffDelayCalc.cc index 0228df30..3c4e82b4 100644 --- a/dcalc/CcsCeffDelayCalc.cc +++ b/dcalc/CcsCeffDelayCalc.cc @@ -87,7 +87,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, parasitic_ = parasitic; output_waveforms_ = nullptr; - GateTableModel *table_model = arc->gateTableModel(scene, min_max); + const GateTableModel *table_model = arc->gateTableModel(scene, min_max); if (table_model && parasitic) { OutputWaveforms *output_waveforms = table_model->outputWaveforms(); Parasitics *parasitics = scene->parasitics(min_max); @@ -112,12 +112,36 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, drvr_cell->ensureVoltageWaveforms(scenes_); output_waveforms_ = output_waveforms; ref_time_ = output_waveforms_->referenceTime(in_slew_); - debugPrint(debug_, "ccs_dcalc", 1, "{} {}", drvr_cell->name(), + debugPrint(debug_, "ccs_dcalc", 1, "{} {}", + drvr_cell->name(), drvr_rf_->shortName()); + double gate_delay, drvr_slew; - gateDelaySlew(drvr_library, drvr_rf_, gate_delay, drvr_slew); - return makeResult(drvr_library, drvr_rf_, gate_delay, drvr_slew, - load_pin_index_map); + gateDelaySlew(drvr_library, gate_delay, drvr_slew); + debugPrint(debug_, "ccs_dcalc", 2, "gate_delay {} drvr_slew {}", + delayAsString(gate_delay, this), delayAsString(drvr_slew, this)); + + // Fill in pocv parameters. + ArcDelay gate_delay2(gate_delay); + Slew drvr_slew2(drvr_slew); + if (variables_->pocvEnabled()) { + double ceff = region_ceff_[0]; + const Pvt *pvt = pinPvt(drvr_pin_, scene, min_max); + table_model->gateDelayPocv(pvt, in_slew_, ceff, min_max, + variables_->pocvMode(), + gate_delay2, drvr_slew2); + } + ArcDcalcResult dcalc_result(load_pin_index_map.size()); + dcalc_result.setGateDelay(gate_delay2); + dcalc_result.setDrvrSlew(drvr_slew2); + + for (const auto &[load_pin, load_idx] : load_pin_index_map) { + double wire_delay, load_slew; + loadDelaySlew(load_pin, drvr_library, drvr_slew, wire_delay, load_slew); + dcalc_result.setWireDelay(load_idx, wire_delay); + dcalc_result.setLoadSlew(load_idx, load_slew); + } + return dcalc_result; } } return table_dcalc_->gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic, @@ -126,12 +150,11 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, void CcsCeffDelayCalc::gateDelaySlew(const LibertyLibrary *drvr_library, - const RiseFall *rf, // Return values. double &gate_delay, double &drvr_slew) { - initRegions(drvr_library, rf); + initRegions(drvr_library, drvr_rf_); findCsmWaveform(); ref_time_ = output_waveforms_->referenceTime(in_slew_); gate_delay = region_times_[region_vth_idx_] - ref_time_; @@ -300,33 +323,10 @@ CcsCeffDelayCalc::findCsmWaveform() //////////////////////////////////////////////////////////////// -ArcDcalcResult -CcsCeffDelayCalc::makeResult(const LibertyLibrary *drvr_library, - const RiseFall *rf, - double &gate_delay, - double &drvr_slew, - const LoadPinIndexMap &load_pin_index_map) -{ - ArcDcalcResult dcalc_result(load_pin_index_map.size()); - debugPrint(debug_, "ccs_dcalc", 2, "gate_delay {} drvr_slew {}", - delayAsString(gate_delay, this), delayAsString(drvr_slew, this)); - dcalc_result.setGateDelay(gate_delay); - dcalc_result.setDrvrSlew(drvr_slew); - - for (const auto &[load_pin, load_idx] : load_pin_index_map) { - double wire_delay, load_slew; - loadDelaySlew(load_pin, drvr_library, rf, drvr_slew, wire_delay, load_slew); - dcalc_result.setWireDelay(load_idx, wire_delay); - dcalc_result.setLoadSlew(load_idx, load_slew); - } - return dcalc_result; -} - void CcsCeffDelayCalc::loadDelaySlew(const Pin *load_pin, const LibertyLibrary *drvr_library, - const RiseFall *rf, - double &drvr_slew, + double drvr_slew, // Return values. double &wire_delay, double &load_slew) @@ -349,7 +349,7 @@ CcsCeffDelayCalc::loadDelaySlew(const Pin *load_pin, else loadDelaySlew(load_pin, drvr_slew, elmore, wire_delay, load_slew); - thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew); + thresholdAdjust(load_pin, drvr_library, drvr_rf_, wire_delay, load_slew); } void diff --git a/dcalc/CcsCeffDelayCalc.hh b/dcalc/CcsCeffDelayCalc.hh index 53a103bb..46125a94 100644 --- a/dcalc/CcsCeffDelayCalc.hh +++ b/dcalc/CcsCeffDelayCalc.hh @@ -71,22 +71,15 @@ protected: typedef std::vector Region; void gateDelaySlew(const LibertyLibrary *drvr_library, - const RiseFall *rf, // Return values. double &gate_delay, double &drvr_slew); void initRegions(const LibertyLibrary *drvr_library, const RiseFall *rf); void findCsmWaveform(); - ArcDcalcResult makeResult(const LibertyLibrary *drvr_library, - const RiseFall *rf, - double &gate_delay, - double &drvr_slew, - const LoadPinIndexMap &load_pin_index_map); void loadDelaySlew(const Pin *load_pin, const LibertyLibrary *drvr_library, - const RiseFall *rf, - double &drvr_slew, + double drvr_slew, // Return values. double &wire_delay, double &load_slew); From 59663ab640b4be96c95c2ff72bd5a97766f0cde2 Mon Sep 17 00:00:00 2001 From: Jaehyun Kim Date: Sat, 21 Mar 2026 18:46:31 +0900 Subject: [PATCH 06/22] update test files for upstream API refactoring Adapt all cpp/tcl test files to match upstream OpenSTA API changes: - string* output params changed to string return values (Verilog, Network) - Report methods renamed (reportLineString->reportLine, printf->std::format) - Delay type refactored from float typedef to class (Graph) - Liberty model APIs updated (value semantics, shared_ptr, PocvMode) - EXPECT_STREQ -> EXPECT_EQ for std::string returns (Sdc, Search) - streamPrint -> sta::print with std::format specifiers (Spice) - Avoid unset_clock_groups -all path (upstream iterator invalidation bug) Signed-off-by: Jaehyun Kim --- graph/test/cpp/TestGraph.cc | 153 +++++++------- liberty/test/cpp/TestLibertyClasses.cc | 83 ++++---- network/test/cpp/TestNetwork.cc | 6 +- sdc/test/cpp/TestSdcClasses.cc | 30 +-- sdc/test/sdc_clocks.tcl | 12 +- search/test/cpp/TestSearchClasses.cc | 8 +- spice/test/cpp/TestSpice.cc | 238 ++++++++++----------- util/test/cpp/TestUtil.cc | 279 +++++++++++-------------- verilog/test/cpp/TestVerilog.cc | 114 +++++----- 9 files changed, 448 insertions(+), 475 deletions(-) diff --git a/graph/test/cpp/TestGraph.cc b/graph/test/cpp/TestGraph.cc index 868018d6..58b1e2c1 100644 --- a/graph/test/cpp/TestGraph.cc +++ b/graph/test/cpp/TestGraph.cc @@ -1,5 +1,7 @@ #include -#include "DelayFloat.hh" +#include "Delay.hh" +#include "DelayScalar.hh" +#include "StaState.hh" #include "MinMax.hh" #include "Graph.hh" #include "Transition.hh" @@ -9,38 +11,55 @@ namespace sta { +// Minimal StaState subclass that provides a DelayOps for unit tests. +class TestStaState : public StaState +{ +public: + TestStaState() { delay_ops_ = new DelayOpsScalar(); } + ~TestStaState() override { delete delay_ops_; delay_ops_ = nullptr; } +}; + class DelayFloatTest : public ::testing::Test { protected: void SetUp() override { initDelayConstants(); + sta_state_ = new TestStaState(); } + void TearDown() override { + delete sta_state_; + sta_state_ = nullptr; + } + // Convenience accessor for delay comparison functions. + const StaState *sta() const { return sta_state_; } + + TestStaState *sta_state_; }; TEST_F(DelayFloatTest, DelayZero) { - EXPECT_TRUE(delayZero(0.0f)); - EXPECT_TRUE(delayZero(delay_zero)); - EXPECT_FALSE(delayZero(1.0f)); - EXPECT_FALSE(delayZero(-1.0f)); + EXPECT_TRUE(delayZero(Delay(0.0f), sta())); + EXPECT_TRUE(delayZero(delay_zero, sta())); + EXPECT_FALSE(delayZero(Delay(1.0f), sta())); + EXPECT_FALSE(delayZero(Delay(-1.0f), sta())); } TEST_F(DelayFloatTest, DelayEqual) { - EXPECT_TRUE(delayEqual(1.0f, 1.0f)); - EXPECT_TRUE(delayEqual(0.0f, 0.0f)); - EXPECT_FALSE(delayEqual(1.0f, 2.0f)); + EXPECT_TRUE(delayEqual(Delay(1.0f), Delay(1.0f), sta())); + EXPECT_TRUE(delayEqual(Delay(0.0f), Delay(0.0f), sta())); + EXPECT_FALSE(delayEqual(Delay(1.0f), Delay(2.0f), sta())); } TEST_F(DelayFloatTest, DelayInf) { // delayInf checks against STA's INF constant, not IEEE infinity - EXPECT_TRUE(delayInf(INF)); - EXPECT_TRUE(delayInf(-INF)); - EXPECT_FALSE(delayInf(0.0f)); - EXPECT_FALSE(delayInf(1e10f)); + EXPECT_TRUE(delayInf(Delay(INF), sta())); + EXPECT_TRUE(delayInf(Delay(-INF), sta())); + EXPECT_FALSE(delayInf(Delay(0.0f), sta())); + EXPECT_FALSE(delayInf(Delay(1e10f), sta())); } TEST_F(DelayFloatTest, DelayLess) { - EXPECT_TRUE(delayLess(1.0f, 2.0f, nullptr)); - EXPECT_FALSE(delayLess(2.0f, 1.0f, nullptr)); - EXPECT_FALSE(delayLess(1.0f, 1.0f, nullptr)); + EXPECT_TRUE(delayLess(Delay(1.0f), Delay(2.0f), sta())); + EXPECT_FALSE(delayLess(Delay(2.0f), Delay(1.0f), sta())); + EXPECT_FALSE(delayLess(Delay(1.0f), Delay(1.0f), sta())); } TEST_F(DelayFloatTest, DelayRemove) { @@ -50,11 +69,6 @@ TEST_F(DelayFloatTest, DelayRemove) { EXPECT_FLOAT_EQ(result, 2.0f); } -TEST_F(DelayFloatTest, DelayRatio) { - EXPECT_FLOAT_EQ(delayRatio(6.0f, 3.0f), 2.0f); - EXPECT_FLOAT_EQ(delayRatio(0.0f, 1.0f), 0.0f); -} - TEST_F(DelayFloatTest, DelayInitValueMin) { const Delay &init = delayInitValue(MinMax::min()); // Min init value should be a large positive number @@ -68,8 +82,8 @@ TEST_F(DelayFloatTest, DelayInitValueMax) { } TEST_F(DelayFloatTest, MakeDelay) { - Delay d = makeDelay(1.5f, 0.0f, 0.0f); - EXPECT_FLOAT_EQ(d, 1.5f); + Delay d = makeDelay(1.5f, 0.0f); + EXPECT_FLOAT_EQ(delayAsFloat(d), 1.5f); } TEST_F(DelayFloatTest, DelayAsFloat) { @@ -79,33 +93,33 @@ TEST_F(DelayFloatTest, DelayAsFloat) { // Additional delay tests for improved coverage TEST_F(DelayFloatTest, DelayGreater) { - EXPECT_TRUE(delayGreater(2.0f, 1.0f, nullptr)); - EXPECT_FALSE(delayGreater(1.0f, 2.0f, nullptr)); - EXPECT_FALSE(delayGreater(1.0f, 1.0f, nullptr)); + EXPECT_TRUE(delayGreater(Delay(2.0f), Delay(1.0f), sta())); + EXPECT_FALSE(delayGreater(Delay(1.0f), Delay(2.0f), sta())); + EXPECT_FALSE(delayGreater(Delay(1.0f), Delay(1.0f), sta())); } TEST_F(DelayFloatTest, DelayLessEqual) { - EXPECT_TRUE(delayLessEqual(1.0f, 2.0f, nullptr)); - EXPECT_TRUE(delayLessEqual(1.0f, 1.0f, nullptr)); - EXPECT_FALSE(delayLessEqual(2.0f, 1.0f, nullptr)); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(2.0f), sta())); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(1.0f), sta())); + EXPECT_FALSE(delayLessEqual(Delay(2.0f), Delay(1.0f), sta())); } TEST_F(DelayFloatTest, DelayGreaterEqual) { - EXPECT_TRUE(delayGreaterEqual(2.0f, 1.0f, nullptr)); - EXPECT_TRUE(delayGreaterEqual(1.0f, 1.0f, nullptr)); - EXPECT_FALSE(delayGreaterEqual(1.0f, 2.0f, nullptr)); + EXPECT_TRUE(delayGreaterEqual(Delay(2.0f), Delay(1.0f), sta())); + EXPECT_TRUE(delayGreaterEqual(Delay(1.0f), Delay(1.0f), sta())); + EXPECT_FALSE(delayGreaterEqual(Delay(1.0f), Delay(2.0f), sta())); } TEST_F(DelayFloatTest, MakeDelayWithSigma) { - // In float mode, sigma is ignored - Delay d = makeDelay(2.5f, 0.1f, 0.2f); - EXPECT_FLOAT_EQ(d, 2.5f); + // makeDelay(mean, std_dev) - sigma stored in Delay class + Delay d = makeDelay(2.5f, 0.1f); + EXPECT_FLOAT_EQ(delayAsFloat(d), 2.5f); } TEST_F(DelayFloatTest, DelayNegative) { Delay d = -5.0f; EXPECT_FLOAT_EQ(delayAsFloat(d), -5.0f); - EXPECT_FALSE(delayZero(d)); + EXPECT_FALSE(delayZero(d, sta())); } //////////////////////////////////////////////////////////////// @@ -274,11 +288,12 @@ TEST(VertexStandaloneTest, Paths) EXPECT_EQ(v.paths(), nullptr); } -// Test Vertex slews -TEST(VertexStandaloneTest, Slews) +// Test Vertex pin default +TEST(VertexStandaloneTest, PinDefault) { Vertex v; - EXPECT_EQ(v.slews(), nullptr); + // slews() is protected; verify public pin() accessor instead + EXPECT_EQ(v.pin(), nullptr); } //////////////////////////////////////////////////////////////// @@ -360,10 +375,10 @@ TEST(EdgeStandaloneTest, RemoveDelayAnnotated) TEST(EdgeStandaloneTest, SetArcDelays) { Edge e; - // Set and clear arc delays - ArcDelay *delays = new ArcDelay[4]; + // Set and clear arc delays (setArcDelays takes float*) + float *delays = new float[4]; for (int i = 0; i < 4; i++) - delays[i] = 0.0; + delays[i] = 0.0f; e.setArcDelays(delays); EXPECT_NE(e.arcDelays(), nullptr); e.setArcDelays(nullptr); @@ -385,14 +400,14 @@ TEST_F(DelayFloatTest, DelayLessEqualMinMax) { // 4-arg delayLessEqual with MinMax // With max: same as fuzzyLessEqual - EXPECT_TRUE(delayLessEqual(1.0f, 2.0f, MinMax::max(), nullptr)); - EXPECT_TRUE(delayLessEqual(1.0f, 1.0f, MinMax::max(), nullptr)); - EXPECT_FALSE(delayLessEqual(2.0f, 1.0f, MinMax::max(), nullptr)); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(2.0f), MinMax::max(), sta())); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(1.0f), MinMax::max(), sta())); + EXPECT_FALSE(delayLessEqual(Delay(2.0f), Delay(1.0f), MinMax::max(), sta())); // With min: same as fuzzyGreaterEqual (reversed) - EXPECT_TRUE(delayLessEqual(2.0f, 1.0f, MinMax::min(), nullptr)); - EXPECT_TRUE(delayLessEqual(1.0f, 1.0f, MinMax::min(), nullptr)); - EXPECT_FALSE(delayLessEqual(1.0f, 2.0f, MinMax::min(), nullptr)); + EXPECT_TRUE(delayLessEqual(Delay(2.0f), Delay(1.0f), MinMax::min(), sta())); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(1.0f), MinMax::min(), sta())); + EXPECT_FALSE(delayLessEqual(Delay(1.0f), Delay(2.0f), MinMax::min(), sta())); } //////////////////////////////////////////////////////////////// @@ -413,7 +428,8 @@ TEST(EdgeStandaloneTest, DefaultState) TEST(VertexStandaloneTest, SlewsDefault) { Vertex v; - EXPECT_EQ(v.slews(), nullptr); + // slews() is protected; verify public paths() accessor instead + EXPECT_EQ(v.paths(), nullptr); } // Test Edge::arcDelayAnnotateBit - static method @@ -440,22 +456,14 @@ TEST(EdgeStandaloneTest, EdgeInitViaTimingArcSet) EXPECT_EQ(e.timingArcSet(), nullptr); } -// Test Vertex setSlews -// Covers: Vertex::setSlews +// Test Vertex initial state via public accessors +// Covers: Vertex default state TEST(VertexStandaloneTest, SetSlews) { Vertex v; - EXPECT_EQ(v.slews(), nullptr); - - // Allocate some slews - Slew *slews = new Slew[4]; - for (int i = 0; i < 4; i++) - slews[i] = static_cast(i) * 1e-9f; - - // setSlews is protected, but we test via the public slews() accessor - // We can't directly call setSlews, but we verify initial state - EXPECT_EQ(v.slews(), nullptr); - delete[] slews; + // slews() and setSlews() are protected; verify public accessors instead + EXPECT_EQ(v.pin(), nullptr); + EXPECT_EQ(v.paths(), nullptr); } // Test Vertex setPaths @@ -541,14 +549,12 @@ TEST(EdgeStandaloneTest, SetTimingArcSetNull) EXPECT_EQ(e.timingArcSet(), nullptr); } -// Test Vertex setSlews indirectly - slews_ is protected -// Covers: Vertex::setSlews path +// Test Vertex public accessors for initial state +// Covers: Vertex::paths, Vertex::setPaths TEST(VertexStandaloneTest, VertexSlewsProtected) { Vertex v; - // Initially slews_ is nullptr - EXPECT_EQ(v.slews(), nullptr); - // setPaths is public - at least verify paths + // slews() is protected; verify public setPaths/paths instead v.setPaths(nullptr); EXPECT_EQ(v.paths(), nullptr); } @@ -673,7 +679,8 @@ TEST(EdgeStandaloneTest, ArcDelaysSetAndAccess) { Edge e; EXPECT_EQ(e.arcDelays(), nullptr); - ArcDelay *delays = new ArcDelay[8]; + // setArcDelays takes float* + float *delays = new float[8]; for (int i = 0; i < 8; i++) delays[i] = static_cast(i) * 1e-12f; e.setArcDelays(delays); @@ -773,14 +780,14 @@ TEST(EdgeStandaloneTest, MultipleFlagCombinations) TEST_F(DelayFloatTest, DelayLessEqualMinMaxVariant) { // With max: standard less-equal - EXPECT_TRUE(delayLessEqual(1.0f, 2.0f, MinMax::max(), nullptr)); - EXPECT_TRUE(delayLessEqual(2.0f, 2.0f, MinMax::max(), nullptr)); - EXPECT_FALSE(delayLessEqual(3.0f, 2.0f, MinMax::max(), nullptr)); + EXPECT_TRUE(delayLessEqual(Delay(1.0f), Delay(2.0f), MinMax::max(), sta())); + EXPECT_TRUE(delayLessEqual(Delay(2.0f), Delay(2.0f), MinMax::max(), sta())); + EXPECT_FALSE(delayLessEqual(Delay(3.0f), Delay(2.0f), MinMax::max(), sta())); // With min: reversed (greater-equal) - EXPECT_TRUE(delayLessEqual(3.0f, 2.0f, MinMax::min(), nullptr)); - EXPECT_TRUE(delayLessEqual(2.0f, 2.0f, MinMax::min(), nullptr)); - EXPECT_FALSE(delayLessEqual(1.0f, 2.0f, MinMax::min(), nullptr)); + EXPECT_TRUE(delayLessEqual(Delay(3.0f), Delay(2.0f), MinMax::min(), sta())); + EXPECT_TRUE(delayLessEqual(Delay(2.0f), Delay(2.0f), MinMax::min(), sta())); + EXPECT_FALSE(delayLessEqual(Delay(1.0f), Delay(2.0f), MinMax::min(), sta())); } //////////////////////////////////////////////////////////////// diff --git a/liberty/test/cpp/TestLibertyClasses.cc b/liberty/test/cpp/TestLibertyClasses.cc index 60470e17..5369c612 100644 --- a/liberty/test/cpp/TestLibertyClasses.cc +++ b/liberty/test/cpp/TestLibertyClasses.cc @@ -60,8 +60,8 @@ TEST_F(UnitTest, UserToSta) { TEST_F(UnitTest, AsString) { Unit unit(1e-9f, "s", 3); - const char *str = unit.asString(1e-9f); - EXPECT_NE(str, nullptr); + std::string str = unit.asString(1e-9f); + EXPECT_FALSE(str.empty()); // Should produce something like "1.000" } @@ -1268,8 +1268,8 @@ TEST(InternalPowerTest, DirectConstruction) { InternalPower pwr(nullptr, nullptr, nullptr, when_expr, models); EXPECT_EQ(pwr.when(), when_expr.get()); EXPECT_EQ(pwr.relatedPgPin(), nullptr); - EXPECT_EQ(pwr.model(RiseFall::rise()), nullptr); - EXPECT_EQ(pwr.model(RiseFall::fall()), nullptr); + EXPECT_EQ(pwr.model(RiseFall::rise()).model(), nullptr); + EXPECT_EQ(pwr.model(RiseFall::fall()).model(), nullptr); } //////////////////////////////////////////////////////////////// @@ -1450,26 +1450,27 @@ TEST_F(LinearModelTest, GateLinearModelConstruct) { TEST_F(LinearModelTest, GateLinearModelGateDelay) { GateLinearModel model(cell_, 1.0f, 2.0f); - ArcDelay gate_delay; - Slew drvr_slew; + float gate_delay; + float drvr_slew; // delay = intrinsic + resistance * load_cap = 1.0 + 2.0 * 3.0 = 7.0 - model.gateDelay(nullptr, 0.0f, 3.0f, false, gate_delay, drvr_slew); - EXPECT_FLOAT_EQ(delayAsFloat(gate_delay), 7.0f); - EXPECT_FLOAT_EQ(delayAsFloat(drvr_slew), 0.0f); + model.gateDelay(nullptr, 0.0f, 3.0f, gate_delay, drvr_slew); + EXPECT_FLOAT_EQ(gate_delay, 7.0f); + EXPECT_FLOAT_EQ(drvr_slew, 0.0f); } TEST_F(LinearModelTest, GateLinearModelZeroLoad) { GateLinearModel model(cell_, 2.5f, 1.0f); - ArcDelay gate_delay; - Slew drvr_slew; + float gate_delay; + float drvr_slew; // delay = 2.5 + 1.0 * 0.0 = 2.5 - model.gateDelay(nullptr, 0.0f, 0.0f, false, gate_delay, drvr_slew); - EXPECT_FLOAT_EQ(delayAsFloat(gate_delay), 2.5f); + model.gateDelay(nullptr, 0.0f, 0.0f, gate_delay, drvr_slew); + EXPECT_FLOAT_EQ(gate_delay, 2.5f); } TEST_F(LinearModelTest, GateLinearModelReportGateDelay) { GateLinearModel model(cell_, 1.0f, 2.0f); - std::string report = model.reportGateDelay(nullptr, 0.0f, 0.5f, false, 3); + std::string report = model.reportGateDelay(nullptr, 0.0f, 0.5f, + nullptr, PocvMode::scalar, 3); EXPECT_FALSE(report.empty()); // Report should contain "Delay =" EXPECT_NE(report.find("Delay"), std::string::npos); @@ -1477,23 +1478,27 @@ TEST_F(LinearModelTest, GateLinearModelReportGateDelay) { TEST_F(LinearModelTest, CheckLinearModelConstruct) { CheckLinearModel model(cell_, 3.0f); - ArcDelay delay = model.checkDelay(nullptr, 0.0f, 0.0f, 0.0f, false); + ArcDelay delay = model.checkDelay(nullptr, 0.0f, 0.0f, 0.0f, + nullptr, PocvMode::scalar); EXPECT_FLOAT_EQ(delayAsFloat(delay), 3.0f); } TEST_F(LinearModelTest, CheckLinearModelCheckDelay) { CheckLinearModel model(cell_, 5.5f); // checkDelay always returns intrinsic_ regardless of other params - ArcDelay delay1 = model.checkDelay(nullptr, 1.0f, 2.0f, 3.0f, true); + ArcDelay delay1 = model.checkDelay(nullptr, 1.0f, 2.0f, 3.0f, + nullptr, PocvMode::scalar); EXPECT_FLOAT_EQ(delayAsFloat(delay1), 5.5f); - ArcDelay delay2 = model.checkDelay(nullptr, 0.0f, 0.0f, 0.0f, false); + ArcDelay delay2 = model.checkDelay(nullptr, 0.0f, 0.0f, 0.0f, + nullptr, PocvMode::scalar); EXPECT_FLOAT_EQ(delayAsFloat(delay2), 5.5f); } TEST_F(LinearModelTest, CheckLinearModelReportCheckDelay) { CheckLinearModel model(cell_, 2.0f); std::string report = model.reportCheckDelay(nullptr, 0.0f, nullptr, - 0.0f, 0.0f, false, 3); + 0.0f, 0.0f, + nullptr, PocvMode::scalar, 3); EXPECT_FALSE(report.empty()); EXPECT_NE(report.find("Check"), std::string::npos); } @@ -1505,24 +1510,24 @@ TEST_F(LinearModelTest, CheckLinearModelReportCheckDelay) { TEST(InternalPowerTest, ModelAccess) { InternalPowerModels models{}; InternalPower pwr(nullptr, nullptr, nullptr, nullptr, models); - // Initially models should be nullptr - EXPECT_EQ(pwr.model(RiseFall::rise()), nullptr); - EXPECT_EQ(pwr.model(RiseFall::fall()), nullptr); + // Initially models should have null inner TableModel + EXPECT_EQ(pwr.model(RiseFall::rise()).model(), nullptr); + EXPECT_EQ(pwr.model(RiseFall::fall()).model(), nullptr); } TEST(InternalPowerTest, WithModel) { // Create a minimal model: Table -> TableModel -> InternalPowerModel TablePtr tbl = std::make_shared(1.0f); - TableModel *table_model = new TableModel(tbl, nullptr, - ScaleFactorType::internal_power, - RiseFall::rise()); - auto power_model = std::make_shared(table_model); + auto table_model = std::make_shared(tbl, nullptr, + ScaleFactorType::internal_power, + RiseFall::rise()); + InternalPowerModel power_model(table_model); InternalPowerModels models{}; models[RiseFall::riseIndex()] = power_model; InternalPower pwr(nullptr, nullptr, nullptr, nullptr, models); - EXPECT_EQ(pwr.model(RiseFall::rise()), power_model.get()); - EXPECT_EQ(pwr.model(RiseFall::fall()), nullptr); + EXPECT_NE(pwr.model(RiseFall::rise()).model(), nullptr); + EXPECT_EQ(pwr.model(RiseFall::fall()).model(), nullptr); } //////////////////////////////////////////////////////////////// @@ -3473,9 +3478,9 @@ TEST(LibertyUtilTest, PortLibertyToStaWithBrackets) { TEST(InternalPowerModelTest, PowerLookupOrder0) { TablePtr tbl = std::make_shared
(5.0f); - TableModel *table_model = new TableModel(tbl, nullptr, - ScaleFactorType::internal_power, - RiseFall::rise()); + auto table_model = std::make_shared(tbl, nullptr, + ScaleFactorType::internal_power, + RiseFall::rise()); InternalPowerModel model(table_model); LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "INV", "test.lib"); @@ -3485,9 +3490,9 @@ TEST(InternalPowerModelTest, PowerLookupOrder0) { TEST(InternalPowerModelTest, ReportPowerOrder0) { TablePtr tbl = std::make_shared
(3.0f); - TableModel *table_model = new TableModel(tbl, nullptr, - ScaleFactorType::internal_power, - RiseFall::rise()); + auto table_model = std::make_shared(tbl, nullptr, + ScaleFactorType::internal_power, + RiseFall::rise()); InternalPowerModel model(table_model); LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "INV", "test.lib"); @@ -3505,9 +3510,9 @@ TEST(InternalPowerModelTest, PowerLookupOrder1) { values.push_back(1.0f); values.push_back(3.0f); TablePtr tbl = std::make_shared
(std::move(values), axis); - TableModel *table_model = new TableModel(tbl, nullptr, - ScaleFactorType::internal_power, - RiseFall::rise()); + auto table_model = std::make_shared(tbl, nullptr, + ScaleFactorType::internal_power, + RiseFall::rise()); InternalPowerModel model(table_model); LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "INV", "test.lib"); @@ -3529,9 +3534,9 @@ TEST(InternalPowerModelTest, PowerLookupOrder2) { FloatSeq row1; row1.push_back(3.0f); row1.push_back(4.0f); values.push_back(std::move(row0)); values.push_back(std::move(row1)); TablePtr tbl = std::make_shared
(std::move(values), axis1, axis2); - TableModel *table_model = new TableModel(tbl, nullptr, - ScaleFactorType::internal_power, - RiseFall::rise()); + auto table_model = std::make_shared(tbl, nullptr, + ScaleFactorType::internal_power, + RiseFall::rise()); InternalPowerModel model(table_model); LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "INV", "test.lib"); diff --git a/network/test/cpp/TestNetwork.cc b/network/test/cpp/TestNetwork.cc index 7ccfbfdb..564d8f15 100644 --- a/network/test/cpp/TestNetwork.cc +++ b/network/test/cpp/TestNetwork.cc @@ -61,20 +61,20 @@ TEST_F(VerilogNamespaceTest, PortBusName) { // Test Verilog-to-STA conversion TEST_F(VerilogNamespaceTest, ModuleVerilogToSta) { std::string verilog_name = "top_module"; - std::string result = moduleVerilogToSta(&verilog_name); + std::string result = moduleVerilogToSta(verilog_name); EXPECT_EQ(result, "top_module"); } TEST_F(VerilogNamespaceTest, InstanceVerilogToSta) { std::string verilog_name = "u1"; - std::string result = instanceVerilogToSta(&verilog_name); + std::string result = instanceVerilogToSta(verilog_name); EXPECT_EQ(result, "u1"); } // Test escaped name round-trip TEST_F(VerilogNamespaceTest, EscapedNameRoundTrip) { std::string verilog_name = "\\esc_name "; - std::string sta = instanceVerilogToSta(&verilog_name); + std::string sta = instanceVerilogToSta(verilog_name); EXPECT_FALSE(sta.empty()); } diff --git a/sdc/test/cpp/TestSdcClasses.cc b/sdc/test/cpp/TestSdcClasses.cc index 7b8f1c6c..5060d4c1 100644 --- a/sdc/test/cpp/TestSdcClasses.cc +++ b/sdc/test/cpp/TestSdcClasses.cc @@ -886,7 +886,7 @@ TEST_F(VariablesTest, SetUseDefaultArrivalClock) { TEST_F(VariablesTest, SetPocvEnabled) { Variables vars; - vars.setPocvEnabled(true); + vars.setPocvMode(PocvMode::normal); EXPECT_TRUE(vars.pocvEnabled()); } @@ -2170,7 +2170,7 @@ TEST_F(SdcInitTest, GroupPathClone) { ExceptionPath *cloned = gp.clone(nullptr, nullptr, nullptr, true); EXPECT_NE(cloned, nullptr); EXPECT_TRUE(cloned->isGroupPath()); - EXPECT_STREQ(cloned->name(), "grp"); + EXPECT_EQ(cloned->name(), "grp"); delete cloned; } @@ -2184,22 +2184,22 @@ TEST_F(SdcInitTest, FilterPathClone) { TEST_F(SdcInitTest, FalsePathAsString) { FalsePath fp(nullptr, nullptr, nullptr, MinMaxAll::all(), true, nullptr); - const char *str = fp.asString(sta_->cmdNetwork()); - EXPECT_NE(str, nullptr); + std::string str = fp.to_string(sta_->cmdNetwork()); + EXPECT_FALSE(str.empty()); } TEST_F(SdcInitTest, PathDelayAsString) { PathDelay pd(nullptr, nullptr, nullptr, MinMax::max(), false, false, 1.0e-9f, true, nullptr); - const char *str = pd.asString(sta_->cmdNetwork()); - EXPECT_NE(str, nullptr); + std::string str = pd.to_string(sta_->cmdNetwork()); + EXPECT_FALSE(str.empty()); } TEST_F(SdcInitTest, MultiCyclePathAsString) { MultiCyclePath mcp(nullptr, nullptr, nullptr, MinMaxAll::all(), true, 2, true, nullptr); - const char *str = mcp.asString(sta_->cmdNetwork()); - EXPECT_NE(str, nullptr); + std::string str = mcp.to_string(sta_->cmdNetwork()); + EXPECT_FALSE(str.empty()); } // ExceptionPath type predicates @@ -2320,7 +2320,7 @@ TEST_F(SdcInitTest, ExceptionPathDefaultHandlers) { EXPECT_FALSE(fp.useEndClk()); EXPECT_EQ(fp.pathMultiplier(), 0); EXPECT_FLOAT_EQ(fp.delay(), 0.0f); - EXPECT_EQ(fp.name(), nullptr); + EXPECT_TRUE(fp.name().empty()); EXPECT_FALSE(fp.isDefault()); EXPECT_FALSE(fp.ignoreClkLatency()); EXPECT_FALSE(fp.breakPath()); @@ -2641,8 +2641,8 @@ TEST_F(SdcInitTest, ClockEdgeDetails) { EXPECT_EQ(fall->transition(), RiseFall::fall()); EXPECT_EQ(rise->opposite(), fall); EXPECT_EQ(fall->opposite(), rise); - EXPECT_NE(rise->name(), nullptr); - EXPECT_NE(fall->name(), nullptr); + EXPECT_FALSE(rise->name().empty()); + EXPECT_FALSE(fall->name().empty()); EXPECT_GE(rise->index(), 0); EXPECT_GE(fall->index(), 0); EXPECT_NE(rise->index(), fall->index()); @@ -2878,8 +2878,8 @@ TEST_F(SdcInitTest, SdcMakePathDelay) { TEST_F(SdcInitTest, SdcRemoveClockGroupsOther) { ASSERT_NO_THROW(( [&](){ Sdc *sdc = sta_->cmdSdc(); - sdc->removeClockGroupsPhysicallyExclusive(nullptr); - sdc->removeClockGroupsAsynchronous(nullptr); + sdc->removeClockGroupsPhysicallyExclusive(); + sdc->removeClockGroupsAsynchronous(); }() )); } @@ -3813,7 +3813,7 @@ TEST_F(SdcInitTest, VariablesSetUseDefaultArrivalClock) { TEST_F(SdcInitTest, VariablesSetPocvEnabled) { Variables vars; - vars.setPocvEnabled(true); + vars.setPocvMode(PocvMode::normal); EXPECT_TRUE(vars.pocvEnabled()); } @@ -4565,7 +4565,7 @@ TEST_F(SdcExceptionPathTest, GroupPathIsGroupPath) { GroupPath gp("grp", false, nullptr, nullptr, nullptr, true, nullptr); EXPECT_TRUE(gp.isGroupPath()); EXPECT_FALSE(gp.isFalse()); - EXPECT_STREQ(gp.name(), "grp"); + EXPECT_EQ(gp.name(), "grp"); EXPECT_FALSE(gp.isDefault()); EXPECT_EQ(gp.type(), ExceptionPathType::group_path); } diff --git a/sdc/test/sdc_clocks.tcl b/sdc/test/sdc_clocks.tcl index dee61577..b453dd3d 100644 --- a/sdc/test/sdc_clocks.tcl +++ b/sdc/test/sdc_clocks.tcl @@ -84,18 +84,18 @@ set_propagated_clock [get_clocks clk1] # set_clock_groups ############################################################ -set_clock_groups -logically_exclusive -group [get_clocks clk1] -group [get_clocks clk2] +set_clock_groups -name le_grp -logically_exclusive -group [get_clocks clk1] -group [get_clocks clk2] # Remove and re-add as physically exclusive -unset_clock_groups -logically_exclusive -all +unset_clock_groups -logically_exclusive -name le_grp -set_clock_groups -physically_exclusive -group [get_clocks clk1] -group [get_clocks clk2] +set_clock_groups -name pe_grp -physically_exclusive -group [get_clocks clk1] -group [get_clocks clk2] -unset_clock_groups -physically_exclusive -all +unset_clock_groups -physically_exclusive -name pe_grp -set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2] +set_clock_groups -name async_grp -asynchronous -group [get_clocks clk1] -group [get_clocks clk2] -unset_clock_groups -asynchronous -all +unset_clock_groups -asynchronous -name async_grp ############################################################ # set_clock_sense diff --git a/search/test/cpp/TestSearchClasses.cc b/search/test/cpp/TestSearchClasses.cc index 7356d665..8e1ccc19 100644 --- a/search/test/cpp/TestSearchClasses.cc +++ b/search/test/cpp/TestSearchClasses.cc @@ -1233,14 +1233,14 @@ TEST_F(ExceptionPathTest, GroupPathBasic) { EXPECT_FALSE(gp.isFalse()); EXPECT_FALSE(gp.isPathDelay()); EXPECT_EQ(gp.type(), ExceptionPathType::group_path); - EXPECT_STREQ(gp.name(), "group1"); + EXPECT_EQ(gp.name(), "group1"); EXPECT_FALSE(gp.isDefault()); } TEST_F(ExceptionPathTest, GroupPathDefault) { GroupPath gp("default_group", true, nullptr, nullptr, nullptr, true, nullptr); EXPECT_TRUE(gp.isDefault()); - EXPECT_STREQ(gp.name(), "default_group"); + EXPECT_EQ(gp.name(), "default_group"); } TEST_F(ExceptionPathTest, GroupPathTypePriority) { @@ -1258,7 +1258,7 @@ TEST_F(ExceptionPathTest, GroupPathClone) { GroupPath gp("gp_clone", true, nullptr, nullptr, nullptr, true, "comment"); ExceptionPath *clone = gp.clone(nullptr, nullptr, nullptr, true); EXPECT_TRUE(clone->isGroupPath()); - EXPECT_STREQ(clone->name(), "gp_clone"); + EXPECT_EQ(clone->name(), "gp_clone"); EXPECT_TRUE(clone->isDefault()); delete clone; } @@ -1377,7 +1377,7 @@ TEST_F(ExceptionPathTest, DefaultValues) { EXPECT_FALSE(fp.useEndClk()); EXPECT_EQ(fp.pathMultiplier(), 0); EXPECT_FLOAT_EQ(fp.delay(), 0.0f); - EXPECT_EQ(fp.name(), nullptr); + EXPECT_EQ(fp.name(), ""); EXPECT_FALSE(fp.isDefault()); EXPECT_FALSE(fp.ignoreClkLatency()); EXPECT_FALSE(fp.breakPath()); diff --git a/spice/test/cpp/TestSpice.cc b/spice/test/cpp/TestSpice.cc index 7899fda9..8ae8e85a 100644 --- a/spice/test/cpp/TestSpice.cc +++ b/spice/test/cpp/TestSpice.cc @@ -44,7 +44,7 @@ TEST_F(SpiceSmokeTest, TransitionNames) { EXPECT_EQ(Transition::fall()->to_string(), "v"); } -// Tests for streamPrint (free function in WriteSpice.cc) +// Tests for print (Format.hh - formerly print) class StreamPrintTest : public ::testing::Test { protected: void SetUp() override { @@ -63,7 +63,7 @@ protected: TEST_F(StreamPrintTest, BasicString) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "hello world\n"); + sta::print(out, "hello world\n"); out.close(); std::ifstream in(tmpfile_); @@ -75,7 +75,7 @@ TEST_F(StreamPrintTest, BasicString) { TEST_F(StreamPrintTest, FormattedOutput) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v%d %s 0 %.3f\n", 1, "node1", 1.800); + sta::print(out, "v{} {} 0 {:.3f}\n", 1, "node1", 1.800); out.close(); std::ifstream in(tmpfile_); @@ -87,7 +87,7 @@ TEST_F(StreamPrintTest, FormattedOutput) { TEST_F(StreamPrintTest, ScientificNotation) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "C%d %s 0 %.3e\n", 1, "net1", 1.5e-12); + sta::print(out, "C{} {} 0 {:.3e}\n", 1, "net1", 1.5e-12); out.close(); std::ifstream in(tmpfile_); @@ -99,9 +99,9 @@ TEST_F(StreamPrintTest, ScientificNotation) { TEST_F(StreamPrintTest, MultipleWrites) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "* Header\n"); - streamPrint(out, ".tran %.3g %.3g\n", 1e-13, 1e-9); - streamPrint(out, ".end\n"); + sta::print(out, "* Header\n"); + sta::print(out, ".tran {:.3g} {:.3g}\n", 1e-13, 1e-9); + sta::print(out, ".end\n"); out.close(); std::ifstream in(tmpfile_); @@ -182,11 +182,11 @@ TEST_F(XyceCsvTest, FileNotReadableThrows) { ); } -// Additional streamPrint tests for format coverage +// Additional print tests for format coverage TEST_F(StreamPrintTest, EmptyString) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "%s", ""); + sta::print(out, "{}", ""); out.close(); std::ifstream in(tmpfile_); @@ -200,7 +200,7 @@ TEST_F(StreamPrintTest, LongString) { ASSERT_TRUE(out.is_open()); // Build a long subcircuit line std::string long_name(200, 'x'); - streamPrint(out, ".subckt %s\n", long_name.c_str()); + sta::print(out, ".subckt {}\n", long_name.c_str()); out.close(); std::ifstream in(tmpfile_); @@ -213,7 +213,7 @@ TEST_F(StreamPrintTest, LongString) { TEST_F(StreamPrintTest, SpiceResistor) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "R%d %s %s %.4e\n", 1, "n1", "n2", 1.0e3); + sta::print(out, "R{} {} {} {:.4e}\n", 1, "n1", "n2", 1.0e3); out.close(); std::ifstream in(tmpfile_); @@ -227,7 +227,7 @@ TEST_F(StreamPrintTest, SpiceResistor) { TEST_F(StreamPrintTest, SpiceComment) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "* %s\n", "This is a SPICE comment"); + sta::print(out, "* {}\n", "This is a SPICE comment"); out.close(); std::ifstream in(tmpfile_); @@ -240,7 +240,7 @@ TEST_F(StreamPrintTest, SpiceComment) { TEST_F(StreamPrintTest, SpiceSubcktInstantiation) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "x%s %s %s %s %s %s\n", + sta::print(out, "x{} {} {} {} {} {}\n", "inst1", "vdd", "vss", "in", "out", "INV"); out.close(); @@ -254,7 +254,7 @@ TEST_F(StreamPrintTest, SpiceSubcktInstantiation) { TEST_F(StreamPrintTest, SpiceMeasure) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".measure tran %s trig v(%s) val=%.1f %s=%.3e\n", + sta::print(out, ".measure tran {} trig v({}) val={:.1f} {}={:.3e}\n", "delay", "in", 0.9, "targ", 1e-9); out.close(); @@ -346,11 +346,11 @@ TEST_F(SpiceSmokeTest, TransitionInitFinalString) { // Additional SPICE tests for function coverage //////////////////////////////////////////////////////////////// -// streamPrint with integers +// print with integers TEST_F(StreamPrintTest, IntegerFormats) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "R%d %d %d %d\n", 1, 100, 200, 50000); + sta::print(out, "R{} {} {} {}\n", 1, 100, 200, 50000); out.close(); std::ifstream in(tmpfile_); @@ -359,11 +359,11 @@ TEST_F(StreamPrintTest, IntegerFormats) { EXPECT_EQ(line, "R1 100 200 50000"); } -// streamPrint with mixed types +// print with mixed types TEST_F(StreamPrintTest, MixedTypes) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".param %s=%g\n", "vdd", 1.8); + sta::print(out, ".param {}={:g}\n", "vdd", 1.8); out.close(); std::ifstream in(tmpfile_); @@ -374,11 +374,11 @@ TEST_F(StreamPrintTest, MixedTypes) { EXPECT_NE(line.find("1.8"), std::string::npos); } -// streamPrint with percent +// print with percent TEST_F(StreamPrintTest, PercentLiteral) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "value = 100%%\n"); + sta::print(out, "value = 100%\n"); out.close(); std::ifstream in(tmpfile_); @@ -387,12 +387,12 @@ TEST_F(StreamPrintTest, PercentLiteral) { EXPECT_NE(line.find("100%"), std::string::npos); } -// streamPrint with very long format +// print with very long format TEST_F(StreamPrintTest, VeryLongFormat) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); std::string long_name(500, 'n'); - streamPrint(out, ".subckt %s port1 port2 port3\n", long_name.c_str()); + sta::print(out, ".subckt {} port1 port2 port3\n", long_name.c_str()); out.close(); std::ifstream in(tmpfile_); @@ -502,11 +502,11 @@ TEST_F(SpiceSmokeTest, TransitionFind) { EXPECT_EQ(Transition::find("v"), Transition::fall()); } -// Test streamPrint with empty format +// Test print with empty format TEST_F(StreamPrintTest, EmptyFormat) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "%s", ""); + sta::print(out, "{}", ""); out.close(); std::ifstream in(tmpfile_); @@ -515,11 +515,11 @@ TEST_F(StreamPrintTest, EmptyFormat) { EXPECT_EQ(content, ""); } -// Test streamPrint with integer formatting +// Test print with integer formatting TEST_F(StreamPrintTest, IntegerFormatting) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "R%d %d %d %.2f\n", 1, 10, 20, 100.5); + sta::print(out, "R{} {} {} {:.2f}\n", 1, 10, 20, 100.5); out.close(); std::ifstream in(tmpfile_); @@ -528,13 +528,13 @@ TEST_F(StreamPrintTest, IntegerFormatting) { EXPECT_EQ(line, "R1 10 20 100.50"); } -// Test streamPrint with multiple lines +// Test print with multiple lines TEST_F(StreamPrintTest, MultipleLines) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "line1\n"); - streamPrint(out, "line2\n"); - streamPrint(out, "line3\n"); + sta::print(out, "line1\n"); + sta::print(out, "line2\n"); + sta::print(out, "line3\n"); out.close(); std::ifstream in(tmpfile_); @@ -547,11 +547,11 @@ TEST_F(StreamPrintTest, MultipleLines) { EXPECT_EQ(line, "line3"); } -// Test streamPrint with special characters +// Test print with special characters TEST_F(StreamPrintTest, SpecialChars) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "* SPICE deck for %s\n", "test_design"); + sta::print(out, "* SPICE deck for {}\n", "test_design"); out.close(); std::ifstream in(tmpfile_); @@ -609,12 +609,12 @@ TEST_F(SpiceSmokeTest, MinMaxOpposite) { // R6_ tests for Spice function coverage //////////////////////////////////////////////////////////////// -// Test streamPrint with wide variety of format specifiers -// Covers: streamPrint with many format types +// Test print with wide variety of format specifiers +// Covers: print with many format types TEST_F(StreamPrintTest, FormatSpecifiers) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "%c %s %d %f %e %g\n", 'A', "test", 42, 3.14, 1.5e-12, 1.8); + sta::print(out, "{:c} {} {} {} {:e} {:g}\n", 'A', "test", 42, 3.14, 1.5e-12, 1.8); out.close(); std::ifstream in(tmpfile_); @@ -625,12 +625,12 @@ TEST_F(StreamPrintTest, FormatSpecifiers) { EXPECT_NE(line.find("42"), std::string::npos); } -// Test streamPrint with SPICE node naming -// Covers: streamPrint for SPICE net naming patterns +// Test print with SPICE node naming +// Covers: print for SPICE net naming patterns TEST_F(StreamPrintTest, SpiceNodeNaming) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "C%d %s %s %.4e\n", 1, "n_top/sub/net:1", "0", 1.5e-15); + sta::print(out, "C{} {} {} {:.4e}\n", 1, "n_top/sub/net:1", "0", 1.5e-15); out.close(); std::ifstream in(tmpfile_); @@ -640,12 +640,12 @@ TEST_F(StreamPrintTest, SpiceNodeNaming) { EXPECT_NE(line.find("n_top/sub/net:1"), std::string::npos); } -// Test streamPrint with SPICE .include directive -// Covers: streamPrint for SPICE directives +// Test print with SPICE .include directive +// Covers: print for SPICE directives TEST_F(StreamPrintTest, SpiceIncludeDirective) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".include \"%s\"\n", "/path/to/models.spice"); + sta::print(out, ".include \"{}\"\n", "/path/to/models.spice"); out.close(); std::ifstream in(tmpfile_); @@ -655,12 +655,12 @@ TEST_F(StreamPrintTest, SpiceIncludeDirective) { EXPECT_NE(line.find("/path/to/models.spice"), std::string::npos); } -// Test streamPrint SPICE voltage source -// Covers: streamPrint for voltage sources +// Test print SPICE voltage source +// Covers: print for voltage sources TEST_F(StreamPrintTest, SpiceVoltageSource) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v%s %s 0 %.3f\n", "dd", "vdd", 1.800); + sta::print(out, "v{} {} 0 {:.3f}\n", "dd", "vdd", 1.800); out.close(); std::ifstream in(tmpfile_); @@ -669,12 +669,12 @@ TEST_F(StreamPrintTest, SpiceVoltageSource) { EXPECT_EQ(line, "vdd vdd 0 1.800"); } -// Test streamPrint SPICE .tran with detailed parameters -// Covers: streamPrint for transient analysis +// Test print SPICE .tran with detailed parameters +// Covers: print for transient analysis TEST_F(StreamPrintTest, SpiceTransAnalysis) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".tran %g %g %g %g\n", 1e-13, 5e-9, 0.0, 1e-12); + sta::print(out, ".tran {:g} {:g} {:g} {:g}\n", 1e-13, 5e-9, 0.0, 1e-12); out.close(); std::ifstream in(tmpfile_); @@ -683,15 +683,15 @@ TEST_F(StreamPrintTest, SpiceTransAnalysis) { EXPECT_NE(line.find(".tran"), std::string::npos); } -// Test streamPrint SPICE PWL source -// Covers: streamPrint with PWL voltage source +// Test print SPICE PWL source +// Covers: print with PWL voltage source TEST_F(StreamPrintTest, SpicePWLSource) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v_in in 0 PWL(\n"); - streamPrint(out, "+%.3e %.3f\n", 0.0, 0.0); - streamPrint(out, "+%.3e %.3f\n", 1e-10, 1.8); - streamPrint(out, "+%.3e %.3f)\n", 2e-10, 1.8); + sta::print(out, "v_in in 0 PWL(\n"); + sta::print(out, "+{:.3e} {:.3f}\n", 0.0, 0.0); + sta::print(out, "+{:.3e} {:.3f}\n", 1e-10, 1.8); + sta::print(out, "+{:.3e} {:.3f})\n", 2e-10, 1.8); out.close(); std::ifstream in(tmpfile_); @@ -812,12 +812,12 @@ TEST_F(SpiceSmokeTest, RiseFallShortName) { // R8_ tests for SPICE module coverage improvement //////////////////////////////////////////////////////////////// -// Test streamPrint with SPICE transistor format (used in writeParasiticNetwork) -// Covers: streamPrint paths used by WriteSpice +// Test print with SPICE transistor format (used in writeParasiticNetwork) +// Covers: print paths used by WriteSpice TEST_F(StreamPrintTest, SpiceTransistorFormat) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "M%d %s %s %s %s %s W=%.3e L=%.3e\n", + sta::print(out, "M{} {} {} {} {} {} W={:.3e} L={:.3e}\n", 1, "drain", "gate", "source", "bulk", "NMOS", 1.0e-6, 45.0e-9); out.close(); @@ -830,13 +830,13 @@ TEST_F(StreamPrintTest, SpiceTransistorFormat) { EXPECT_NE(line.find("NMOS"), std::string::npos); } -// Test streamPrint with SPICE capacitor format (used in writeParasiticNetwork) -// Covers: streamPrint paths used by WriteSpice::writeParasiticNetwork +// Test print with SPICE capacitor format (used in writeParasiticNetwork) +// Covers: print paths used by WriteSpice::writeParasiticNetwork TEST_F(StreamPrintTest, SpiceCapacitorFormat) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "C%d %s %s %.4e\n", 1, "net1:1", "0", 1.5e-15); - streamPrint(out, "C%d %s %s %.4e\n", 2, "net1:2", "net1:3", 2.5e-15); + sta::print(out, "C{} {} {} {:.4e}\n", 1, "net1:1", "0", 1.5e-15); + sta::print(out, "C{} {} {} {:.4e}\n", 2, "net1:2", "net1:3", 2.5e-15); out.close(); std::ifstream in(tmpfile_); @@ -847,12 +847,12 @@ TEST_F(StreamPrintTest, SpiceCapacitorFormat) { EXPECT_TRUE(line2.find("C2") == 0); } -// Test streamPrint with SPICE voltage source (used in writeClkedStepSource) -// Covers: streamPrint paths used by WriteSpice::writeClkedStepSource +// Test print with SPICE voltage source (used in writeClkedStepSource) +// Covers: print paths used by WriteSpice::writeClkedStepSource TEST_F(StreamPrintTest, SpiceVoltageSource2) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v%s %s 0 pwl(0 %.3f %.3e %.3f)\n", + sta::print(out, "v{} {} 0 pwl(0 {:.3f} {:.3e} {:.3f})\n", "clk", "clk_node", 0.0, 1e-9, 1.8); out.close(); @@ -863,16 +863,16 @@ TEST_F(StreamPrintTest, SpiceVoltageSource2) { EXPECT_NE(line.find("pwl"), std::string::npos); } -// Test streamPrint with SPICE waveform format (used in writeWaveformVoltSource) -// Covers: streamPrint paths used by WriteSpice::writeWaveformVoltSource +// Test print with SPICE waveform format (used in writeWaveformVoltSource) +// Covers: print paths used by WriteSpice::writeWaveformVoltSource TEST_F(StreamPrintTest, SpiceWaveformFormat) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v%s %s 0 pwl(\n", "in", "in_node"); - streamPrint(out, "+ %.3e %.3f\n", 0.0, 0.0); - streamPrint(out, "+ %.3e %.3f\n", 1e-10, 0.9); - streamPrint(out, "+ %.3e %.3f\n", 2e-10, 1.8); - streamPrint(out, "+)\n"); + sta::print(out, "v{} {} 0 pwl(\n", "in", "in_node"); + sta::print(out, "+ {:.3e} {:.3f}\n", 0.0, 0.0); + sta::print(out, "+ {:.3e} {:.3f}\n", 1e-10, 0.9); + sta::print(out, "+ {:.3e} {:.3f}\n", 2e-10, 1.8); + sta::print(out, "+)\n"); out.close(); std::ifstream in(tmpfile_); @@ -882,16 +882,16 @@ TEST_F(StreamPrintTest, SpiceWaveformFormat) { EXPECT_NE(content.find("pwl"), std::string::npos); } -// Test streamPrint with SPICE .measure format (used in spiceTrans context) -// Covers: streamPrint with RISE/FALL strings (used by WriteSpice::spiceTrans) +// Test print with SPICE .measure format (used in spiceTrans context) +// Covers: print with RISE/FALL strings (used by WriteSpice::spiceTrans) TEST_F(StreamPrintTest, SpiceMeasureRiseFall) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); // This mimics how spiceTrans returns RISE/FALL strings const char *rise_str = "RISE"; const char *fall_str = "FALL"; - streamPrint(out, ".measure tran delay_rf trig v(in) val=0.9 %s=last\n", rise_str); - streamPrint(out, "+targ v(out) val=0.9 %s=last\n", fall_str); + sta::print(out, ".measure tran delay_rf trig v(in) val=0.9 {}=last\n", rise_str); + sta::print(out, "+targ v(out) val=0.9 {}=last\n", fall_str); out.close(); std::ifstream in(tmpfile_); @@ -950,15 +950,15 @@ TEST_F(XyceCsvTest, ReadCsvManySignals) { // R9_ tests for SPICE module coverage improvement //////////////////////////////////////////////////////////////// -// streamPrint: SPICE subcircuit definition (used by WriteSpice) +// print: SPICE subcircuit definition (used by WriteSpice) TEST_F(StreamPrintTest, SpiceSubcktDefinition) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".subckt %s %s %s %s %s\n", + sta::print(out, ".subckt {} {} {} {} {}\n", "INV_X1", "VDD", "VSS", "A", "Y"); - streamPrint(out, "M1 Y A VDD VDD PMOS W=%.3e L=%.3e\n", 200e-9, 45e-9); - streamPrint(out, "M2 Y A VSS VSS NMOS W=%.3e L=%.3e\n", 100e-9, 45e-9); - streamPrint(out, ".ends %s\n", "INV_X1"); + sta::print(out, "M1 Y A VDD VDD PMOS W={:.3e} L={:.3e}\n", 200e-9, 45e-9); + sta::print(out, "M2 Y A VSS VSS NMOS W={:.3e} L={:.3e}\n", 100e-9, 45e-9); + sta::print(out, ".ends {}\n", "INV_X1"); out.close(); std::ifstream in(tmpfile_); @@ -970,12 +970,12 @@ TEST_F(StreamPrintTest, SpiceSubcktDefinition) { EXPECT_NE(content.find("NMOS"), std::string::npos); } -// streamPrint: SPICE resistor network (used in writeParasiticNetwork) +// print: SPICE resistor network (used in writeParasiticNetwork) TEST_F(StreamPrintTest, SpiceResistorNetwork) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); for (int i = 0; i < 10; i++) { - streamPrint(out, "R%d n%d n%d %.4e\n", i+1, i, i+1, 50.0 + i*10.0); + sta::print(out, "R{} n{} n{} {:.4e}\n", i+1, i, i+1, 50.0 + i*10.0); } out.close(); @@ -986,12 +986,12 @@ TEST_F(StreamPrintTest, SpiceResistorNetwork) { EXPECT_NE(content.find("R10"), std::string::npos); } -// streamPrint: SPICE capacitor network (used in writeParasiticNetwork) +// print: SPICE capacitor network (used in writeParasiticNetwork) TEST_F(StreamPrintTest, SpiceCapacitorNetwork) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); for (int i = 0; i < 10; i++) { - streamPrint(out, "C%d n%d 0 %.4e\n", i+1, i, 1e-15 * (i+1)); + sta::print(out, "C{} n{} 0 {:.4e}\n", i+1, i, 1e-15 * (i+1)); } out.close(); @@ -1002,11 +1002,11 @@ TEST_F(StreamPrintTest, SpiceCapacitorNetwork) { EXPECT_NE(content.find("C10"), std::string::npos); } -// streamPrint: SPICE .lib directive +// print: SPICE .lib directive TEST_F(StreamPrintTest, SpiceLibDirective) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".lib '%s' %s\n", "/path/to/models.lib", "tt"); + sta::print(out, ".lib '{}' {}\n", "/path/to/models.lib", "tt"); out.close(); std::ifstream in(tmpfile_); @@ -1016,11 +1016,11 @@ TEST_F(StreamPrintTest, SpiceLibDirective) { EXPECT_NE(line.find("tt"), std::string::npos); } -// streamPrint: SPICE .option directive +// print: SPICE .option directive TEST_F(StreamPrintTest, SpiceOptionDirective) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".option %s=%g %s=%g\n", "reltol", 1e-6, "abstol", 1e-12); + sta::print(out, ".option {}={:g} {}={:g}\n", "reltol", 1e-6, "abstol", 1e-12); out.close(); std::ifstream in(tmpfile_); @@ -1030,11 +1030,11 @@ TEST_F(StreamPrintTest, SpiceOptionDirective) { EXPECT_NE(line.find("reltol"), std::string::npos); } -// streamPrint: SPICE .print directive +// print: SPICE .print directive TEST_F(StreamPrintTest, SpicePrintDirective) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".print tran v(%s) v(%s) v(%s)\n", + sta::print(out, ".print tran v({}) v({}) v({})\n", "input", "output", "clk"); out.close(); @@ -1046,11 +1046,11 @@ TEST_F(StreamPrintTest, SpicePrintDirective) { EXPECT_NE(line.find("v(output)"), std::string::npos); } -// streamPrint: SPICE pulse source +// print: SPICE pulse source TEST_F(StreamPrintTest, SpicePulseSource) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "v%s %s 0 PULSE(%.3f %.3f %.3e %.3e %.3e %.3e %.3e)\n", + sta::print(out, "v{} {} 0 PULSE({:.3f} {:.3f} {:.3e} {:.3e} {:.3e} {:.3e} {:.3e})\n", "clk", "clk_node", 0.0, 1.8, 0.0, 20e-12, 20e-12, 500e-12, 1e-9); out.close(); @@ -1061,13 +1061,13 @@ TEST_F(StreamPrintTest, SpicePulseSource) { EXPECT_NE(line.find("PULSE"), std::string::npos); } -// streamPrint: SPICE mutual inductance +// print: SPICE mutual inductance TEST_F(StreamPrintTest, SpiceMutualInductance) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "L%d %s %s %.4e\n", 1, "n1", "n2", 1e-9); - streamPrint(out, "L%d %s %s %.4e\n", 2, "n3", "n4", 1e-9); - streamPrint(out, "K%d L%d L%d %.4f\n", 1, 1, 2, 0.5); + sta::print(out, "L{} {} {} {:.4e}\n", 1, "n1", "n2", 1e-9); + sta::print(out, "L{} {} {} {:.4e}\n", 2, "n3", "n4", 1e-9); + sta::print(out, "K{} L{} L{} {:.4f}\n", 1, 1, 2, 0.5); out.close(); std::ifstream in(tmpfile_); @@ -1077,11 +1077,11 @@ TEST_F(StreamPrintTest, SpiceMutualInductance) { EXPECT_NE(content.find("K1"), std::string::npos); } -// streamPrint: SPICE probe statement +// print: SPICE probe statement TEST_F(StreamPrintTest, SpiceProbeStatement) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".probe v(%s) v(%s) i(%s)\n", + sta::print(out, ".probe v({}) v({}) i({})\n", "out", "in", "v_supply"); out.close(); @@ -1091,12 +1091,12 @@ TEST_F(StreamPrintTest, SpiceProbeStatement) { EXPECT_NE(line.find(".probe"), std::string::npos); } -// streamPrint: SPICE with escaped characters +// print: SPICE with escaped characters TEST_F(StreamPrintTest, SpiceEscapedChars) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "* Node: %s\n", "top/sub/inst:pin"); - streamPrint(out, "R1 %s %s %.4e\n", + sta::print(out, "* Node: {}\n", "top/sub/inst:pin"); + sta::print(out, "R1 {} {} {:.4e}\n", "top/sub/inst:pin", "top/sub/inst:int", 100.0); out.close(); @@ -1106,25 +1106,25 @@ TEST_F(StreamPrintTest, SpiceEscapedChars) { EXPECT_NE(content.find("top/sub/inst:pin"), std::string::npos); } -// streamPrint: SPICE full deck structure +// print: SPICE full deck structure TEST_F(StreamPrintTest, SpiceFullDeck) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, "* Full SPICE deck\n"); - streamPrint(out, ".include \"%s\"\n", "models.spice"); - streamPrint(out, ".subckt top VDD VSS IN OUT\n"); - streamPrint(out, "R1 IN n1 %.2e\n", 50.0); - streamPrint(out, "C1 n1 VSS %.4e\n", 1e-15); - streamPrint(out, "xinv VDD VSS n1 OUT INV_X1\n"); - streamPrint(out, ".ends top\n"); - streamPrint(out, "\n"); - streamPrint(out, "xinst VDD VSS IN OUT top\n"); - streamPrint(out, "vvdd VDD 0 %.3f\n", 1.8); - streamPrint(out, "vvss VSS 0 0\n"); - streamPrint(out, "vin IN 0 PULSE(0 %.3f 0 %.3e %.3e %.3e %.3e)\n", + sta::print(out, "* Full SPICE deck\n"); + sta::print(out, ".include \"{}\"\n", "models.spice"); + sta::print(out, ".subckt top VDD VSS IN OUT\n"); + sta::print(out, "R1 IN n1 {:.2e}\n", 50.0); + sta::print(out, "C1 n1 VSS {:.4e}\n", 1e-15); + sta::print(out, "xinv VDD VSS n1 OUT INV_X1\n"); + sta::print(out, ".ends top\n"); + sta::print(out, "\n"); + sta::print(out, "xinst VDD VSS IN OUT top\n"); + sta::print(out, "vvdd VDD 0 {:.3f}\n", 1.8); + sta::print(out, "vvss VSS 0 0\n"); + sta::print(out, "vin IN 0 PULSE(0 {:.3f} 0 {:.3e} {:.3e} {:.3e} {:.3e})\n", 1.8, 20e-12, 20e-12, 500e-12, 1e-9); - streamPrint(out, ".tran %.3e %.3e\n", 1e-13, 2e-9); - streamPrint(out, ".end\n"); + sta::print(out, ".tran {:.3e} {:.3e}\n", 1e-13, 2e-9); + sta::print(out, ".end\n"); out.close(); std::ifstream in(tmpfile_); @@ -1345,11 +1345,11 @@ TEST_F(XyceCsvTest, ReadCsvAlternatingSign) { EXPECT_EQ(waveforms.size(), 1u); } -// streamPrint: SPICE .end directive +// print: SPICE .end directive TEST_F(StreamPrintTest, SpiceEndDirective) { std::ofstream out(tmpfile_); ASSERT_TRUE(out.is_open()); - streamPrint(out, ".end\n"); + sta::print(out, ".end\n"); out.close(); std::ifstream in(tmpfile_); @@ -1734,7 +1734,7 @@ TEST_F(SpiceDesignTest, InstanceCellName) { EXPECT_STREQ(cell_name, "DFF_X1"); } -// Verify streamPrint with SPICE subcircuit instance format for design cells +// Verify print with SPICE subcircuit instance format for design cells TEST_F(SpiceDesignTest, StreamPrintSubcktInst) { char tmpl[] = "/tmp/sta_spice_subckt_inst_XXXXXX"; int fd = mkstemp(tmpl); @@ -1749,7 +1749,7 @@ TEST_F(SpiceDesignTest, StreamPrintSubcktInst) { std::ofstream out(tmpl); ASSERT_TRUE(out.is_open()); - streamPrint(out, "x%s VDD VSS %s\n", inst_name, cell_name); + sta::print(out, "x{} VDD VSS {}\n", inst_name, cell_name); out.close(); std::ifstream in(tmpl); diff --git a/util/test/cpp/TestUtil.cc b/util/test/cpp/TestUtil.cc index 97e6798c..ad45914b 100644 --- a/util/test/cpp/TestUtil.cc +++ b/util/test/cpp/TestUtil.cc @@ -842,7 +842,7 @@ TEST(ReportTest, RedirectStringBasic) { Report report; report.redirectStringBegin(); - report.reportLineString("hello world"); + report.reportLine("hello world"); const char *result = report.redirectStringEnd(); EXPECT_NE(result, nullptr); std::string s(result); @@ -853,8 +853,8 @@ TEST(ReportTest, RedirectStringMultipleLines) { Report report; report.redirectStringBegin(); - report.reportLineString("line1"); - report.reportLineString("line2"); + report.reportLine("line1"); + report.reportLine("line2"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("line1"), std::string::npos); @@ -866,7 +866,7 @@ TEST(ReportTest, RedirectStringStdString) Report report; report.redirectStringBegin(); std::string line = "std string line"; - report.reportLineString(line); + report.reportLine(line); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("std string line"), std::string::npos); @@ -886,7 +886,7 @@ TEST(ReportTest, ReportLineFormatted) { Report report; report.redirectStringBegin(); - report.reportLine("value=%d", 42); + report.report("value={}", 42); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("value=42"), std::string::npos); @@ -897,7 +897,7 @@ TEST(ReportTest, LogToFile) Report report; const char *tmpfile = "/tmp/test_report_log.txt"; report.logBegin(tmpfile); - report.reportLineString("log test line"); + report.reportLine("log test line"); report.logEnd(); // Verify file was created with content FILE *f = fopen(tmpfile, "r"); @@ -924,7 +924,7 @@ TEST(ReportTest, RedirectFileBegin) Report report; const char *tmpfile = "/tmp/test_report_redirect.txt"; report.redirectFileBegin(tmpfile); - report.reportLineString("redirected line"); + report.reportLine("redirected line"); report.redirectFileEnd(); FILE *f = fopen(tmpfile, "r"); @@ -943,12 +943,12 @@ TEST(ReportTest, RedirectFileAppendBegin) // Write first report.redirectFileBegin(tmpfile); - report.reportLineString("first"); + report.reportLine("first"); report.redirectFileEnd(); // Append report.redirectFileAppendBegin(tmpfile); - report.reportLineString("second"); + report.reportLine("second"); report.redirectFileEnd(); FILE *f = fopen(tmpfile, "r"); @@ -997,7 +997,7 @@ TEST(ReportTest, WarnBasic) { Report report; report.redirectStringBegin(); - report.warn(100, "something bad %d", 42); + report.warn(100, "something bad {}", 42); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 100:"), std::string::npos); @@ -1008,7 +1008,7 @@ TEST(ReportTest, FileWarn) { Report report; report.redirectStringBegin(); - report.fileWarn(101, "test.v", 10, "missing %s", "semicolon"); + report.fileWarn(101, "test.v", 10, "missing {}", "semicolon"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 101:"), std::string::npos); @@ -1022,7 +1022,7 @@ TEST(ReportTest, VwarnBasic) Report report; report.redirectStringBegin(); // Use vwarn indirectly via warn (vwarn is called by warn internals) - report.warn(102, "vwarn test %s", "value"); + report.warn(102, "warn test {}", "value"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 102:"), std::string::npos); @@ -1031,14 +1031,14 @@ TEST(ReportTest, VwarnBasic) TEST(ReportTest, ErrorThrows) { Report report; - EXPECT_THROW(report.error(200, "error message %d", 1), ExceptionMsg); + EXPECT_THROW(report.error(200, "error message {}", 1), ExceptionMsg); } TEST(ReportTest, ErrorMessageContent) { Report report; try { - report.error(200, "specific error %s", "info"); + report.error(200, "specific error {}", "info"); FAIL() << "Expected ExceptionMsg"; } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -1056,7 +1056,7 @@ TEST(ReportTest, FileErrorContent) { Report report; try { - report.fileError(201, "test.sdc", 5, "unexpected token %s", "foo"); + report.fileError(201, "test.sdc", 5, "unexpected token {}", "foo"); FAIL() << "Expected ExceptionMsg"; } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -1146,7 +1146,7 @@ TEST(ReportTest, LogAndConsoleSimultaneous) const char *logfile = "/tmp/test_report_logconsole.txt"; report.logBegin(logfile); // Print to console (with log capturing) - report.reportLineString("dual output"); + report.reportLine("dual output"); report.logEnd(); FILE *f = fopen(logfile, "r"); @@ -1177,38 +1177,35 @@ TEST(StringUtilTest, StringCopyNull) EXPECT_EQ(copy, nullptr); } -TEST(StringUtilTest, StdstrPrint) +TEST(StringUtilTest, StaFormat) { - std::string s = stdstrPrint("value=%d", 42); + std::string s = sta::format("value={}", 42); EXPECT_EQ(s, "value=42"); } -TEST(StringUtilTest, StringPrintToStdString) +TEST(StringUtilTest, StaFormatToStdString) { - std::string s; - stringPrint(s, "test %s %d", "abc", 123); + std::string s = sta::format("test {} {}", "abc", 123); EXPECT_EQ(s, "test abc 123"); } -TEST(StringUtilTest, StringAppendToStdString) +TEST(StringUtilTest, StaFormatAppendToStdString) { std::string s = "prefix "; - stringAppend(s, "suffix %d", 1); + s += sta::format("suffix {}", 1); EXPECT_EQ(s, "prefix suffix 1"); } -TEST(StringUtilTest, StringPrintAllocates) +TEST(StringUtilTest, StaFormatAllocates) { - char *s = stringPrint("number %d", 99); - EXPECT_STREQ(s, "number 99"); - stringDelete(s); + std::string s = sta::format("number {}", 99); + EXPECT_EQ(s, "number 99"); } -TEST(StringUtilTest, StringPrintTmp) +TEST(StringUtilTest, StaFormatTmp) { - char *s = stringPrintTmp("tmp %d", 42); - EXPECT_STREQ(s, "tmp 42"); - // tmp strings should not be freed by the caller + std::string s = sta::format("tmp {}", 42); + EXPECT_EQ(s, "tmp 42"); } TEST(StringUtilTest, MakeTmpString) @@ -1229,7 +1226,8 @@ TEST(StringUtilTest, MakeTmpStringFromStdString) TEST(StringUtilTest, IsTmpString) { - char *tmp = stringPrintTmp("test"); + char *tmp = makeTmpString(10); + strcpy(tmp, "test"); EXPECT_TRUE(isTmpString(tmp)); char local[] = "local"; @@ -1370,7 +1368,7 @@ TEST(DebugTest, ReportLine) debug.setLevel("test", 1); // Redirect output to string to capture the debug line report.redirectStringBegin(); - debug.reportLine("test", "value %d", 42); + debug.report("test", "value {}", 42); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("test"), std::string::npos); @@ -1378,125 +1376,91 @@ TEST(DebugTest, ReportLine) } //////////////////////////////////////////////////////////////// -// Helper functions to test va_list variants of Report +// Tests for variadic template Report methods (warn, fileWarn, error, fileError) //////////////////////////////////////////////////////////////// -static void callVwarn(Report &report, int id, const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - report.vwarn(id, fmt, args); - va_end(args); -} - -static void callVfileWarn(Report &report, int id, const char *filename, - int line, const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - report.vfileWarn(id, filename, line, fmt, args); - va_end(args); -} - -static void callVerror(Report &report, int id, const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - report.verror(id, fmt, args); - va_end(args); -} - -static void callVfileError(Report &report, int id, const char *filename, - int line, const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - report.vfileError(id, filename, line, fmt, args); - va_end(args); -} - -TEST(ReportVaTest, VwarnBasic) +TEST(ReportVaTest, WarnBasic) { Report report; report.redirectStringBegin(); - callVwarn(report, 300, "vwarn message %d", 42); + report.warn(300, "warn message {}", 42); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 300:"), std::string::npos); - EXPECT_NE(s.find("vwarn message 42"), std::string::npos); + EXPECT_NE(s.find("warn message 42"), std::string::npos); } -TEST(ReportVaTest, VwarnSuppressed) +TEST(ReportVaTest, WarnSuppressed) { Report report; report.suppressMsgId(300); report.redirectStringBegin(); - callVwarn(report, 300, "suppressed vwarn"); + report.warn(300, "suppressed warn"); const char *result = report.redirectStringEnd(); std::string s(result); - EXPECT_EQ(s.find("suppressed vwarn"), std::string::npos); + EXPECT_EQ(s.find("suppressed warn"), std::string::npos); } -TEST(ReportVaTest, VfileWarnBasic) +TEST(ReportVaTest, FileWarnBasic) { Report report; report.redirectStringBegin(); - callVfileWarn(report, 301, "test.v", 15, "vfile warn msg %s", "detail"); + report.fileWarn(301, "test.v", 15, "file warn msg {}", "detail"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 301:"), std::string::npos); EXPECT_NE(s.find("test.v"), std::string::npos); EXPECT_NE(s.find("line 15"), std::string::npos); - EXPECT_NE(s.find("vfile warn msg detail"), std::string::npos); + EXPECT_NE(s.find("file warn msg detail"), std::string::npos); } -TEST(ReportVaTest, VfileWarnSuppressed) +TEST(ReportVaTest, FileWarnSuppressed) { Report report; report.suppressMsgId(301); report.redirectStringBegin(); - callVfileWarn(report, 301, "test.v", 15, "suppressed vfile warn"); + report.fileWarn(301, "test.v", 15, "suppressed file warn"); const char *result = report.redirectStringEnd(); std::string s(result); - EXPECT_EQ(s.find("suppressed vfile warn"), std::string::npos); + EXPECT_EQ(s.find("suppressed file warn"), std::string::npos); } -TEST(ReportVaTest, VerrorThrows) +TEST(ReportVaTest, ErrorThrows) { Report report; - EXPECT_THROW(callVerror(report, 400, "verror msg %d", 99), ExceptionMsg); + EXPECT_THROW(report.error(400, "error msg {}", 99), ExceptionMsg); } -TEST(ReportVaTest, VerrorContent) +TEST(ReportVaTest, ErrorContent) { Report report; try { - callVerror(report, 400, "verror content %s", "test"); + report.error(400, "error content {}", "test"); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); - EXPECT_NE(what.find("verror content test"), std::string::npos); + EXPECT_NE(what.find("error content test"), std::string::npos); } } -TEST(ReportVaTest, VfileErrorThrows) +TEST(ReportVaTest, FileErrorThrows) { Report report; - EXPECT_THROW(callVfileError(report, 401, "myfile.sdc", 20, "vfile error msg"), + EXPECT_THROW(report.fileError(401, "myfile.sdc", 20, "file error msg"), ExceptionMsg); } -TEST(ReportVaTest, VfileErrorContent) +TEST(ReportVaTest, FileErrorContent) { Report report; try { - callVfileError(report, 401, "myfile.sdc", 20, "vfile error %d", 42); + report.fileError(401, "myfile.sdc", 20, "file error {}", 42); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); EXPECT_NE(what.find("myfile.sdc"), std::string::npos); EXPECT_NE(what.find("line 20"), std::string::npos); - EXPECT_NE(what.find("vfile error 42"), std::string::npos); + EXPECT_NE(what.find("file error 42"), std::string::npos); } } @@ -1507,7 +1471,7 @@ TEST(ReportTest, LongReportLine) report.redirectStringBegin(); // Create a string longer than the initial 1000 char buffer std::string long_str(2000, 'x'); - report.reportLine("%s", long_str.c_str()); + report.reportLine(long_str); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find(long_str), std::string::npos); @@ -1518,7 +1482,7 @@ TEST(ReportTest, LongWarnLine) Report report; report.redirectStringBegin(); std::string long_str(2000, 'y'); - report.warn(500, "%s", long_str.c_str()); + report.warn(500, "{}", long_str); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 500:"), std::string::npos); @@ -1526,23 +1490,23 @@ TEST(ReportTest, LongWarnLine) } // Test ExceptionMsg suppressed flag -TEST(ReportVaTest, VerrorSuppressedFlag) +TEST(ReportVaTest, ErrorSuppressedFlag) { Report report; report.suppressMsgId(400); try { - callVerror(report, 400, "suppressed verror"); + report.error(400, "suppressed error"); FAIL(); } catch (const ExceptionMsg &e) { EXPECT_TRUE(e.suppressed()); } } -TEST(ReportVaTest, VerrorNotSuppressedFlag) +TEST(ReportVaTest, ErrorNotSuppressedFlag) { Report report; try { - callVerror(report, 400, "not suppressed"); + report.error(400, "not suppressed"); FAIL(); } catch (const ExceptionMsg &e) { EXPECT_FALSE(e.suppressed()); @@ -1820,19 +1784,18 @@ TEST(TransitionCovTest, RiseFallToString) // Additional StringUtil coverage //////////////////////////////////////////////////////////////// -TEST(StringUtilCovTest, StringPrintArgs) +TEST(StringUtilCovTest, StaFormatArgs) { - // stringPrintArgs is called by stringPrint internally; test via stringPrint - char *s = stringPrint("args test %d %s", 42, "hello"); - EXPECT_STREQ(s, "args test 42 hello"); - stringDelete(s); + // Test sta::format with multiple arguments + std::string s = sta::format("args test {} {}", 42, "hello"); + EXPECT_EQ(s, "args test 42 hello"); } // stringDeleteCheck (only for non-tmp strings - should not crash) TEST(StringUtilCovTest, StringDeleteCheckNonTmp) { ASSERT_NO_THROW(( [&](){ - char *s = stringPrint("not tmp"); + char *s = stringCopy("not tmp"); // This should not crash or exit; it's not a tmp string stringDeleteCheck(s); stringDelete(s); @@ -1849,23 +1812,21 @@ TEST(StringUtilCovTest, IsTmpStringHeap) delete [] s; } -// Long stringPrintTmp (forces buffer growth) -TEST(StringUtilCovTest, LongStringPrintTmp) +// Long sta::format string +TEST(StringUtilCovTest, LongStaFormat) { std::string long_str(500, 'z'); - char *tmp = stringPrintTmp("%s", long_str.c_str()); - EXPECT_STREQ(tmp, long_str.c_str()); + std::string result = sta::format("{}", long_str); + EXPECT_EQ(result, long_str); } -// stringAppend (char* version) inline in header -TEST(StringUtilCovTest, StringAppendCharPtr) +// std::string append +TEST(StringUtilCovTest, StringAppendStd) { - char buf[100]; - char *p = buf; - stringAppend(p, "hello"); - stringAppend(p, " world"); - *p = '\0'; - EXPECT_STREQ(buf, "hello world"); + std::string s; + s += "hello"; + s += " world"; + EXPECT_EQ(s, "hello world"); } //////////////////////////////////////////////////////////////// @@ -1886,7 +1847,7 @@ TEST(ReportCovTest, ReportLineStringEmpty) { Report report; report.redirectStringBegin(); - report.reportLineString(""); + report.reportLine(""); const char *result = report.redirectStringEnd(); std::string s(result); // Empty line should just have a newline @@ -1899,7 +1860,7 @@ TEST(ReportCovTest, ReportLineLongFormatted) Report report; report.redirectStringBegin(); std::string fmt_str(2000, 'a'); - report.reportLine("%s end", fmt_str.c_str()); + report.report("{} end", fmt_str); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find(fmt_str), std::string::npos); @@ -1914,12 +1875,12 @@ TEST(ReportCovTest, ReportRedirectSequence) // Redirect to file first report.redirectFileBegin(tmpfile); - report.reportLineString("file output"); + report.reportLine("file output"); report.redirectFileEnd(); // Then redirect to string report.redirectStringBegin(); - report.reportLineString("string output"); + report.reportLine("string output"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("string output"), std::string::npos); @@ -1935,7 +1896,7 @@ TEST(ReportCovTest, LogDuringStringRedirect) report.logBegin(logfile); report.redirectStringBegin(); - report.reportLineString("string only"); + report.reportLine("string only"); const char *result = report.redirectStringEnd(); report.logEnd(); @@ -1950,7 +1911,7 @@ TEST(ReportCovTest, WarnWithLongMessage) Report report; report.redirectStringBegin(); std::string long_msg(1500, 'w'); - report.warn(999, "prefix %s suffix", long_msg.c_str()); + report.warn(999, "prefix {} suffix", long_msg); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 999:"), std::string::npos); @@ -1964,7 +1925,7 @@ TEST(ReportCovTest, FileWarnLongMessage) Report report; report.redirectStringBegin(); std::string long_msg(1500, 'f'); - report.fileWarn(998, "bigfile.v", 100, "detail: %s", long_msg.c_str()); + report.fileWarn(998, "bigfile.v", 100, "detail: {}", long_msg); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 998:"), std::string::npos); @@ -1978,7 +1939,7 @@ TEST(ReportCovTest, ErrorLongMessage) Report report; std::string long_msg(1500, 'e'); try { - report.error(997, "err: %s", long_msg.c_str()); + report.error(997, "err: {}", long_msg); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -1993,7 +1954,7 @@ TEST(ReportCovTest, FileErrorLongMessage) Report report; std::string long_msg(1500, 'x'); try { - report.fileError(996, "big.sdc", 50, "detail: %s", long_msg.c_str()); + report.fileError(996, "big.sdc", 50, "detail: {}", long_msg); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -2396,14 +2357,14 @@ TEST(ReportCovTest, RedirectStringPrintMultiple) EXPECT_STREQ(result, "abcdefghi"); } -// Test Report printToBuffer with va_list -// Covers: Report::printToBuffer(const char*, va_list) -TEST(ReportCovTest, PrintToBufferViaReportLine) +// Test Report::report with format args +// Covers: Report::report(std::string_view, Args&&...) +TEST(ReportCovTest, ReportFormatViaReport) { Report report; report.redirectStringBegin(); - // reportLine calls printToBuffer internally - report.reportLine("value=%d", 42); + // report() uses std::format style formatting + report.report("value={}", 42); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("value=42"), std::string::npos); @@ -2414,7 +2375,7 @@ TEST(ReportCovTest, ReportLineString) { Report report; report.redirectStringBegin(); - report.reportLineString("test line"); + report.reportLine("test line"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("test line"), std::string::npos); @@ -2426,7 +2387,7 @@ TEST(ReportCovTest, ReportLineStringStd) Report report; report.redirectStringBegin(); std::string line = "std string line"; - report.reportLineString(line); + report.reportLine(line); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("std string line"), std::string::npos); @@ -2461,7 +2422,7 @@ TEST(ReportStdCovTest, PrintErrorConsoleViaWarn) ASSERT_NO_THROW(( [&](){ Report *report = makeReportStd(); // warn uses printErrorConsole path - report->warn(9999, "test warning %d", 42); + report->warn(9999, "test warning {}", 42); delete report; }() )); @@ -2496,7 +2457,7 @@ TEST(ReportCovTest, LogBeginEnd) Report report; const char *logfile = "/tmp/sta_test_log_r5.log"; report.logBegin(logfile); - report.reportLine("log line %d", 1); + report.report("log line {}", 1); report.logEnd(); // Verify log file exists and has content std::ifstream in(logfile); @@ -2590,7 +2551,7 @@ TEST(GzStreamTest, GzStreamWriteRead) TEST(ReportCovTest, ErrorThrowsException) { Report report; - EXPECT_THROW(report.error(1, "test error %s", "msg"), ExceptionMsg); + EXPECT_THROW(report.error(1, "test error {}", "msg"), ExceptionMsg); } // Test Report fileError throws ExceptionMsg @@ -2618,7 +2579,7 @@ TEST(ReportCovTest, ReportErrorFormatting) { Report report; try { - report.error(999, "critical format test %s %d", "value", 42); + report.error(999, "critical format test {} {}", "value", 42); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -2632,7 +2593,7 @@ TEST(ReportCovTest, ReportFileErrorFormatting) { Report report; try { - report.fileError(998, "critical.v", 42, "critical file error %s", "detail"); + report.fileError(998, "critical.v", 42, "critical file error {}", "detail"); FAIL(); } catch (const ExceptionMsg &e) { std::string what = e.what(); @@ -2660,7 +2621,7 @@ TEST(ReportCovTest, ReportStdCreation) ASSERT_NE(report, nullptr); // Verify it works as a Report report->redirectStringBegin(); - report->reportLineString("test via ReportStd"); + report->reportLine("test via ReportStd"); const char *result = report->redirectStringEnd(); EXPECT_NE(result, nullptr); std::string s(result); @@ -2675,7 +2636,7 @@ TEST(ReportCovTest, ReportStdWarn) Report *report = makeReportStd(); ASSERT_NE(report, nullptr); report->redirectStringBegin(); - report->warn(700, "reportstd warn test %d", 99); + report->warn(700, "reportstd warn test {}", 99); const char *result = report->redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 700:"), std::string::npos); @@ -2701,7 +2662,7 @@ TEST(ReportCovTest, ReportPrintToBufferLong) report.redirectStringBegin(); // Create a string exceeding the initial 1000-char buffer std::string long_str(3000, 'Z'); - report.reportLine("%s", long_str.c_str()); + report.reportLine(long_str); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find(long_str), std::string::npos); @@ -2780,7 +2741,7 @@ TEST(ReportCovTest, WarnLongMessage) Report report; report.redirectStringBegin(); std::string long_msg(5000, 'W'); - report.warn(800, "%s", long_msg.c_str()); + report.warn(800, "{}", long_msg); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 800:"), std::string::npos); @@ -2794,7 +2755,7 @@ TEST(ReportCovTest, FileWarnLongMessage2) Report report; report.redirectStringBegin(); std::string long_msg(2000, 'F'); - report.fileWarn(801, "long_file.v", 999, "%s", long_msg.c_str()); + report.fileWarn(801, "long_file.v", 999, "{}", long_msg); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning 801:"), std::string::npos); @@ -2841,13 +2802,13 @@ TEST(ReportCovTest, ErrorNotSuppressed) // because it calls abort(). Instead, test printToBuffer and // redirectStringPrint paths. -// Test Report::printToBuffer via reportLine -// Covers: Report::printToBuffer(const char*, va_list) -TEST(ReportCovTest, PrintToBufferViaReportLine2) +// Test Report::report with multiple format args +// Covers: Report::report(std::string_view, Args&&...) +TEST(ReportCovTest, ReportFormatViaReport2) { Report report; report.redirectStringBegin(); - report.reportLine("test %d %s %.2f", 42, "hello", 3.14); + report.report("test {} {} {:.2f}", 42, "hello", 3.14); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("42"), std::string::npos); @@ -2878,23 +2839,23 @@ TEST(ReportCovTest, RedirectStringPrintLong) Report report; report.redirectStringBegin(); std::string long_str(5000, 'X'); - report.reportLineString(long_str); + report.reportLine(long_str); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("XXXXX"), std::string::npos); } -// Test Report::printToBuffer with various format strings -// Covers: Report::printToBuffer(const char*, va_list) -TEST(ReportCovTest, PrintToBufferFormats) +// Test Report::report with various format strings +// Covers: Report::report(std::string_view, Args&&...) +TEST(ReportCovTest, ReportFormatVariousFormats) { Report report; report.redirectStringBegin(); - // Exercise various printf formats - report.reportLine("int: %d", 12345); - report.reportLine("float: %f", 1.5); - report.reportLine("string: %s", "test_string"); - report.reportLine("hex: %x", 0xFF); + // Exercise various std::format specifiers + report.report("int: {}", 12345); + report.report("float: {}", 1.5); + report.report("string: {}", "test_string"); + report.report("hex: {:x}", 0xFF); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("12345"), std::string::npos); @@ -2908,9 +2869,9 @@ TEST(ReportStdCovTest, ReportStdConstructorAndPrint) Report *report = makeReportStd(); ASSERT_NE(report, nullptr); // warn() calls printErrorConsole - report->warn(10001, "R8 test warning %s", "message"); + report->warn(10001, "R8 test warning {}", "message"); // reportLine calls printConsole - report->reportLine("R8 test print %d", 42); + report->report("R8 test print {}", 42); delete report; } @@ -2920,7 +2881,7 @@ TEST(ReportStdCovTest, PrintErrorConsoleViaFileWarn) { Report *report = makeReportStd(); ASSERT_NE(report, nullptr); - report->fileWarn(10002, "test_file.v", 100, "file warning %d", 99); + report->fileWarn(10002, "test_file.v", 100, "file warning {}", 99); delete report; } @@ -2930,7 +2891,7 @@ TEST(ReportCovTest, PrintToBufferEmpty) { Report report; report.redirectStringBegin(); - report.reportLine("%s", ""); + report.reportLine(""); const char *result = report.redirectStringEnd(); // Should have at least a newline EXPECT_NE(result, nullptr); @@ -2942,7 +2903,7 @@ TEST(ReportCovTest, WarnWithRedirect) { Report report; report.redirectStringBegin(); - report.warn(10003, "warning %d: %s", 1, "test"); + report.warn(10003, "warning {}: {}", 1, "test"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning"), std::string::npos); @@ -2955,7 +2916,7 @@ TEST(ReportCovTest, FileWarnWithRedirect) { Report report; report.redirectStringBegin(); - report.fileWarn(10004, "myfile.tcl", 42, "file issue %s", "here"); + report.fileWarn(10004, "myfile.tcl", 42, "file issue {}", "here"); const char *result = report.redirectStringEnd(); std::string s(result); EXPECT_NE(s.find("Warning"), std::string::npos); diff --git a/verilog/test/cpp/TestVerilog.cc b/verilog/test/cpp/TestVerilog.cc index cd959339..a12e2d50 100644 --- a/verilog/test/cpp/TestVerilog.cc +++ b/verilog/test/cpp/TestVerilog.cc @@ -51,31 +51,31 @@ TEST_F(VerilogTest, InstanceWithSlash) { // Verilog to STA conversions TEST_F(VerilogTest, ModuleToSta) { std::string name = "top"; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_EQ(result, "top"); } TEST_F(VerilogTest, InstanceToSta) { std::string name = "inst1"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_EQ(result, "inst1"); } TEST_F(VerilogTest, EscapedToSta) { std::string name = "\\esc_name "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, NetToSta) { std::string name = "net1"; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_EQ(result, "net1"); } TEST_F(VerilogTest, PortToSta) { std::string name = "port_a"; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_EQ(result, "port_a"); } @@ -165,7 +165,7 @@ TEST_F(VerilogTest, CellEscapePrefix) { // Verilog-to-STA conversions with escaped names TEST_F(VerilogTest, EscapedModuleToSta) { std::string name = "\\my/module "; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); // Should strip leading \ and trailing space, but escape special chars EXPECT_FALSE(result.empty()); EXPECT_NE(result.front(), '\\'); @@ -173,38 +173,38 @@ TEST_F(VerilogTest, EscapedModuleToSta) { TEST_F(VerilogTest, EscapedNetToSta) { std::string name = "\\net[0] "; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, EscapedPortToSta) { std::string name = "\\port/a "; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, PlainModuleToSta) { std::string name = "top_module"; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_EQ(result, "top_module"); } TEST_F(VerilogTest, PlainNetToSta) { std::string name = "wire1"; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_EQ(result, "wire1"); } TEST_F(VerilogTest, PlainPortToSta) { std::string name = "port_b"; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_EQ(result, "port_b"); } // Escaped name with brackets (bus notation) TEST_F(VerilogTest, EscapedInstanceWithBracket) { std::string name = "\\inst[0] "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // Brackets should be escaped in STA name EXPECT_NE(result.find("\\["), std::string::npos); @@ -213,7 +213,7 @@ TEST_F(VerilogTest, EscapedInstanceWithBracket) { // Escaped name with divider TEST_F(VerilogTest, EscapedInstanceWithDivider) { std::string name = "\\u1/u2 "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // Divider should be escaped in STA name EXPECT_NE(result.find("\\/"), std::string::npos); @@ -222,14 +222,14 @@ TEST_F(VerilogTest, EscapedInstanceWithDivider) { // Escaped name with escape character TEST_F(VerilogTest, EscapedNameWithEscapeChar) { std::string name = "\\esc\\val "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); } // Escaped name without trailing space TEST_F(VerilogTest, EscapedNoTrailingSpace) { std::string name = "\\esc_name"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); } @@ -303,7 +303,7 @@ TEST_F(VerilogTest, InstanceWithAt) { // verilogToSta: escaped name with multiple special chars TEST_F(VerilogTest, EscapedMultipleSpecial) { std::string name = "\\u1/u2[3] "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // Both / and [ and ] should be escaped EXPECT_NE(result.find("\\/"), std::string::npos); @@ -314,7 +314,7 @@ TEST_F(VerilogTest, EscapedMultipleSpecial) { // verilogToSta: escaped name with backslash inside TEST_F(VerilogTest, EscapedWithBackslash) { std::string name = "\\a\\b "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // The backslash inside should be escaped as \\ EXPECT_NE(result.find("\\\\"), std::string::npos); @@ -342,25 +342,25 @@ TEST_F(VerilogTest, CellDoubleBackslash) { // netVerilogToSta with plain name TEST_F(VerilogTest, NetToStaPlain) { std::string name = "simple_wire"; - EXPECT_EQ(netVerilogToSta(&name), "simple_wire"); + EXPECT_EQ(netVerilogToSta(name), "simple_wire"); } // portVerilogToSta with plain name TEST_F(VerilogTest, PortToStaPlain) { std::string name = "port_clk"; - EXPECT_EQ(portVerilogToSta(&name), "port_clk"); + EXPECT_EQ(portVerilogToSta(name), "port_clk"); } // moduleVerilogToSta plain TEST_F(VerilogTest, ModuleToStaPlain) { std::string name = "mod_top"; - EXPECT_EQ(moduleVerilogToSta(&name), "mod_top"); + EXPECT_EQ(moduleVerilogToSta(name), "mod_top"); } // verilogToSta: escaped name without trailing space TEST_F(VerilogTest, EscapedNoSpace) { std::string name = "\\name"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // "ame" (without leading 'n' because 'n' is first char after \ which is stripped) // Actually: ignoring leading '\', copy the rest. "name" has no trailing space. @@ -421,14 +421,14 @@ TEST_F(VerilogTest, InstanceWithBrackets) { // verilogToSta: empty escaped name TEST_F(VerilogTest, EmptyEscapedName) { std::string name = "\\"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_TRUE(result.empty()); } // verilogToSta: escaped name with only space TEST_F(VerilogTest, EscapedOnlySpace) { std::string name = "\\ "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_TRUE(result.empty()); } @@ -454,28 +454,28 @@ TEST_F(VerilogTest, CellOnlySpecialChars) { // instanceVerilogToSta: plain unescaped name TEST_F(VerilogTest, UnescapedInstance) { std::string name = "plain_inst"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_EQ(result, "plain_inst"); } // netVerilogToSta: escaped name with bus notation TEST_F(VerilogTest, EscapedNetBus) { std::string name = "\\data[7:0] "; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_FALSE(result.empty()); } // moduleVerilogToSta: escaped module name TEST_F(VerilogTest, EscapedModule) { std::string name = "\\mod/special "; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_FALSE(result.empty()); } // portVerilogToSta: escaped port name TEST_F(VerilogTest, EscapedPort) { std::string name = "\\port$gen "; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_FALSE(result.empty()); } @@ -521,7 +521,7 @@ TEST_F(VerilogTest, PortWithPlus) { // instanceVerilogToSta: escaped name with various special chars TEST_F(VerilogTest, EscapedInstanceComplex) { std::string name = "\\inst.a/b[c] "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); // The result should contain the original special characters in some form EXPECT_GT(result.size(), 3u); @@ -530,21 +530,21 @@ TEST_F(VerilogTest, EscapedInstanceComplex) { // netVerilogToSta: plain net with underscore TEST_F(VerilogTest, PlainNetUnderscore) { std::string name = "_net_wire_"; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_EQ(result, "_net_wire_"); } // portVerilogToSta: plain port with numbers TEST_F(VerilogTest, PlainPortNumeric) { std::string name = "port_123"; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_EQ(result, "port_123"); } // moduleVerilogToSta: plain module with mixed case TEST_F(VerilogTest, PlainModuleMixedCase) { std::string name = "MyModule_V2"; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_EQ(result, "MyModule_V2"); } @@ -575,14 +575,14 @@ TEST_F(VerilogTest, PortWithPipe) { // instanceVerilogToSta: escaped name without trailing space (edge case) TEST_F(VerilogTest, EscapedNoTrailingSpaceComplex) { std::string name = "\\inst/a[0]"; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); } // cellVerilogName: very long name TEST_F(VerilogTest, CellLongName) { std::string long_name(200, 'a'); - std::string result = cellVerilogName(long_name.c_str()); + std::string result = cellVerilogName(long_name); EXPECT_EQ(result, long_name); } @@ -590,7 +590,7 @@ TEST_F(VerilogTest, CellLongName) { TEST_F(VerilogTest, CellLongEscapedName) { std::string long_name(200, 'a'); long_name[100] = '/'; - std::string result = cellVerilogName(long_name.c_str()); + std::string result = cellVerilogName(long_name); EXPECT_EQ(result.front(), '\\'); EXPECT_EQ(result.back(), ' '); } @@ -1014,21 +1014,21 @@ TEST_F(VerilogTest, InstanceWithLessThan) { // VerilogToSta: net with bus range TEST_F(VerilogTest, EscapedNetRange) { std::string name = "\\data[7:0] "; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_FALSE(result.empty()); } // VerilogToSta: module with digit prefix TEST_F(VerilogTest, ModuleDigitPrefix) { std::string name = "123module"; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_EQ(result, "123module"); } // portVerilogToSta: escaped TEST_F(VerilogTest, EscapedPortComplex) { std::string name = "\\port.a[0]/b "; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_FALSE(result.empty()); } @@ -1036,7 +1036,7 @@ TEST_F(VerilogTest, EscapedPortComplex) { TEST_F(VerilogTest, RoundTripSpecialCell) { // STA name with escaped bracket std::string sta_name = "cell\\[0\\]"; - std::string verilog = cellVerilogName(sta_name.c_str()); + std::string verilog = cellVerilogName(sta_name); EXPECT_FALSE(verilog.empty()); } @@ -1427,25 +1427,25 @@ TEST_F(VerilogTest, PortNameWithBacktick) { // Verilog to STA conversions: edge cases TEST_F(VerilogTest, EscapedInstanceOnlyBrackets) { std::string name = "\\[0] "; - std::string result = instanceVerilogToSta(&name); + std::string result = instanceVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, EscapedNetOnlySlash) { std::string name = "\\/ "; - std::string result = netVerilogToSta(&name); + std::string result = netVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, ModuleToStaEscapedComplex) { std::string name = "\\mod.a/b[1] "; - std::string result = moduleVerilogToSta(&name); + std::string result = moduleVerilogToSta(name); EXPECT_FALSE(result.empty()); } TEST_F(VerilogTest, PortToStaEscapedBracket) { std::string name = "\\port[3] "; - std::string result = portVerilogToSta(&name); + std::string result = portVerilogToSta(name); EXPECT_FALSE(result.empty()); } @@ -1727,35 +1727,35 @@ TEST_F(VerilogTest, PortNameMixedSpecial) { // Round-trip tests: staToVerilog -> verilogToSta should preserve identity for simple names TEST_F(VerilogTest, RoundTripSimpleName) { std::string sta_name = "simple_wire"; - std::string verilog = netVerilogName(sta_name.c_str()); - std::string back = netVerilogToSta(&verilog); + std::string verilog = netVerilogName(sta_name); + std::string back = netVerilogToSta(verilog); EXPECT_EQ(back, sta_name); } TEST_F(VerilogTest, RoundTripSimpleCell) { std::string sta_name = "my_cell_123"; - std::string verilog = cellVerilogName(sta_name.c_str()); + std::string verilog = cellVerilogName(sta_name); EXPECT_EQ(verilog, sta_name); // no escaping needed } TEST_F(VerilogTest, RoundTripSimpleInstance) { std::string sta_name = "u1_abc"; - std::string verilog = instanceVerilogName(sta_name.c_str()); - std::string back = instanceVerilogToSta(&verilog); + std::string verilog = instanceVerilogName(sta_name); + std::string back = instanceVerilogToSta(verilog); EXPECT_EQ(back, sta_name); } TEST_F(VerilogTest, RoundTripSimplePort) { std::string sta_name = "clk_in"; - std::string verilog = portVerilogName(sta_name.c_str()); - std::string back = portVerilogToSta(&verilog); + std::string verilog = portVerilogName(sta_name); + std::string back = portVerilogToSta(verilog); EXPECT_EQ(back, sta_name); } TEST_F(VerilogTest, RoundTripSimpleModule) { std::string sta_name = "top_module"; - std::string verilog = cellVerilogName(sta_name.c_str()); - std::string back = moduleVerilogToSta(&verilog); + std::string verilog = cellVerilogName(sta_name); + std::string back = moduleVerilogToSta(verilog); EXPECT_EQ(back, sta_name); } @@ -1802,7 +1802,7 @@ TEST_F(VerilogTest, DclBusPortName) { TEST_F(VerilogTest, NetBusRangeConversion) { // Verilog bus notation should convert properly std::string verilog_name = "data[3]"; - std::string net_name = netVerilogToSta(&verilog_name); + std::string net_name = netVerilogToSta(verilog_name); EXPECT_FALSE(net_name.empty()); } @@ -1838,7 +1838,7 @@ TEST_F(VerilogTest, EmptyNames) { // Covers: netVerilogToSta with bus notation TEST_F(VerilogTest, BusVerilogToSta) { std::string verilog_name = "bus[7:0]"; - std::string bus = netVerilogToSta(&verilog_name); + std::string bus = netVerilogToSta(verilog_name); EXPECT_FALSE(bus.empty()); } @@ -1846,7 +1846,7 @@ TEST_F(VerilogTest, BusVerilogToSta) { // Covers: instanceVerilogToSta with escaped name TEST_F(VerilogTest, EscapedInstanceToSta) { std::string verilog_name = "\\inst[0] "; - std::string name = instanceVerilogToSta(&verilog_name); + std::string name = instanceVerilogToSta(verilog_name); EXPECT_FALSE(name.empty()); } @@ -1854,10 +1854,10 @@ TEST_F(VerilogTest, EscapedInstanceToSta) { // Covers: netVerilogToSta bracket handling TEST_F(VerilogTest, NetVerilogToStaBrackets) { std::string name1 = "wire1"; - std::string net1 = netVerilogToSta(&name1); + std::string net1 = netVerilogToSta(name1); EXPECT_EQ(net1, "wire1"); std::string name2 = "bus[0]"; - std::string net2 = netVerilogToSta(&name2); + std::string net2 = netVerilogToSta(name2); EXPECT_FALSE(net2.empty()); } @@ -1893,7 +1893,7 @@ TEST_F(VerilogTest, PortHierSep) { // Covers: instanceVerilogToSta simple case TEST_F(VerilogTest, InstanceToStaSimple) { std::string verilog_name = "u1"; - std::string name = instanceVerilogToSta(&verilog_name); + std::string name = instanceVerilogToSta(verilog_name); EXPECT_EQ(name, "u1"); } From 3ec34c571e1a3d50fcdba42aec5993e351e1d307 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 24 Mar 2026 10:21:44 -0700 Subject: [PATCH 07/22] Only install fmt if std::format is not available Signed-off-by: James Cherry --- CMakeLists.txt | 52 ++++++++++++++++++++++++++++++++++-------- Dockerfile.centos7 | 24 +++++++++++++++++++ Dockerfile.ubuntu22.04 | 5 ++-- README.md | 6 +++++ 4 files changed, 75 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3c6ab462..db29b2af 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -403,15 +403,44 @@ find_package(Threads) find_package(Eigen3 REQUIRED) -# fmt library: fallback when std::format is not available (e.g. GCC 11 on Ubuntu 22.04) -find_package(fmt QUIET) -if(NOT fmt_FOUND) - include(FetchContent) - FetchContent_Declare(fmt - GIT_REPOSITORY https://github.com/fmtlib/fmt.git - GIT_TAG 10.2.1 - ) - FetchContent_MakeAvailable(fmt) +# See if std::format is available and if nor install fmt. +include(CheckCXXSourceCompiles) +set(_sta_fmt_check_saved_flags "${CMAKE_REQUIRED_FLAGS}") +if(MSVC) + string(APPEND CMAKE_REQUIRED_FLAGS " /std:c++20") +else() + string(APPEND CMAKE_REQUIRED_FLAGS " -std=c++20") +endif() +check_cxx_source_compiles(" +#include +#include +int main() { (void)std::format(\"{}\", 42); return 0; } +" HAVE_CXX_STD_FORMAT) +set(CMAKE_REQUIRED_FLAGS "${_sta_fmt_check_saved_flags}") + +if(HAVE_CXX_STD_FORMAT) + message(STATUS "std::format: available") +else() + # Set the fmt dir for the ubuntu/centos docker files. + if(EXISTS "/usr/local/lib/cmake/fmt/fmt-config.cmake") + set(fmt_DIR "/usr/local/lib/cmake/fmt") + elseif(EXISTS "/usr/lib/x86_64-linux-gnu/cmake/fmt/fmt-config.cmake") + set(fmt_DIR "/usr/lib/x86_64-linux-gnu/cmake/fmt") + elseif(EXISTS "/usr/lib/aarch64-linux-gnu/cmake/fmt/fmt-config.cmake") + set(fmt_DIR "/usr/lib/aarch64-linux-gnu/cmake/fmt") + endif() + find_package(fmt QUIET) + if(fmt_FOUND) + message(STATUS "std::format: using installed fmt library") + else() + message(STATUS "std::format: building fmt library") + include(FetchContent) + FetchContent_Declare(fmt + GIT_REPOSITORY https://github.com/fmtlib/fmt.git + GIT_TAG 10.2.1 + ) + FetchContent_MakeAvailable(fmt) + endif() endif() include(cmake/FindCUDD.cmake) @@ -529,12 +558,15 @@ target_sources(OpenSTA target_link_libraries(OpenSTA Eigen3::Eigen - fmt::fmt ${TCL_LIBRARY} ${CMAKE_THREAD_LIBS_INIT} ${CUDD_LIB} ) +if(NOT HAVE_CXX_STD_FORMAT) + target_link_libraries(OpenSTA fmt::fmt) +endif() + if (ZLIB_LIBRARIES) target_link_libraries(OpenSTA ${ZLIB_LIBRARIES}) endif() diff --git a/Dockerfile.centos7 b/Dockerfile.centos7 index cdcd6037..458d0dbc 100644 --- a/Dockerfile.centos7 +++ b/Dockerfile.centos7 @@ -53,6 +53,30 @@ RUN source /opt/rh/devtoolset-11/enable && \ make -j`nproc` && \ make install +# Download and build fmt +# Ensure the Vault redirect is applied to everything including new installs +RUN sed -i s/mirror.centos.org/vault.centos.org/g /etc/yum.repos.d/*.repo && \ + sed -i s/^#.*baseurl=http/baseurl=http/g /etc/yum.repos.d/*.repo && \ + sed -i s/^mirrorlist=http/#mirrorlist=http/g /etc/yum.repos.d/*.repo && \ + yum install -y ca-certificates git && \ + update-ca-trust force-enable +# clone fmt compatible version (10.2.1) +RUN git config --global http.sslVerify false && \ + git clone --depth 1 --branch 10.2.1 https://github.com/fmtlib/fmt.git /tmp/fmt +RUN source /opt/rh/devtoolset-11/enable && \ + cd /tmp/fmt && \ + mkdir build && cd build && \ + cmake3 .. \ + -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + -DFMT_TEST=OFF \ + -DCMAKE_BUILD_TYPE=Release \ + -DFMT_DOC=OFF && \ + make -j$(nproc) && \ + make install +RUN rm -rf /tmp/fmt + +################################################################ + FROM base-dependencies AS builder COPY . /OpenSTA diff --git a/Dockerfile.ubuntu22.04 b/Dockerfile.ubuntu22.04 index e636fc21..b8c94ca4 100644 --- a/Dockerfile.ubuntu22.04 +++ b/Dockerfile.ubuntu22.04 @@ -13,12 +13,13 @@ RUN apt-get update && \ gdb \ tcl-dev \ tcl-tclreadline \ - libeigen3-dev \ swig \ bison \ flex \ automake \ - autotools-dev + autotools-dev \ + libeigen3-dev \ + libfmt-dev # Download CUDD RUN wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cudd-3.0.0.tar.gz && \ diff --git a/README.md b/README.md index 8323cf74..e30b1051 100644 --- a/README.md +++ b/README.md @@ -104,6 +104,7 @@ eigen 3.4.0 3.4.0 MPL2 required cudd 3.0.0 3.0.0 BSD required tclreadline 2.3.8 2.3.8 BSD optional zLib 1.2.5 1.2.8 zlib optional +libfmt 8.1.1 N/A MIT required if std::format not available ``` The [TCL readline library](https://tclreadline.sourceforge.net/tclreadline.html) @@ -143,6 +144,11 @@ make You can use the "configure --prefix" option and "make install" to install CUDD in a different directory. +Modern c++ compilers that support c++20 include support for std::format. +With older compilers like gcc 11 on Ubuntu 22.04 and Centos7 the fmt library +is used instead. If it is not installed locally, the github repository is +downloaded and compiled in the build directory. + ### Building with CMake Use the following commands to checkout the git repository and build the From f4048cdf3efed83ccdfd79db3391a4e49df75593 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 24 Mar 2026 10:31:24 -0700 Subject: [PATCH 08/22] read_saif ref missing instance resolves #406 Signed-off-by: James Cherry --- power/SaifReader.cc | 4 +++- test/read_saif_null_instance.lib | 14 ++++++++++++++ test/read_saif_null_instance.ok | 1 + test/read_saif_null_instance.saif | 16 ++++++++++++++++ test/read_saif_null_instance.tcl | 5 +++++ test/read_saif_null_instance.v | 2 ++ test/regression_vars.tcl | 1 + 7 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 test/read_saif_null_instance.lib create mode 100644 test/read_saif_null_instance.ok create mode 100644 test/read_saif_null_instance.saif create mode 100644 test/read_saif_null_instance.tcl create mode 100644 test/read_saif_null_instance.v diff --git a/power/SaifReader.cc b/power/SaifReader.cc index c06cb512..72a35926 100644 --- a/power/SaifReader.cc +++ b/power/SaifReader.cc @@ -139,7 +139,9 @@ SaifReader::instancePush(const char *instance_name) else { // Inside annotation scope. Instance *parent = path_.empty() ? sdc_network_->topInstance() : path_.back(); - Instance *child = sdc_network_->findChild(parent, instance_name); + Instance *child = parent + ? sdc_network_->findChild(parent, instance_name) + : nullptr; path_.push_back(child); } stringDelete(instance_name); diff --git a/test/read_saif_null_instance.lib b/test/read_saif_null_instance.lib new file mode 100644 index 00000000..da8ae595 --- /dev/null +++ b/test/read_saif_null_instance.lib @@ -0,0 +1,14 @@ +library(min) { + technology(cmos); + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1mA"; + capacitive_load_unit(1, pf); + cell(BUF) { + pin(A) { direction : input; } + pin(Y) { direction : output; + function : "A"; + timing() { related_pin : "A"; } + } + } +} diff --git a/test/read_saif_null_instance.ok b/test/read_saif_null_instance.ok new file mode 100644 index 00000000..42f6c7a4 --- /dev/null +++ b/test/read_saif_null_instance.ok @@ -0,0 +1 @@ +Annotated 0 pin activities. diff --git a/test/read_saif_null_instance.saif b/test/read_saif_null_instance.saif new file mode 100644 index 00000000..dcaff257 --- /dev/null +++ b/test/read_saif_null_instance.saif @@ -0,0 +1,16 @@ +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(DIVIDER / ) +(TIMESCALE 1ns) +(DURATION 1000) + (INSTANCE TOP + (INSTANCE child + (INSTANCE grandchild + (NET + (clk (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 1000)) + ) + ) + ) + ) +) diff --git a/test/read_saif_null_instance.tcl b/test/read_saif_null_instance.tcl new file mode 100644 index 00000000..59f4d5a3 --- /dev/null +++ b/test/read_saif_null_instance.tcl @@ -0,0 +1,5 @@ +# read_saif references missing instance +read_liberty read_saif_null_instance.lib +read_verilog read_saif_null_instance.v +link_design top +read_saif -scope TOP read_saif_null_instance.saif diff --git a/test/read_saif_null_instance.v b/test/read_saif_null_instance.v new file mode 100644 index 00000000..2f1a84ac --- /dev/null +++ b/test/read_saif_null_instance.v @@ -0,0 +1,2 @@ +module top(input clk); +endmodule diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index edc16ee0..9b6af334 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -158,6 +158,7 @@ record_public_tests { path_group_names power_json prima3 + read_saif_null_instance report_checks_sorted report_checks_src_attr report_json1 From c38762185c8fe66d1e2016e3ddcb3c062642d587 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 24 Mar 2026 12:22:20 -0700 Subject: [PATCH 09/22] StaConfig.hh pass HAVE_CXX_STD_FORMAT Signed-off-by: James Cherry --- include/sta/Format.hh | 5 +---- util/StaConfig.hh.cmake | 2 ++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/sta/Format.hh b/include/sta/Format.hh index 1745f482..88555a1e 100644 --- a/include/sta/Format.hh +++ b/include/sta/Format.hh @@ -35,10 +35,7 @@ #include #endif -// std::format is not supported in GCC 11 (e.g. Ubuntu 22.04). -// Use fmt library as fallback when __cpp_lib_format is not defined. - -#if defined(__cpp_lib_format) && __cpp_lib_format >= 201907L +#if HAVE_CXX_STD_FORMAT #include namespace sta { diff --git a/util/StaConfig.hh.cmake b/util/StaConfig.hh.cmake index 2efd9720..daf90b36 100644 --- a/util/StaConfig.hh.cmake +++ b/util/StaConfig.hh.cmake @@ -6,4 +6,6 @@ #cmakedefine ZLIB_FOUND +#cmakedefine01 HAVE_CXX_STD_FORMAT + #define TCL_READLINE ${TCL_READLINE} From d233581e167e72a332024ba9181361f791f9fcdb Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 25 Mar 2026 08:35:18 +1300 Subject: [PATCH 10/22] Make `wire_load_tree_` default to unknown so we can detect when it's not present in a Liberty file. (#402) This is potentially a behavior change, but I think omitting this is rare. I've only seen it in some DTCD Liberty files. In those Liberty libraries, it seems to be expected that the Liberty data is valid for all `WireloadTree` types. Thus it is necessary to distinguish between "wire load tree was specified as 'balanced'" and "wire load tree was not specified". --- liberty/Liberty.cc | 2 +- parasitics/Parasitics.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 5e4328ad..17d0b464 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -3042,7 +3042,7 @@ OperatingConditions::OperatingConditions(const char *name) : Pvt(0.0, 0.0, 0.0), name_(name), // Default wireload tree. - wire_load_tree_(WireloadTree::balanced) + wire_load_tree_(WireloadTree::unknown) { } diff --git a/parasitics/Parasitics.cc b/parasitics/Parasitics.cc index ab304bda..69187f95 100644 --- a/parasitics/Parasitics.cc +++ b/parasitics/Parasitics.cc @@ -257,12 +257,12 @@ Parasitics::makeWireloadNetwork(const Pin *drvr_pin, makeWireloadNetworkWorst(parasitic, drvr_pin, net, wireload_cap, wireload_res, fanout); break; + case WireloadTree::unknown: case WireloadTree::balanced: makeWireloadNetworkBalanced(parasitic, drvr_pin, wireload_cap, wireload_res, fanout); break; case WireloadTree::best_case: - case WireloadTree::unknown: makeWireloadNetworkBest(parasitic, drvr_pin, wireload_cap, wireload_res, fanout); break; From b9e439f41c1d3c8b5165378c36bf310f279115ee Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 24 Mar 2026 18:42:47 -0700 Subject: [PATCH 11/22] delay calc clip delay to 0.0 resolves #405 Signed-off-by: James Cherry --- dcalc/DmpCeff.cc | 14 +++++++------- dcalc/GraphDelayCalc.cc | 34 +++++++++++++++++----------------- liberty/TableModel.cc | 4 +++- 3 files changed, 27 insertions(+), 25 deletions(-) diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index 38c04648..1cccadaf 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -448,10 +448,10 @@ DmpAlg::showJacobian() { std::string line = " "; for (int j = 0; j < nr_order_; j++) - line += sta::format("{:12}", dmp_param_index_strings[j]); + line += sta::format("{:>12}", dmp_param_index_strings[j]); report_->reportLine(line); - line.clear(); for (int i = 0; i < nr_order_; i++) { + line.clear(); line += sta::format("{:4} ", dmp_func_index_strings[i]); for (int j = 0; j < nr_order_; j++) line += sta::format("{:12.3e} ", fjac_[i][j]); @@ -551,10 +551,10 @@ DmpAlg::loadDelaySlew(const Pin *, // Use the driver thresholds and rely on thresholdAdjust to // convert the delay and slew to the load's thresholds. try { - if (debug_->check("dmp_ceff", 4)) - showVl(); elmore_ = elmore; p3_ = 1.0 / elmore; + if (debug_->check("dmp_ceff", 4)) + showVl(); double t_lower = t0_; double t_upper = vlCrossingUpperBound(); double load_delay = findVlCrossing(vth_, t_lower, t_upper); @@ -1189,9 +1189,9 @@ DmpZeroC2::init(const LibertyLibrary *drvr_library, } void -DmpZeroC2::gateDelaySlew( // Return values. - double &delay, - double &slew) +DmpZeroC2::gateDelaySlew(// Return values. + double &delay, + double &slew) { try { findDriverParams(c1_); diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index 8c12cdf1..9c95ed1b 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -411,27 +411,27 @@ GraphDelayCalc::seedDrvrSlew(Vertex *drvr_vertex, for (const MinMax *min_max : MinMax::range()) { for (const RiseFall *rf : RiseFall::range()) { InputDrive *drive = nullptr; - if (network_->isTopLevelPort(drvr_pin)) { - Port *port = network_->port(drvr_pin); + if (network_->isTopLevelPort(drvr_pin)) { + Port *port = network_->port(drvr_pin); drive = sdc->findInputDrive(port); - } - if (drive) { - const LibertyCell *drvr_cell; - const LibertyPort *from_port, *to_port; - float *from_slews; + } + if (drive) { + const LibertyCell *drvr_cell; + const LibertyPort *from_port, *to_port; + float *from_slews; drive->driveCell(rf, min_max, drvr_cell, from_port, - from_slews, to_port); - if (drvr_cell) { - if (from_port == nullptr) - from_port = driveCellDefaultFromPort(drvr_cell, to_port); - findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, rf, + from_slews, to_port); + if (drvr_cell) { + if (from_port == nullptr) + from_port = driveCellDefaultFromPort(drvr_cell, to_port); + findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, rf, from_port, from_slews, to_port, scene, min_max); - } - else + } + else seedNoDrvrCellSlew(drvr_vertex, drvr_pin, rf, drive, scene, min_max, - arc_delay_calc); - } - else + arc_delay_calc); + } + else seedNoDrvrSlew(drvr_vertex, drvr_pin, rf, scene, min_max, arc_delay_calc); } } diff --git a/liberty/TableModel.cc b/liberty/TableModel.cc index 46dd6d6b..c3e8856f 100644 --- a/liberty/TableModel.cc +++ b/liberty/TableModel.cc @@ -116,7 +116,9 @@ GateTableModel::gateDelay(const Pvt *pvt, drvr_slew = findValue(pvt, slew_models_->model(), in_slew, load_cap, 0.0); else drvr_slew = 0.0; - // Clip negative slews to zero. + // Clip negative delays and slews to zero. + if (gate_delay < 0.0) + gate_delay = 0.0; if (drvr_slew < 0.0) drvr_slew = 0.0; } From 3d5f1e85942bde5401f9281955afbc611f27f44c Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Mar 2026 14:48:15 +0000 Subject: [PATCH 12/22] fix warnings Signed-off-by: dsengupta0628 --- liberty/test/cpp/TestLibertyClasses.cc | 8 ++++---- network/test/cpp/TestNetwork.cc | 1 - parasitics/test/cpp/TestParasitics.cc | 2 -- sdc/test/cpp/TestSdcClasses.cc | 2 -- spice/test/cpp/TestSpice.cc | 9 ++++++--- verilog/test/cpp/TestVerilog.cc | 2 +- 6 files changed, 11 insertions(+), 13 deletions(-) diff --git a/liberty/test/cpp/TestLibertyClasses.cc b/liberty/test/cpp/TestLibertyClasses.cc index 60470e17..70868898 100644 --- a/liberty/test/cpp/TestLibertyClasses.cc +++ b/liberty/test/cpp/TestLibertyClasses.cc @@ -1993,8 +1993,6 @@ TEST_F(LinearModelTest, Table3ReportValue) { TEST_F(LinearModelTest, TableModelReport) { TablePtr tbl = std::make_shared
(42.0f); TableModel model(tbl, nullptr, ScaleFactorType::cell, RiseFall::rise()); - const Units *units = lib_->units(); - Report *report_obj = nullptr; // report needs Report*; test order/axes instead EXPECT_EQ(model.order(), 0); EXPECT_EQ(model.axis1(), nullptr); @@ -3285,8 +3283,9 @@ TEST(TestCellTest, FootprintDefault) { TestCell cell(&lib, "CELL1", "test.lib"); const char *fp = cell.footprint(); // Empty string or nullptr for default - if (fp) + if (fp) { EXPECT_EQ(fp, ""); + } } TEST(TestCellTest, SetFootprint) { @@ -3300,8 +3299,9 @@ TEST(TestCellTest, UserFunctionClassDefault) { LibertyLibrary lib("test_lib", "test.lib"); TestCell cell(&lib, "CELL1", "test.lib"); const char *ufc = cell.userFunctionClass(); - if (ufc) + if (ufc) { EXPECT_EQ(ufc, ""); + } } TEST(TestCellTest, SetUserFunctionClass) { diff --git a/network/test/cpp/TestNetwork.cc b/network/test/cpp/TestNetwork.cc index 7ccfbfdb..1d9cd15b 100644 --- a/network/test/cpp/TestNetwork.cc +++ b/network/test/cpp/TestNetwork.cc @@ -1141,7 +1141,6 @@ TEST(ConcreteNetworkTest, FindCellViaNetwork) { TEST(ConcreteNetworkTest, FindAnyCell) { ConcreteNetwork network; Library *lib1 = network.makeLibrary("lib1", "lib1.lib"); - Library *lib2 = network.makeLibrary("lib2", "lib2.lib"); network.makeCell(lib1, "INV_X1", true, "lib1.lib"); Cell *found = network.findAnyCell("INV_X1"); EXPECT_NE(found, nullptr); diff --git a/parasitics/test/cpp/TestParasitics.cc b/parasitics/test/cpp/TestParasitics.cc index 6583aa47..eddb6967 100644 --- a/parasitics/test/cpp/TestParasitics.cc +++ b/parasitics/test/cpp/TestParasitics.cc @@ -1304,7 +1304,6 @@ TEST_F(StaParasiticsTest, ParasiticNodeResistorMap) { // Test findNode (deprecated) - delegates to findParasiticNode TEST_F(StaParasiticsTest, FindNodeDeprecated) { ASSERT_NO_THROW(( [&](){ - Parasitics *parasitics = sta_->findParasitics("default"); ConcretePiElmore pe(1e-12f, 100.0f, 2e-12f); // findNode on non-network parasitic should work but return nullptr // since it's not a parasitic network @@ -1317,7 +1316,6 @@ TEST_F(StaParasiticsTest, FindNodeDeprecated) { // Test unannotatedLoads through parasitics API with PiElmore TEST_F(StaParasiticsTest, UnannotatedLoadsPiElmore) { ASSERT_NO_THROW(( [&](){ - Parasitics *parasitics = sta_->findParasitics("default"); ConcretePiElmore pe(1e-12f, 100.0f, 2e-12f); // With no network loads, should just return what parasitics->loads returns // which needs a connected pin. With nullptr pin, this will likely crash diff --git a/sdc/test/cpp/TestSdcClasses.cc b/sdc/test/cpp/TestSdcClasses.cc index 7b8f1c6c..b93185cf 100644 --- a/sdc/test/cpp/TestSdcClasses.cc +++ b/sdc/test/cpp/TestSdcClasses.cc @@ -3542,8 +3542,6 @@ TEST_F(SdcInitTest, DisabledPortsSetAll) { // PortExtCap: operations (needs Port* constructor) TEST_F(SdcInitTest, PortExtCapSetGet) { - // Need a port to construct PortExtCap - Network *network = sta_->cmdNetwork(); // PortExtCap default constructor PortExtCap pec; pec.setPinCap(nullptr, 0.1f, RiseFall::rise(), MinMax::max()); diff --git a/spice/test/cpp/TestSpice.cc b/spice/test/cpp/TestSpice.cc index 7899fda9..8504d28a 100644 --- a/spice/test/cpp/TestSpice.cc +++ b/spice/test/cpp/TestSpice.cc @@ -1302,8 +1302,12 @@ TEST_F(SpiceSmokeTest, RiseFallRangeValues) { auto range = RiseFall::range(); int idx = 0; for (auto rf : range) { - if (idx == 0) EXPECT_EQ(rf, RiseFall::rise()); - if (idx == 1) EXPECT_EQ(rf, RiseFall::fall()); + if (idx == 0) { + EXPECT_EQ(rf, RiseFall::rise()); + } + if (idx == 1) { + EXPECT_EQ(rf, RiseFall::fall()); + } idx++; } EXPECT_EQ(idx, 2); @@ -1554,7 +1558,6 @@ TEST_F(SpiceDesignTest, LibertyCellTimingArcs) { // Verify pin connectivity for SPICE net writing TEST_F(SpiceDesignTest, PinConnectivity) { Network *network = sta_->cmdNetwork(); - Instance *top = network->topInstance(); // The internal net n1 connects and1:ZN to buf1:A Pin *and1_zn = network->findPin("and1/ZN"); diff --git a/verilog/test/cpp/TestVerilog.cc b/verilog/test/cpp/TestVerilog.cc index cd959339..bac2ef32 100644 --- a/verilog/test/cpp/TestVerilog.cc +++ b/verilog/test/cpp/TestVerilog.cc @@ -316,7 +316,7 @@ TEST_F(VerilogTest, EscapedWithBackslash) { std::string name = "\\a\\b "; std::string result = instanceVerilogToSta(&name); EXPECT_FALSE(result.empty()); - // The backslash inside should be escaped as \\ + // The backslash inside should be escaped as double-backslash EXPECT_NE(result.find("\\\\"), std::string::npos); } From 2910df0b18bca951beff79ecfd6e9ad688e20f16 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Mar 2026 16:06:38 +0000 Subject: [PATCH 13/22] cleanup#2 Signed-off-by: dsengupta0628 --- power/test/cpp/TestPower.cc | 1 - sdc/test/cpp/TestSdcClasses.cc | 25 ------------------------- 2 files changed, 26 deletions(-) diff --git a/power/test/cpp/TestPower.cc b/power/test/cpp/TestPower.cc index 9db5b340..6ecedbb8 100644 --- a/power/test/cpp/TestPower.cc +++ b/power/test/cpp/TestPower.cc @@ -769,7 +769,6 @@ TEST_F(PowerDesignTest, PowerPerInstance) { int count = 0; while (child_iter->hasNext() && count < 5) { Instance *inst = child_iter->next(); - PowerResult result = sta_->power(inst, corner); count++; } delete child_iter; diff --git a/sdc/test/cpp/TestSdcClasses.cc b/sdc/test/cpp/TestSdcClasses.cc index b93185cf..b7378488 100644 --- a/sdc/test/cpp/TestSdcClasses.cc +++ b/sdc/test/cpp/TestSdcClasses.cc @@ -35,31 +35,6 @@ namespace sta { -static std::string -readTextFile(const char *filename) -{ - std::ifstream in(filename); - if (!in.is_open()) - return ""; - return std::string((std::istreambuf_iterator(in)), - std::istreambuf_iterator()); -} - -static size_t -countSubstring(const std::string &text, - const std::string &needle) -{ - if (needle.empty()) - return 0; - size_t count = 0; - size_t pos = 0; - while ((pos = text.find(needle, pos)) != std::string::npos) { - ++count; - pos += needle.size(); - } - return count; -} - // RiseFall tests class RiseFallTest : public ::testing::Test {}; From 9359303763e80a3628cc3ee61f9f96679d9d6739 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Mar 2026 18:15:30 +0000 Subject: [PATCH 14/22] cleanup more Signed-off-by: dsengupta0628 --- power/test/cpp/TestPower.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/power/test/cpp/TestPower.cc b/power/test/cpp/TestPower.cc index 6ecedbb8..c1f5bdab 100644 --- a/power/test/cpp/TestPower.cc +++ b/power/test/cpp/TestPower.cc @@ -768,7 +768,7 @@ TEST_F(PowerDesignTest, PowerPerInstance) { InstanceChildIterator *child_iter = network->childIterator(top); int count = 0; while (child_iter->hasNext() && count < 5) { - Instance *inst = child_iter->next(); + child_iter->next(); count++; } delete child_iter; From 35aef386d652ae71c1314ce39886c4cff9411967 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Wed, 25 Mar 2026 21:09:35 +0000 Subject: [PATCH 15/22] excercise the power func in sta test Signed-off-by: dsengupta0628 --- power/test/cpp/TestPower.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/power/test/cpp/TestPower.cc b/power/test/cpp/TestPower.cc index c1f5bdab..2c37eb01 100644 --- a/power/test/cpp/TestPower.cc +++ b/power/test/cpp/TestPower.cc @@ -768,7 +768,7 @@ TEST_F(PowerDesignTest, PowerPerInstance) { InstanceChildIterator *child_iter = network->childIterator(top); int count = 0; while (child_iter->hasNext() && count < 5) { - child_iter->next(); + sta_->power(child_iter->next(), corner); count++; } delete child_iter; From 17febe2c48646c26d9fef7a80e524d48ef82ed45 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Thu, 26 Mar 2026 00:38:13 +0000 Subject: [PATCH 16/22] update sta code to accomodate LVF and write_spice changes latest on 3/25 Signed-off-by: dsengupta0628 --- CMakeLists.txt | 2 +- spice/test/spice_write.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 178ee1a9..88c37cc2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -444,7 +444,7 @@ else() include(FetchContent) FetchContent_Declare(fmt GIT_REPOSITORY https://github.com/fmtlib/fmt.git - GIT_TAG 10.2.1 + GIT_TAG 11.0.2 ) FetchContent_MakeAvailable(fmt) endif() diff --git a/spice/test/spice_write.tcl b/spice/test/spice_write.tcl index e9712268..486e064d 100644 --- a/spice/test/spice_write.tcl +++ b/spice/test/spice_write.tcl @@ -42,7 +42,7 @@ close $subckt_fh # C++ WritePathSpice code paths. write_path_spice \ -path_args {-sort_by_slack} \ - -spice_directory $spice_dir \ + -spice_file [file join $spice_dir path] \ -lib_subckt_file $subckt_file \ -model_file $model_file \ -power VDD \ From cb8851ef57e289016a12b0cfbd89028d7fcb7c3e Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Thu, 26 Mar 2026 14:35:25 +0000 Subject: [PATCH 17/22] Do not clip negative delays just yet- needs more debug Signed-off-by: dsengupta0628 --- liberty/TableModel.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/liberty/TableModel.cc b/liberty/TableModel.cc index c3e8856f..3bda98e3 100644 --- a/liberty/TableModel.cc +++ b/liberty/TableModel.cc @@ -116,9 +116,9 @@ GateTableModel::gateDelay(const Pvt *pvt, drvr_slew = findValue(pvt, slew_models_->model(), in_slew, load_cap, 0.0); else drvr_slew = 0.0; - // Clip negative delays and slews to zero. - if (gate_delay < 0.0) - gate_delay = 0.0; + // TODO: Check for a better solution than clip negative delays and slews to zero. + //if (gate_delay < 0.0) + // gate_delay = 0.0; if (drvr_slew < 0.0) drvr_slew = 0.0; } From df00dcd22438374bcf49321346cbae0d5bfd7f4b Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Thu, 26 Mar 2026 21:11:47 +0000 Subject: [PATCH 18/22] update for succesful bazel build Signed-off-by: dsengupta0628 --- BUILD | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/BUILD b/BUILD index 44f0c0e1..dc3b7498 100644 --- a/BUILD +++ b/BUILD @@ -183,7 +183,8 @@ genrule( #define STA_VERSION "2.7.0" #define STA_GIT_SHA1 "f21d4a3878e2531e3af4930818d9b5968aad9416" #define SSTA 0 - #define ZLIB_FOUND' > \"$@\" + #define ZLIB_FOUND + #define HAVE_CXX_STD_FORMAT 1' > \"$@\" """, visibility = ["//:__subpackages__"], ) From 616280e2f710ad5617d2c210e44f967f164b776f Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Fri, 27 Mar 2026 01:10:10 +0000 Subject: [PATCH 19/22] fix LibertyParser warnings Signed-off-by: dsengupta0628 --- liberty/LibertyParser.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/liberty/LibertyParser.cc b/liberty/LibertyParser.cc index b3cefe9a..11a3d05a 100644 --- a/liberty/LibertyParser.cc +++ b/liberty/LibertyParser.cc @@ -79,7 +79,7 @@ LibertyParser::makeDefine(const LibertyAttrValueSeq *values, const std::string &value_type_name = (*values)[2]->stringValue(); LibertyAttrType value_type = attrValueType(value_type_name); LibertyGroupType group_type = groupType(group_type_name); - define = new LibertyDefine(std::move(define_name), group_type, value_type, line); + define = new LibertyDefine(define_name, group_type, value_type, line); LibertyGroup *group = this->group(); group->addDefine(define); for (auto value : *values) @@ -168,7 +168,7 @@ LibertyParser::makeSimpleAttr(const std::string name, int line) { LibertySimpleAttr *attr = - new LibertySimpleAttr(std::move(name), std::move(*value), line); + new LibertySimpleAttr(name, *value, line); delete value; LibertyGroup *group = this->group(); group->addAttr(attr); @@ -189,7 +189,7 @@ LibertyParser::makeComplexAttr(const std::string name, } else { LibertyComplexAttr *attr = - new LibertyComplexAttr(std::move(name), std::move(*values), line); + new LibertyComplexAttr(name, *values, line); delete values; LibertyGroup *group = this->group(); group->addAttr(attr); @@ -414,7 +414,7 @@ LibertyGroup::findSubgroups(const std::string type) const const LibertyGroup * LibertyGroup::findSubgroup(const std::string type) const { - const LibertyGroupSeq &groups = findKeyValue(subgroup_map_, type); + const LibertyGroupSeq groups = findKeyValue(subgroup_map_, type); if (groups.size() >= 1) return groups[0]; else @@ -436,7 +436,7 @@ LibertyGroup::findComplexAttrs(const std::string attr_name) const const LibertyComplexAttr * LibertyGroup::findComplexAttr(const std::string attr_name) const { - const LibertyComplexAttrSeq &attrs = findKeyValue(complex_attr_map_, attr_name); + const LibertyComplexAttrSeq attrs = findKeyValue(complex_attr_map_, attr_name); if (attrs.size() >= 1) return attrs[0]; else From 4f288f2cf209aec7bd5ca2bc42cf66716438f922 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Fri, 27 Mar 2026 16:28:12 +0000 Subject: [PATCH 20/22] Revert unnecessary change in sta/BUILD Signed-off-by: dsengupta0628 --- BUILD | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/BUILD b/BUILD index dc3b7498..44f0c0e1 100644 --- a/BUILD +++ b/BUILD @@ -183,8 +183,7 @@ genrule( #define STA_VERSION "2.7.0" #define STA_GIT_SHA1 "f21d4a3878e2531e3af4930818d9b5968aad9416" #define SSTA 0 - #define ZLIB_FOUND - #define HAVE_CXX_STD_FORMAT 1' > \"$@\" + #define ZLIB_FOUND' > \"$@\" """, visibility = ["//:__subpackages__"], ) From c5f5468ca0d421f76c292b531efeb1d43f6846d9 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Fri, 27 Mar 2026 19:22:27 +0000 Subject: [PATCH 21/22] more update sta fmp and existing spdlog handling Signed-off-by: dsengupta0628 --- BUILD | 3 ++- CMakeLists.txt | 27 +++++++++++++++------------ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/BUILD b/BUILD index 44f0c0e1..dc3b7498 100644 --- a/BUILD +++ b/BUILD @@ -183,7 +183,8 @@ genrule( #define STA_VERSION "2.7.0" #define STA_GIT_SHA1 "f21d4a3878e2531e3af4930818d9b5968aad9416" #define SSTA 0 - #define ZLIB_FOUND' > \"$@\" + #define ZLIB_FOUND + #define HAVE_CXX_STD_FORMAT 1' > \"$@\" """, visibility = ["//:__subpackages__"], ) diff --git a/CMakeLists.txt b/CMakeLists.txt index 88c37cc2..c837df82 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -428,17 +428,15 @@ set(CMAKE_REQUIRED_FLAGS "${_sta_fmt_check_saved_flags}") if(HAVE_CXX_STD_FORMAT) message(STATUS "std::format: available") else() - # Set the fmt dir for the ubuntu/centos docker files. - if(EXISTS "/usr/local/lib/cmake/fmt/fmt-config.cmake") - set(fmt_DIR "/usr/local/lib/cmake/fmt") - elseif(EXISTS "/usr/lib/x86_64-linux-gnu/cmake/fmt/fmt-config.cmake") - set(fmt_DIR "/usr/lib/x86_64-linux-gnu/cmake/fmt") - elseif(EXISTS "/usr/lib/aarch64-linux-gnu/cmake/fmt/fmt-config.cmake") - set(fmt_DIR "/usr/lib/aarch64-linux-gnu/cmake/fmt") - endif() - find_package(fmt QUIET) - if(fmt_FOUND) - message(STATUS "std::format: using installed fmt library") + # Use spdlog's bundled fmt when available to avoid ODR violations. + find_package(spdlog QUIET) + if(spdlog_FOUND) + message(STATUS "std::format: using spdlog's bundled fmt") + set(STA_USE_SPDLOG_FMT TRUE) + get_target_property(_spdlog_inc spdlog::spdlog INTERFACE_INCLUDE_DIRECTORIES) + set(_fmt_dir "${CMAKE_CURRENT_BINARY_DIR}/_spdlog_fmt") + file(MAKE_DIRECTORY "${_fmt_dir}") + file(CREATE_LINK "${_spdlog_inc}/spdlog/fmt/bundled" "${_fmt_dir}/fmt" SYMBOLIC) else() message(STATUS "std::format: building fmt library") include(FetchContent) @@ -571,7 +569,12 @@ target_link_libraries(OpenSTA ) if(NOT HAVE_CXX_STD_FORMAT) - target_link_libraries(OpenSTA fmt::fmt) + if(STA_USE_SPDLOG_FMT) + target_include_directories(OpenSTA PUBLIC "${_fmt_dir}") + target_link_libraries(OpenSTA PUBLIC spdlog::spdlog) + else() + target_link_libraries(OpenSTA fmt::fmt) + endif() endif() if (ZLIB_LIBRARIES) From ffda41536fe1cff4a3a9eed7caf9f810f63234e0 Mon Sep 17 00:00:00 2001 From: dsengupta0628 Date: Fri, 27 Mar 2026 19:53:13 +0000 Subject: [PATCH 22/22] consistent signature Signed-off-by: dsengupta0628 --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c837df82..407a0f47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -571,7 +571,7 @@ target_link_libraries(OpenSTA if(NOT HAVE_CXX_STD_FORMAT) if(STA_USE_SPDLOG_FMT) target_include_directories(OpenSTA PUBLIC "${_fmt_dir}") - target_link_libraries(OpenSTA PUBLIC spdlog::spdlog) + target_link_libraries(OpenSTA spdlog::spdlog) else() target_link_libraries(OpenSTA fmt::fmt) endif()

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