diff --git a/CMakeLists.txt b/CMakeLists.txt index 364038c1..db14372e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -241,8 +241,6 @@ set(STA_SOURCE util/RiseFallMinMaxDelay.cc util/RiseFallValues.cc util/Stats.cc - util/StringSeq.cc - util/StringSet.cc util/StringUtil.cc util/Transition.cc diff --git a/dcalc/CcsCeffDelayCalc.cc b/dcalc/CcsCeffDelayCalc.cc index 3f460d08..ae71f648 100644 --- a/dcalc/CcsCeffDelayCalc.cc +++ b/dcalc/CcsCeffDelayCalc.cc @@ -118,7 +118,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin, ref_time_ = output_waveforms_->referenceTime(in_slew_); debugPrint(debug_, "ccs_dcalc", 1, "%s %s", drvr_cell->name(), - drvr_rf_->to_string().c_str()); + drvr_rf_->shortName()); ArcDelay gate_delay; Slew drvr_slew; gateDelaySlew(drvr_library, drvr_rf_, gate_delay, drvr_slew); diff --git a/dcalc/DelayCalc.cc b/dcalc/DelayCalc.cc index bde9248c..98a3e7b1 100644 --- a/dcalc/DelayCalc.cc +++ b/dcalc/DelayCalc.cc @@ -25,6 +25,7 @@ #include "DelayCalc.hh" #include +#include #include "ContainerHelpers.hh" #include "StringUtil.hh" @@ -37,9 +38,9 @@ namespace sta { -typedef std::map DelayCalcMap; +typedef std::map DelayCalcMap; -static DelayCalcMap *delay_calcs = nullptr; +static DelayCalcMap delay_calcs; void registerDelayCalcs() @@ -54,26 +55,23 @@ registerDelayCalcs() } void -registerDelayCalc(const char *name, +registerDelayCalc(const std::string &name, MakeArcDelayCalc maker) { - if (delay_calcs == nullptr) - delay_calcs = new DelayCalcMap; - (*delay_calcs)[name] = maker; + delay_calcs[name] = maker; } void deleteDelayCalcs() { - delete delay_calcs; - delay_calcs = nullptr; + delay_calcs.clear(); } ArcDelayCalc * -makeDelayCalc(const char *name, +makeDelayCalc(const std::string &name, StaState *sta) { - MakeArcDelayCalc maker = findKey(delay_calcs, name); + MakeArcDelayCalc maker = findKey(&delay_calcs, name); if (maker) return maker(sta); else @@ -81,16 +79,16 @@ makeDelayCalc(const char *name, } bool -isDelayCalcName(const char *name) +isDelayCalcName(const std::string &name) { - return delay_calcs->contains(name); + return delay_calcs.contains(name); } StringSeq delayCalcNames() { StringSeq names; - for (const auto [name, make_dcalc] : *delay_calcs) + for (const auto &[name, make_dcalc] : delay_calcs) names.push_back(name); return names; } diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index dd9b6721..c32362f2 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -125,7 +125,7 @@ class DmpAlg : public StaState { public: DmpAlg(int nr_order, StaState *sta); - virtual ~DmpAlg(); + ~DmpAlg() override = default; virtual const char *name() = 0; // Set driver model and pi model parameters for delay calculation. virtual void init(const LibertyLibrary *library, @@ -156,7 +156,7 @@ public: // Return values. double &vo, double &dol_dt); - // Load responce to driver waveform. + // Load response to driver waveform. void Vl(double t, // Return values. double &vl, @@ -288,8 +288,6 @@ DmpAlg::DmpAlg(int nr_order, fjac_[i] = fjac_storage_ + i * max_nr_order_; } -DmpAlg::~DmpAlg() = default; - void DmpAlg::init(const LibertyLibrary *drvr_library, const LibertyCell *drvr_cell, @@ -1645,7 +1643,8 @@ gateModelRd(const LibertyCell *cell, gate_model->gateDelay(pvt, in_slew, cap1, pocv_enabled, d1, s1); gate_model->gateDelay(pvt, in_slew, cap2, pocv_enabled, d2, s2); double vth = cell->libertyLibrary()->outputThreshold(rf); - float rd = -std::log(vth) * std::abs(delayAsFloat(d1) - delayAsFloat(d2)) / (cap2 - cap1); + float rd = -std::log(vth) * std::abs(delayAsFloat(d1) - delayAsFloat(d2)) + / (cap2 - cap1); return rd; } diff --git a/dcalc/GraphDelayCalc.cc b/dcalc/GraphDelayCalc.cc index 5fdf9587..8bc0765e 100644 --- a/dcalc/GraphDelayCalc.cc +++ b/dcalc/GraphDelayCalc.cc @@ -604,7 +604,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell, { debugPrint(debug_, "delay_calc", 2, " driver cell %s %s", drvr_cell->name(), - rf->to_string().c_str()); + rf->shortName()); for (TimingArcSet *arc_set : drvr_cell->timingArcSets(from_port, to_port)) { for (TimingArc *arc : arc_set->arcs()) { if (arc->toEdge()->asRiseFall() == rf) { @@ -1114,8 +1114,7 @@ GraphDelayCalc::makeArcDcalcArgs(Vertex *drvr_vertex, const Pin *from_pin = from_vertex->pin(); const RiseFall *from_rf = arc1->fromEdge()->asRiseFall(); const RiseFall *drvr_rf = arc1->toEdge()->asRiseFall(); - Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge1, scene, min_max); - in_slew = edgeFromSlew(from_vertex, from_rf, edge1, scene, min_max); + const Slew in_slew = edgeFromSlew(from_vertex, from_rf, edge1, scene, min_max); const Pin *drvr_pin1 = drvr_vertex1->pin(); float load_cap; @@ -1694,7 +1693,7 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge, related_out_cap, scene, min_max, digits); } else { - const Slew &from_slew = edgeFromSlew(from_vertex, from_rf, edge, scene, min_max); + const Slew from_slew = edgeFromSlew(from_vertex, from_rf, edge, scene, min_max); const Parasitic *to_parasitic; float load_cap; parasiticLoad(to_pin, to_rf, scene, min_max, nullptr, arc_delay_calc_, diff --git a/dcalc/PrimaDelayCalc.cc b/dcalc/PrimaDelayCalc.cc index 85175777..118233ce 100644 --- a/dcalc/PrimaDelayCalc.cc +++ b/dcalc/PrimaDelayCalc.cc @@ -231,7 +231,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args, output_waveforms_[drvr_idx] = output_waveforms; debugPrint(debug_, "ccs_dcalc", 1, "%s %s", dcalc_arg.drvrCell()->name(), - drvr_rf_->to_string().c_str()); + drvr_rf_->shortName()); LibertyCell *drvr_cell = dcalc_arg.drvrCell(); const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary(); bool vdd_exists; @@ -744,7 +744,7 @@ PrimaDelayCalc::dcalcResults() debugPrint(debug_, "ccs_dcalc", 2, "load %s %s delay %s slew %s", network_->pathName(load_pin), - drvr_rf_->to_string().c_str(), + drvr_rf_->shortName(), delayAsString(wire_delay, this), delayAsString(load_slew, this)); diff --git a/doc/ApiChanges.txt b/doc/ApiChanges.txt index 34136d76..23c9e11f 100644 --- a/doc/ApiChanges.txt +++ b/doc/ApiChanges.txt @@ -40,7 +40,7 @@ StaState::clk_network__ moved to Mode StaState::parasitics_ moved to Scene Sta::findPathEnds group_paths arg has been changed from PathGroupNameSet* -to StdStringSeq&. +to StringSeq&. Sta::isClock has been removed. Use mode->clkNetwork()->isClock instead. diff --git a/doc/ChangeLog.txt b/doc/ChangeLog.txt index ee123999..8d695f63 100644 --- a/doc/ChangeLog.txt +++ b/doc/ChangeLog.txt @@ -3,7 +3,7 @@ OpenSTA Timing Analyzer Release Notes This file summarizes user visible changes for each release. -2025/02/24 +2026/02/24 ---------- The define_scene -library argument now takes a the library name or a @@ -201,7 +201,7 @@ to remove paths through identical pins and rise/fall edges. Instances now have pins for verilog netlist power/ground connections, Sta::findPathEnds group_paths arg has been changed from PathGroupNameSet* -to StdStringSeq&. +to StringSeq&. Release 2.6.1 2025/03/30 ------------------------- diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index 344e45a6..fb9ea3b6 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,11 +1,11 @@ - Parallax STA documentationJames Cherry5142025-03-17T12:59:52.4638705382010-07-31T21:07:002026-02-25T07:28:47.891834000P123DT1H12M13SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry5192025-03-17T12:59:52.4638705382010-07-31T21:07:002026-03-07T17:12:46.349252000P123DT1H24M11SLibreOffice/25.8.1.1$MacOSX_AARCH64 LibreOffice_project/54047653041915e595ad4e45cccea684809c77b5PDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 348148 - 534 + 1488348 + 1956 19290 17736 true @@ -13,12 +13,12 @@ view2 - 8324 - 356965 - 534 - 348148 - 19823 - 365882 + 17619 + 1497110 + 1956 + 1488348 + 21244 + 1506082 0 1 false @@ -89,7 +89,7 @@ false true false - 26480554 + 26953533 0 false @@ -198,7 +198,7 @@ - + @@ -4399,13 +4399,15 @@ - + + - + + @@ -4414,874 +4416,894 @@ - + + - - + + - + - + - + + + + + + + + + + + + + + + + - + - - - - - - - - - - - - + - + + - + + + + - - - - + - - + - - + + - - - + + - + + - - + + - - - + + + - - - + + - + - - + + + - + - - - - + - + + + + - + - - - + + - + + - + - - + + - + - + - - - - - + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - + - + - + + + + + + + + + + + + - - - - - - - - - - - - + - + - + - + - + - - + + + + + + + + + + + + + - - - - - - - - - - - + - - - + + - - - + + - + - + - - + + - - + + - + - + - + + + + + + + + + + + + + - + - - - - - - - - - - - - + - + + + + - - - - + + + + + + + + + + + + - + - + - + - + - + - + - - - - - - - - - - - - - + + - - + + - + - + - - + + - - - + + - - + + + - + - + - - - + + - - + + + - + + + + + + + + + - - - - - - - - - + - + - - - + + - + - - + + + - - + + - - - - - + + + + - + - - + + + - - + + + + + + + + + + + + + + + + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - + - - + + - - + + - + + - + + - + - - + + - - + - - + - + - - + + - - + + - + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - + - - - + + + - + - - + + + - + - - + + + - + - - - + + - + - + + + + - + - - + + + - - - - - + + + - + - - - + + - - - + + - - - + + - + - + - - + + + - - + + + - + - + - - - + + - - + + - + - + - + - - - + + - + + - + - - + + + - + - - + + - - + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + @@ -5575,786 +5597,792 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + + @@ -6479,7 +6507,7 @@ Example Command Scripts1 Timing Analysis using SDF2 Timing Analysis with Multiple Process Corners2 - Timing Analysis with Multiple Modes3 + Timing Analysis with Multiple Corners and Modes3 Power Analysis3 TCL Interpreter5 Debugging Timing6 @@ -6490,31 +6518,31 @@ Variables85 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. Use the report_units command to see the ccmmand units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. read_liberty nangate45_slow.lib.gzread_liberty nangate45_typ.lib.gzread_liberty nangate45_fast.lib.gzread_verilog example1.link_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}define_scene ss -liberty nangate45_slowdefine_scene tt -liberty nangate45_typdefine_scene ff -liberty nangate45_fast# report all scenesreport_checks -path_delay min_max# report typical scenereport_checks -scene tt This example can be found in examples/multi_corner.tcl. Other examples can be found in the examples directory. - Timing Analysis with Multiple Corners and Modes + Timing Analysis with Multiple Corners and Modes OpenSTA supports multi-corner, multi-mode analysis. Each corner/mode combination is called a “scene”. The SDC constraints in each mode describe a different operating mode, such as mission mode or scan mode. Each corner has min/max Liberty libraries and SPEF parasitics. A mode named “default” is initially created for SDC commands. It is deleted when a mode is defined with set_mode or read_sdc -mode. Similartly, a named “default” is initially created that is deleted when define_scene is used to define a scene. An example command script using two process corners two modes is shown below. read_liberty asap7_small_ff.lib.gzread_liberty asap7_small_ss.lib.gzread_verilog reg1_asap7.vlink_design topread_sdc -mode mode1 mcmm2_mode1.sdcread_sdc -mode mode2 mcmm2_mode2.sdcread_spef -name reg1_ff reg1_asap7.spefread_spef -name reg1_ss reg1_asap7_ss.spefdefine_scene scene1 -mode mode1 -liberty asap7_small_ff -spef reg1_ffdefine_scene scene2 -mode mode2 -liberty asap7_small_ss -spef reg1_ssreport_checks -scenes scene1report_checks -scenes scene2report_checks -group_path_count 4 This example can be found in examples/mcmm3.tcl.In the example show above the SDC for the modes is in separate files. Alternatively, the SDC can be defined in the command file using the set_mode command between SDC command groups. set_mode mode1create_clock -name m1_clk -period 1000 {clk1 clk2 clk3}set_input_delay -clock m1_clk 100 {in1 in2}set_mode mode2create_clock -name m2_clk -period 500 {clk1 clk3}set_output_delay -clock m2_clk 100 out - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. @@ -6526,14 +6554,14 @@ read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-scene scene] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-scene scene] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. + Many reporting commands support redirection of the output to a file much like a Unix shell. report_checks -to out1 > path.logreport_checks -to out2 >> path.log Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. @@ -6559,13 +6587,13 @@ Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6578,7 +6606,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6600,7 +6628,7 @@ - all_outputs + all_outputs @@ -6613,7 +6641,7 @@ - all_registers + all_registers [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] @@ -6691,7 +6719,7 @@ - check_setup + check_setup [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] @@ -6760,7 +6788,7 @@ - connect_pin + connect_pin netport|pin @@ -6859,7 +6887,7 @@ - create_generated_clock + create_generated_clock [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -6975,7 +7003,7 @@ - create_voltage_area + create_voltage_area [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -6988,7 +7016,7 @@ - current_design + current_design [design] @@ -7001,7 +7029,7 @@ - current_instance + current_instance [instance] @@ -7022,7 +7050,7 @@ - define_scene + define_scene -mode mode_name -liberty liberty_files|-liberty_min liberty_min_files -liberty_max liberty_max_files-spef spef_file| -spef_min spef_min_file -spef_max spef_max_file @@ -7060,7 +7088,7 @@ - delete_clock + delete_clock [-all] clocks @@ -7081,7 +7109,7 @@ - delete_from_list + delete_from_list list objects @@ -7111,7 +7139,7 @@ - delete_generated_clock + delete_generated_clock [-all] clocks @@ -7132,7 +7160,7 @@ - delete_instance + delete_instance instance @@ -7153,7 +7181,7 @@ - delete_net + delete_net net @@ -7174,7 +7202,7 @@ - disconnect_pin + disconnect_pin netport | pin | -all @@ -7219,7 +7247,7 @@ - elapsed_run_time + elapsed_run_time @@ -7233,7 +7261,7 @@ - find_timing_paths + find_timing_paths [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-scene scene][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] @@ -7448,7 +7476,7 @@ - get_cells + get_cells [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7525,7 +7553,7 @@ - get_clocks + get_clocks [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7579,7 +7607,7 @@ - get_fanin + get_fanin -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7665,7 +7693,7 @@ - get_fanout + get_fanout -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7750,7 +7778,7 @@ - get_full_name + get_full_name object @@ -7841,7 +7869,7 @@ - get_lib_pins + get_lib_pins [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns @@ -7911,7 +7939,7 @@ - get_libs + get_libs [-filter expr][-regexp][-nocase][-quiet]patterns @@ -7965,7 +7993,7 @@ - get_nets + get_nets [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8042,7 +8070,7 @@ - get_name + get_name object @@ -8064,7 +8092,7 @@ - get_pins + get_pins [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8135,7 +8163,7 @@ - get_ports + get_ports [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -8197,7 +8225,7 @@ - get_property + get_property [-object_type object_type]objectproperty @@ -8229,65 +8257,66 @@ The properties for different objects types are shown below. - cell (SDC lib_cell) + cell (SDC lib_cell) base_namefilenamefull_namelibraryname clock - full_nameis_generatedis_propagatedis_virtualnameperiodsources + full_nameis_generatedis_propagatedis_virtualnameperiodsources edge delay_max_falldelay_min_falldelay_max_risedelay_min_risefull_namefrom_pinsenseto_pin instance (SDC cell) cellfull_nameis_bufferis_clock_gateis_hierarchicalis_inverteris_macrois_memoryliberty_cellnameref_name liberty_cell (SDC lib_cell) - areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname - liberty_port (SDC lib_pin) - capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname - library - filename (Liberty library only)namefull_name + areabase_namedont_usefilenamefull_nameis_bufferis_inverteris_memorylibraryname + liberty_port (SDC lib_pin) + capacitancedirectiondrive_resistancedrive_resistance_max_falldrive_resistance_max_risedrive_resistance_min_falldrive_resistance_min_risefull_nameintrinsic_delayintrinsic_delay_max_fallintrinsic_delay_max_riseintrinsic_delay_min_fallintrinsic_delay_min_riseis_register_clocklib_cellname + library + filename (Liberty library only)namefull_name net full_namename - path (PathEnd) + path (PathEnd) endpointendpoint_clockendpoint_clock_pinslackstartpointstartpoint_clockpoints pin - activity (activity in transitions per second, duty cycle, origin)slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + activity (activity in transitions per second, duty cycle, origin)origin is one ofglobalset_power_activity -globalinputset_power_activity -inputuserset_power_activity -input_ports -pinsvcdread_vcdsaifread_saifpropagatedpropagated from upstream activitiesclockSDC create_clock or create_generated_clockconstantconstant pins propagated from verilog tie high/low, set_case_analysis, set_logic_one/zero/dc + slew_max_fallslew_max_riseslew_min_fallslew_min_riseclocksclock_domainsdirectionfull_nameis_hierarchicalis_portis_register_clocklib_pin_namenameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise port - activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise - point (PathRef) - arrivalpinrequiredslack + activityslew_max_fallslew_max_riseslew_min_fallslew_min_risedirectionfull_nameliberty_portnameslack_maxslack_max_fallslack_max_riseslack_minslack_min_fallslack_min_rise + point (PathRef) + arrivalpinrequiredslack - get_scenes + get_scenes - [-mode mode_name]scene_name + [-mode mode_name]scene_name - mode_name + mode_name - Get the scenes for mode_name. + Get the scenes for mode_name. - scene_name + scene_name - A scene name pattern. + A scene name pattern. - The get_scenes command is used to find the scenes matching a pattern or that use an SDC mode. + The get_scenes command is used to find the scenes matching a pattern or that use an SDC mode. - get_timing_edges + get_timing_edges [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] @@ -8295,53 +8324,53 @@ - -from from_pin + -from from_pin - A list of pins. + A list of pins. - -to to_pin + -to to_pin - A list of pins. + A list of pins. - -of_objects objects + -of_objects objects - A list of instances or library cells. The –from and -to options cannot be used with –of_objects. + A list of instances or library cells. The –from and -to options cannot be used with –of_objects. - -filter expr + -filter expr A filter expression of the form “property==value”where property is a property supported by the get_property command. See the section “Filter Expressions” for additional forms. - The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. + The get_timing_edges command returns a list of timing edges (arcs) to, from or between pins. The result can be passed to get_property or set_disable_timing. - group_path + group_path - -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] + -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] - -name group_name + -name group_name The name of the path group. @@ -8349,7 +8378,7 @@ - -weight weight + -weight weight Not supported. @@ -8357,7 +8386,7 @@ - -critical_range range + -critical_range range Not supported. @@ -8392,7 +8421,7 @@ -through through_list - Group paths through a list of instances, pins or nets. + Group paths through a list of instances, pins or nets. @@ -8400,7 +8429,7 @@ -rise_through through_list - Group rising paths through a list of instances, pins or nets. + Group rising paths through a list of instances, pins or nets. @@ -8408,7 +8437,7 @@ -fall_through through_list - Group falling paths through a list of instances, pins or nets. + Group falling paths through a list of instances, pins or nets. @@ -8416,7 +8445,7 @@ -to to_list - Group paths to a list of clocks, instances, ports or pins. + Group paths to a list of clocks, instances, ports or pins. @@ -8424,7 +8453,7 @@ -rise_to to_list - Group rising paths to a list of clocks, instances, ports or pins. + Group rising paths to a list of clocks, instances, ports or pins. @@ -8432,15 +8461,15 @@ -fall_to to_list - Group falling paths to a list of clocks, instances, port-s or pins. + Group falling paths to a list of clocks, instances, port-s or pins. - -default + -default - Restore the paths in the path group -from/-to/-through/-to to their default path group. + Restore the paths in the path group -from/-to/-through/-to to their default path group. @@ -8450,84 +8479,84 @@ - include + include - [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] + [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] - -echo|-e + -echo|-e - Print each command before evaluating it. + Print each command before evaluating it. - -verbose|-v + -verbose|-v - Print each command before evaluating it as well as the result it returns. + Print each command before evaluating it as well as the result it returns. - filename + filename - The name of the file containing commands to read. + The name of the file containing commands to read. - > log_filename + > log_filename - Redirect command output to log_filename. + Redirect command output to log_filename. - >> log_filename + >> log_filename - Redirect command output and append log_filename. + Redirect command output and append log_filename. - Read STA/SDC/Tcl commands from filename. - The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. + Read STA/SDC/Tcl commands from filename. + The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. - link_design + link_design - [-no_black_boxes][cell_name] + [-no_black_boxes][cell_name] - -no_black_boxes + -no_black_boxes - Do not make empty “black box” cells for instances that reference undefined cells. + Do not make empty “black box” cells for instances that reference undefined cells. - cell_name + cell_name - The top level module/cell name of the design hierarchy to link. + The top level module/cell name of the design hierarchy to link. - Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. + Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. The linker creates empty "block box" cells for instances the reference undefined cells when the variable link_create_black_boxes is true. When link_create_black_boxes is false an error is reported and the link fails. The link_design command returns 1 if the link succeeds and 0 if it fails. @@ -8535,7 +8564,7 @@ - make_instance + make_instance inst_pathlib_cell @@ -8565,7 +8594,7 @@ - make_net + make_net net_name_list @@ -8586,18 +8615,18 @@ - read_liberty + read_liberty - [-corner corner][-min][-max][-infer_latches]filename + [-corner corner][-min][-max][-infer_latches]filename - -corner corner + -corner corner - Use the library for process corner corner delay calculation. + Use the library for process corner corner delay calculation. @@ -8621,12 +8650,12 @@ filename - The liberty file name to read. + The liberty file name to read. The read_liberty command reads a Liberty format library file. The first library that is read sets the units used by SDC/TCL commands and reporting. The include_file attribute is supported. - Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: + Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} In this example a positive level-sensitive latch is inferred. Files compressed with gzip are automatically uncompressed. @@ -8635,48 +8664,48 @@ - read_saif + read_saif - [-scope scope]filename + [-scope scope]filename - scope + scope - The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - filename + filename - The name of the SAIF file to read. + The name of the SAIF file to read. - The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_sdc + read_sdc - [-mode mode_name][-echo]filename + [-mode mode_name][-echo]filename - mode_name + mode_name - Mode for the SDC commands in the file. + Mode for the SDC commands in the file. @@ -8696,8 +8725,8 @@ - Read SDC commands from filename. - If the mode does not exist it is created. Multiple SDC files can append commands to a mode by using the -mode_name argument for each one. If no -mode arguement is is used the commands are added to the current mode. + Read SDC commands from filename. + If the mode does not exist it is created. Multiple SDC files can append commands to a mode by using the -mode_name argument for each one. If no -mode arguement is is used the commands are added to the current mode. The read_sdc command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. Files compressed with gzip are automatically uncompressed. @@ -8705,15 +8734,15 @@ - read_sdf + read_sdf - [-scene scene][-unescaped_dividers]filename + [-scene scene][-unescaped_dividers]filename - scene + scene Scene delays to annotate. @@ -8736,7 +8765,7 @@ - Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. + Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple scenes are defined -scene must be specified. SDC annotation for mcmm analysis must follow the scene definitions. Files compressed with gzip are automatically uncompressed. INCREMENT is supported as an alias for INCREMENTAL. The following SDF statements are not supported. @@ -8746,18 +8775,18 @@ - read_spef + read_spef - [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename + [-name name][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce][-path path]filename - name + name - The name of the SPEF parasitics to use for defining scenes. The default is the base name of filename. + The name of the SPEF parasitics to use for defining scenes. The default is the base name of filename. @@ -8765,12 +8794,12 @@ path - Hierarchical block instance path to annotate with parasitics. + Hierarchical block instance path to annotate with parasitics. - ‑keep_capacitive_coupling + ‑keep_capacitive_coupling Keep coupling capacitors in parasitic networks rather than converting them to grounded capacitors. @@ -8778,10 +8807,10 @@ - ‑coupling_reduction_factorfactor + ‑coupling_reduction_factorfactor - Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. + Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. @@ -8793,58 +8822,58 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. - Separate min/max parasitics can be annotated for each scene mode/corner. - read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max - Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. + Separate min/max parasitics can be annotated for each scene mode/corner. + read_spef -name min spef1read_spef -name max spef2define_scene -mode mode1 -spef_min min -spef_max max + Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. The following SPEF constructs are ignored. *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues - If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. + If the SPEF file contains triplet values the first value is used. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - read_vcd + read_vcd - [-scope scope][-mode mode_name]filename + [-scope scope][-mode mode_name]filename - scope + scope - The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - mode_name + mode_name - Mode to annotate activities. + Mode to annotate activities. - filename + filename - The name of the VCD file to read. + The name of the VCD file to read. - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog filename @@ -8859,8 +8888,8 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. - Verilog 2001 module port declaratations are supported. An example is shown below. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -8868,7 +8897,7 @@ - replace_cell + replace_cell instance_listreplacement_cell @@ -8892,45 +8921,45 @@ - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. - replace_activity_annotation + replace_activity_annotation - [-report_unannotated][-report_annotated] + [-report_unannotated][-report_annotated] - -report_unannotated + -report_unannotated - Report unannotated pins. + Report unannotated pins. - -report_unannotated + -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check - [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] + [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -9000,26 +9029,26 @@ - -max_line lines + -max_line lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9031,16 +9060,16 @@ - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -9061,7 +9090,7 @@ - -from_in_ports + -from_in_ports Report annotated delays from input ports. @@ -9069,7 +9098,7 @@ - -to_out_ports + -to_out_ports Report annotated delays to output ports. @@ -9077,26 +9106,26 @@ - -max_lines lines + -max_lines lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -9108,335 +9137,335 @@ - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-unique_edges_to_endpoint][-scenes scenes][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] - -from from_list + -from from_list - Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Report paths through a list of instances, pins or nets. + Report paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Report rising paths through a list of instances, pins or nets. + Report rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Report falling paths through a list of instances, pins or nets. + Report falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Report paths to a list of clocks, instances, ports or pins. + Report paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Report rising paths to a list of clocks, instances, ports or pins. + Report rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Report falling paths to a list of clocks, instances, ports or pins. + Report falling paths to a list of clocks, instances, ports or pins. - -unconstrained + -unconstrained - Report unconstrained paths also. The unconstrained path group is not reported without this option. + Report unconstrained paths also. The unconstrained path group is not reported without this option. - -path_delay min + -path_delay min - Report min path (hold) checks. + Report min path (hold) checks. - -path_delay min_rise + -path_delay min_rise - Report min path (hold) checks for rising endpoints. + Report min path (hold) checks for rising endpoints. - -path_delay min_fall + -path_delay min_fall - Report min path (hold) checks for falling endpoints. + Report min path (hold) checks for falling endpoints. - -path_delay max + -path_delay max - Report max path (setup) checks. + Report max path (setup) checks. - -path_delay max_rise + -path_delay max_rise - Report max path (setup) checks for rising endpoints. + Report max path (setup) checks for rising endpoints. - -path_delay max_fall + -path_delay max_fall - Report max path (setup) checks for falling endpoints. + Report max path (setup) checks for falling endpoints. - -path_delay min_max + -path_delay min_max - Report max and max path (setup and hold) checks. + Report max and max path (setup and hold) checks. - -group_path_count path_count + -group_path_count path_count - The number of paths to report in each path group. The default is 1. + The number of paths to report in each path group. The default is 1. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to report for each endpoint. The default is 1. + The number of paths to report for each endpoint. The default is 1. - ‑unique_paths_to_endpoint + ‑unique_paths_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pins is reported. - ‑unique_edges_to_endpoint + ‑unique_edges_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count, conditional timing arcs result in paths that through the same pins and rise/fall edges. With this option only the worst path through the set of pins and rise/fall edges is reported. - scenes + scenes - Report paths for one process corner. The default is to report paths for all process corners. + Report paths for one process corner. The default is to report paths for all process corners. - max_slack + max_slack - Only report paths with less slack than max_slack. + Only report paths with less slack than max_slack. - min_slack + min_slack - Only report paths with more slack than min_slack. + Only report paths with more slack than min_slack. - -sort_by_slack + -sort_by_slack - Sort paths by slack rather than slack grouped by path group. + Sort paths by slack rather than slack grouped by path group. - groups + groups - List of path groups to report. The default is to report all path groups. + List of path groups to report. The default is to report all path groups. - -format end + -format end - Report path ends in one line with delay, required time and slack. + Report path ends in one line with delay, required time and slack. - -format full + -format full - Report path start and end points and the path. This is the default path type. + Report path start and end points and the path. This is the default path type. - -format full_clock + -format full_clock - Report path start and end points, the path, and the source and and target clock paths. + Report path start and end points, the path, and the source and and target clock paths. - -format full_clock_expanded + -format full_clock_expanded - Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. + Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. - -format short + -format short - Report only path start and end points. + Report only path start and end points. - -format summary + -format summary - Report only path ends with delay. + Report only path ends with delay. - -format json + -format json - Report in json format. -fields is ignored. + Report in json format. -fields is ignored. - fields + fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr - digits + digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - -no_line_splits + -no_line_splits - Do not split long lines into multiple lines. + Do not split long lines into multiple lines. - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. - See set_false_path for a description of allowed from_list, through_list and to_list objects. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + See set_false_path for a description of allowed from_list, through_list and to_list objects. - report_check_types + report_check_types - [-scenes scenes][-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] + [-scenes scenes][-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] - scenes + scenes - Report checks for some scens. The default value is all scenes. + Report checks for some scens. The default value is all scenes. - -violators + -violators Report all violated timing and design rule constraints. @@ -9444,7 +9473,7 @@ - -verbose + -verbose Use a verbose output format. @@ -9452,18 +9481,18 @@ - -format slack_only + -format slack_only - Report the minimum slack for each timing check. + Report the minimum slack for each timing check. - -format end + -format end - Report the endpoint for each check. + Report the endpoint for each check. @@ -9557,10 +9586,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9568,7 +9597,7 @@ -no_split_lines - Do not split long lines into multiple lines. + Do not split long lines into multiple lines. @@ -9578,60 +9607,60 @@ - report_clock_latency + report_clock_latency - [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] - clocks + clocks - The clocks to report. The default value is all c + The clocks to report. The default value is all c - scenes + scenes - Report clocks for scenes. The default value is all clocks in scenes modes. + Report clocks for scenes. The default value is all clocks in scenes modes. - -include_internal_latency + -include_internal_latency - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. - digits + digits - The number of digits to report for delays. + The number of digits to report for delays. - Report the clock network latency. + Report the clock network latency. - report_clock_min_period + report_clock_min_period - [-clocks clocks][-scenes scenes][-include_port_paths] + [-clocks clocks][-scenes scenes][-include_port_paths] - clocks + clocks The clocks to report. @@ -9646,14 +9675,14 @@ - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. - report_clock_properties + report_clock_properties [clock_names] @@ -9674,10 +9703,10 @@ - report_clock_skew + report_clock_skew - [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] + [-setup|-hold][-clocks clocks][-scenes scenes][-include_internal_latency][-digits digits] @@ -9698,55 +9727,55 @@ - clocks + clocks - The clocks to report. The default value is all clocks in scenes modes. + The clocks to report. The default value is all clocks in scenes modes. - scenes + scenes - Report clocks for scenes. The default value is all scenes. + Report clocks for scenes. The default value is all scenes. - -include_internal_latency + -include_internal_latency - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. - -digits digits + -digits digits The number of digits to report for delays. - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc - [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] + [-from from_pin][-to to_pin][-scene scene][-min][-max][-digits digits][> filename][>> filename] - from_pin + from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. @@ -9754,40 +9783,40 @@ to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. - scene + scene - Report paths for process scene. The -scene keyword is required if more than one process corner is defined. + Report paths for process scene. The -scene keyword is required if more than one process corner is defined. - -min + -min - Report delay calculation for min delays. + Report delay calculation for min delays. - -max + -max - Report delay calculation for max delays. + Report delay calculation for max delays. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default is sta_report_default_digits. + The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9797,7 +9826,7 @@ - report_disabled_edges + report_disabled_edges @@ -9805,42 +9834,42 @@ The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges - [-from from_pin][-to to_pin] + [-from from_pin][-to to_pin] - -from from_pin + -from from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. - -to to_pin + -to to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance instance_path[> filename][>> filename] @@ -9861,7 +9890,7 @@ - report_lib_cell + report_lib_cell cell_name[> filename][>> filename] @@ -9883,7 +9912,7 @@ - report_net + report_net [-digits digits]net_path[> filename][>> filename] @@ -9891,10 +9920,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9906,190 +9935,190 @@ - Report the connections and capacitance of a net. + Report the connections and capacitance of a net. - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] - -report_unannotated + -report_unannotated - Report unannotated and partially annotated nets. + Report unannotated and partially annotated nets. - Report SPEF parasitic annotation completeness. + Report SPEF parasitic annotation completeness. - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] - -instances instances + -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_slews + report_slews - [-scenes scenes]pin + [-scenes scenes]pin - scenes + scenes - Report slews for process for scenes process corners.. + Report slews for process for scenes process corners.. - pin + pin - + - Report the slews at pin + Report the slews at pin - report_tns + report_tns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the total max/setup slack. + Report the total max/setup slack. - -min + -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the total negative slack. + Report the total negative slack. - report_units + report_units - Report the units used for command arguments and reporting. + Report the units used for command arguments and reporting. report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um - report_wns + report_wns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the worst max/setup slack. + Report the worst max/setup slack. - -min + -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the worst negative slack. If the worst slack is positive, zero is reported. + Report the worst negative slack. If the worst slack is positive, zero is reported. - report_worst_slack + report_worst_slack [-min][-max][-digits digits] @@ -10113,10 +10142,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -10127,10 +10156,10 @@ - set_assigned_check + set_assigned_check - -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin + -setup|-hold|-recovery|-removal[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -10138,7 +10167,7 @@ -setup - Annotate setup timing checks. + Annotate setup timing checks. @@ -10146,7 +10175,7 @@ -hold - Annotate hold timing checks. + Annotate hold timing checks. @@ -10154,7 +10183,7 @@ -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. @@ -10162,7 +10191,7 @@ -removal - Annotate removal timing checks. + Annotate removal timing checks. @@ -10183,10 +10212,10 @@ - scene + scene - The name of a scene. The -scene keyword is required if more than one scene is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. @@ -10223,10 +10252,10 @@ - -clock rise|fall + -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. @@ -10234,7 +10263,7 @@ margin - The timing check margin. + The timing check margin. @@ -10245,10 +10274,10 @@ - set_assigned_delay + set_assigned_delay - -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay + -cell|-net[-rise][-fall][-scene scene][-min][-max][-from from_pins][-to to_pins]delay @@ -10285,10 +10314,10 @@ - scene + scene - The name of a scene. The -scene keyword is required if more than one scene is defined. + The name of a scene. The -scene keyword is required if more than one scene is defined. @@ -10338,10 +10367,10 @@ - set_assigned_transition + set_assigned_transition - [-rise][-fall][-scene scene][-min][-max]slewpin_list + [-rise][-fall][-scene scene][-min][-max]slewpin_list @@ -10363,10 +10392,10 @@ - scene + scene - Annotate delays for scene. + Annotate delays for scene. @@ -10408,7 +10437,7 @@ - set_case_analysis + set_case_analysis 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10424,13 +10453,13 @@ The set_case_analysis command sets the signal on a port or pin to a constant logic value. No paths are propagated from constant pins. Constant values set with the set_case_analysis command are propagated through downstream gates. - Conditional timing arcs with mode groups are controlled by logic values on the instance pins. + Conditional timing arcs with mode groups are controlled by logic values on the instance pins. - set_clock_gating_check + set_clock_gating_check [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] @@ -10438,7 +10467,7 @@ - -setup setup_time + -setup setup_time Clock enable setup margin. @@ -10446,7 +10475,7 @@ - -hold hold_time + -hold hold_time Clock enable hold margin. @@ -10504,7 +10533,7 @@ - set_clock_groups + set_clock_groups [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks @@ -10512,7 +10541,7 @@ - -name name + -name name The clock group name. @@ -10565,7 +10594,7 @@ - set_clock_latency + set_clock_latency [-source][-clock clock][-rise][-fall][-min][-max]delayobjects @@ -10573,7 +10602,7 @@ - -source + -source The latency is at the clock source. @@ -10581,7 +10610,7 @@ - -clock clock + -clock clock If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. @@ -10636,13 +10665,13 @@ - The set_clock_latency command describes expected delays of the clock tree when analyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function. + The set_clock_latency command describes expected delays of the clock tree when anxsalyzing a design using ideal clocks. Use the -source option to specify latency at the clock source, also known as insertion delay. Source latency is delay in the clock tree that is external to the design or a clock tree internal to an instance that implements a complex logic function.set_clock_latency removes propagated clock properties for the clocks and pins objects. - set_clock_transition + set_clock_transition [-rise][-fall][-min][-max]transitionclocks @@ -10653,24 +10682,24 @@ -rise - Set the transition time for the rising edge of the clock. - - - - - -fall - - - Set the transition time for the falling edge of the clock. + Set the transition time for the rising edge of the clock. + + + -fall + + + Set the transition time for the falling edge of the clock. + + -min - Set the min transition time. + Set the min transition time. @@ -10678,7 +10707,7 @@ -max - Set the min transition time. + Set the min transition time. @@ -10704,7 +10733,7 @@ - set_clock_uncertainty + set_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] @@ -10712,18 +10741,18 @@ - -from from_clock + -from from_clock - Inter-clock uncertainty source clock. + Inter-clock uncertainty source clock. - -to to_clock + -to to_clock - Inter-clock uncertainty target clock. + Inter-clock uncertainty target clock. @@ -10731,7 +10760,7 @@ -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. @@ -10739,7 +10768,7 @@ -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. @@ -10747,7 +10776,7 @@ -setup - uncertainty is for setup checks. + uncertainty is for setup checks. @@ -10755,12 +10784,12 @@ -hold - uncertainty is for hold checks. + uncertainty is for hold checks. - uncertainty + uncertainty Clock uncertainty. @@ -10775,99 +10804,99 @@ - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - -distance distance_unit + -distance distance_unit - The distance scale factor followed by 'm'. + The distance scale factor followed by 'm'. - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. - M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 + M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um + set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin A pin used as the timing check reference. @@ -10875,7 +10904,7 @@ - -to to_pin + -to to_pin A pin that the setup/hold check is applied to. @@ -10899,7 +10928,7 @@ - -clock clock + -clock clock The setup/hold check clock. @@ -10920,7 +10949,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -10935,13 +10964,14 @@ - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + - set_disable_timing + set_disable_timing [-from from_port][-to to_port]objects @@ -10949,18 +10979,18 @@ - -from from_port + -from from_port - + - -to to_port + -to to_port - + @@ -10968,11 +10998,11 @@ objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. - The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. + The set_disable_timing command is used to disable paths though pins in the design. There are many different forms of the command depending on the objects specified in objects. All timing paths though an instance are disabled when objects contains an instance. Timing checks in the instance are not disabled. set_disable_timing u2 The -from and -to options can be used to restrict the disabled path to those from, to or between specific pins on the instance. @@ -10986,18 +11016,19 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports + -rise - Set the drive rise resistance. + Set the drive rise resistance. @@ -11005,7 +11036,7 @@ -fall - Set the drive fall resistance. + Set the drive fall resistance. @@ -11013,7 +11044,7 @@ -max - Set the maximum resistance. + Set the maximum resistance. @@ -11021,7 +11052,7 @@ -min - Set the minimum resistance. + Set the minimum resistance. @@ -11034,39 +11065,39 @@ - ports + ports A list of ports. - The set_drive command describes the resistance of an input port external driver. + The set_drive command describes the resistance of an input port external driver. - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports - -lib_cell cell_name + -lib_cell cell_name - The driving cell. + The driving cell. - -library library + -library library - The driving cell library. + The driving cell library. @@ -11074,7 +11105,7 @@ -rise - Set the driving cell for a rising edge. + Set the driving cell for a rising edge. @@ -11082,7 +11113,7 @@ -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. @@ -11090,7 +11121,7 @@ -max - Set the driving cell for max delays. + Set the driving cell for max delays. @@ -11098,12 +11129,12 @@ -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin The output port of the driving cell. @@ -11111,15 +11142,16 @@ - -from_pin from_pin + -from_pin from_pin - Use timing arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. + - -input_transition_rise trans_rise + -input_transition_rise trans_rise The transition time for a rising input at from_pin. @@ -11127,7 +11159,7 @@ - -input_transition_fall trans_fall + -input_transition_fall trans_fall The transition time for a falling input at from_pin. @@ -11135,7 +11167,7 @@ - ports + ports A list of ports. @@ -11146,10 +11178,9 @@ - - set_false_path + set_false_path [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -11160,7 +11191,7 @@ -setup - Apply to setup checks. + Apply to setup checks. @@ -11168,7 +11199,7 @@ -hold - Apply to hold checks. + Apply to hold checks. @@ -11176,7 +11207,7 @@ -rise - Apply to rising path edges. + Apply to rising path edges. @@ -11184,7 +11215,7 @@ -fall - Apply to falling path edges. + Apply to falling path edges. @@ -11197,7 +11228,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11205,7 +11236,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11213,7 +11244,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11221,16 +11252,15 @@ The set_false_path command disables timing along a path from, through and to a group of design objects. - Objects in from_list can be clocks, register/latch instances, or register/latch clock pins. The -rise_from and -fall_from keywords restrict the false paths to a specific clock edge. + Objects in from_list can be clocks, register/latch instances, or register/latch clock pins. The -rise_from and -fall_from keywords restrict the false paths to a specific clock edge. Objects in through_list can be nets, instances, instance pins, or hierarchical pins,. The -rise_through and -fall_through keywords restrict the false paths to a specific path edge that traverses through the object. Objects in to_list can be clocks, register/latch instances, or register/latch clock pins. The -rise_to and -fall_to keywords restrict the false paths to a specific transition at the path end. - - set_fanout_load + set_fanout_load fanoutport_list @@ -11243,7 +11273,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11264,7 +11294,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11277,7 +11307,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11290,7 +11320,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11301,9 +11331,10 @@ + - set_input_delay + set_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11314,7 +11345,7 @@ -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. @@ -11322,16 +11353,15 @@ -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. - -max - Set the maximum arrival time. + Set the maximum arrival time. @@ -11339,12 +11369,12 @@ -min - Set the minimum arrival time. + Set the minimum arrival time. - -clock clock + -clock clock The arrival time is from clock. @@ -11360,7 +11390,7 @@ - -reference_pin ref_pin + -reference_pin ref_pin The arrival time is with respect to the clock that arrives at ref_pin. @@ -11371,7 +11401,7 @@ -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. @@ -11379,7 +11409,7 @@ -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. @@ -11407,20 +11437,19 @@ - The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. - set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] - The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + The set_input_delay command is used to specify the arrival time of an input signal. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + set_input_delay -clock clk1 1.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - - set_input_transition + set_input_transition [-rise][-fall][-max][-min]transitionport_list @@ -11431,7 +11460,7 @@ -rise - Set the rising edge transition. + Set the rising edge transition. @@ -11439,7 +11468,7 @@ -fall - Set the falling edge transition. + Set the falling edge transition. @@ -11447,7 +11476,7 @@ -max - Set the minimum transition time. + Set the minimum transition time. @@ -11455,7 +11484,7 @@ -min - Set the maximum transition time. + Set the maximum transition time. @@ -11481,7 +11510,7 @@ - set_level_shifter_strategy + set_level_shifter_strategy [-rule rule_type] @@ -11492,9 +11521,10 @@ + - set_level_shifter_threshold + set_level_shifter_threshold [-voltage voltage] @@ -11507,7 +11537,7 @@ - set_load + set_load [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11518,7 +11548,7 @@ -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). @@ -11526,16 +11556,15 @@ -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). - -max - Set the max capacitance. + Set the max capacitance. @@ -11543,7 +11572,7 @@ -min - Set the min capacitance. + Set the min capacitance. @@ -11551,7 +11580,7 @@ -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. @@ -11587,16 +11616,16 @@ - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc port_list @@ -11617,7 +11646,7 @@ - set_logic_one + set_logic_one port_list @@ -11632,14 +11661,13 @@ - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - - set_logic_zero + set_logic_zero port_list @@ -11654,13 +11682,13 @@ - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area area @@ -11681,7 +11709,7 @@ - set_max_capacitance + set_max_capacitance capacitanceobjects @@ -11695,6 +11723,7 @@ + objects @@ -11710,10 +11739,10 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11721,7 +11750,7 @@ -rise - Set max delay for rising paths. + Set max delay for rising paths. @@ -11729,13 +11758,12 @@ -fall - Set max delay for falling paths. + Set max delay for falling paths. - - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11743,7 +11771,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11751,7 +11779,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11767,10 +11795,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -11791,13 +11819,13 @@ The set_max_delay command constrains the maximum delay through combinational logic paths. See set_false_path for a description of allowed from_list, through_list and to_list objects. If the to_list ends at a timing check the setup/hold time is included in the path delay. - When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. + When the -ignore_clock_latency option is used clock latency at the source and destination of the path delay is ignored. The constraint is reported in the default path group (**default**) rather than the clock path group when the path ends at a timing check. - set_max_dynamic_power + set_max_dynamic_power power [unit] @@ -11810,7 +11838,7 @@ - set_max_fanout + set_max_fanout fanoutobjects @@ -11839,7 +11867,7 @@ - set_max_leakage_power + set_max_leakage_power power [unit] @@ -11852,13 +11880,12 @@ - set_max_time_borrow + set_max_time_borrow delayobjects - delay @@ -11876,13 +11903,13 @@ - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition [-data_path][-clock_path][-rise][-fall]transitionobjects @@ -11890,34 +11917,35 @@ - -data_path + -data_path - Set the max slew for data paths. + Set the max slew for data paths. - -clock_path + -clock_path - Set the max slew for clock paths. + Set the max slew for clock paths. + + + + + + -rise + + + Set the max slew for rising paths. - -rise + -fall - Set the max slew for rising paths. - - - - - -fall - - - Set the max slew for falling paths. + Set the max slew for falling paths. @@ -11925,7 +11953,7 @@ transition - The maximum slew/transition time. + The maximum slew/transition time. @@ -11937,7 +11965,7 @@ - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -11945,7 +11973,7 @@ - set_min_capacitance + set_min_capacitance capacitanceobjects @@ -11956,7 +11984,7 @@ capacitance - Minimum capacitance. + Minimum capacitance. @@ -11972,13 +12000,12 @@ - - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11986,20 +12013,21 @@ -rise - Set min delay for rising paths. + Set min delay for rising paths. + -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12007,7 +12035,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12015,7 +12043,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12031,10 +12059,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -12050,7 +12078,7 @@ delay - The minimum delay. + The minimum delay. @@ -12059,10 +12087,9 @@ - - set_min_pulse_width + set_min_pulse_width [-high][-low]min_widthobjects @@ -12107,20 +12134,21 @@ - set_mode + set_mode - mode_name + mode_name - The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. + The the mode for SDC c ommands in the TCL interpreter. If mode mode_name does not exist, it is created. When modes are created the default mode is deleted. + - set_multicycle_path + set_multicycle_path [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -12131,7 +12159,7 @@ -setup - Set cycle count for setup checks. + Set cycle count for setup checks. @@ -12139,7 +12167,7 @@ -hold - Set cycle count for hold checks. + Set cycle count for hold checks. @@ -12147,16 +12175,15 @@ -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. - -fall - Set cycle count for falling path edges. + Set cycle count for falling path edges. @@ -12177,7 +12204,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -12185,7 +12212,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -12193,7 +12220,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -12220,17 +12247,18 @@ + - set_operating_conditions + set_operating_conditions - [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] + [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] - -analysis_type single + -analysis_type single Use one operating condition for min and max paths. @@ -12238,7 +12266,7 @@ - -analysis_type bc_wc + -analysis_type bc_wc Best case, worst case analysis. Setup checks use max_condition for clock and data paths. Hold checks use the min_condition for clock and data paths. @@ -12246,7 +12274,7 @@ - ‑analysis_type on_chip_variation + ‑analysis_type on_chip_variation The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. @@ -12254,7 +12282,7 @@ - -library lib + -library lib The name of the library that contains condition. @@ -12270,16 +12298,15 @@ - -min min_condition + -min min_condition The operating condition to use for min paths and hold checks. - - -max max_condition + -max max_condition The operating condition to use for max paths and setup checks. @@ -12287,7 +12314,7 @@ - -min_library min_lib + -min_library min_lib The name of the library that contains min_condition. @@ -12295,7 +12322,7 @@ - -max_library max_lib + -max_library max_lib The name of the library that contains max_condition. @@ -12308,18 +12335,19 @@ - set_output_delay + set_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list + -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. @@ -12327,7 +12355,7 @@ -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. @@ -12335,7 +12363,7 @@ -max - Set the maximum output delay. + Set the maximum output delay. @@ -12343,15 +12371,15 @@ -min - Set the minimum output delay. + Set the minimum output delay. - -clock clock + -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. @@ -12359,15 +12387,15 @@ -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. @@ -12375,7 +12403,7 @@ -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. @@ -12383,7 +12411,7 @@ delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. @@ -12395,17 +12423,17 @@ - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports @@ -12413,7 +12441,7 @@ -min - Set the min fanout. + Set the min fanout. @@ -12421,7 +12449,7 @@ -max - Set the max fanout. + Set the max fanout. @@ -12441,21 +12469,21 @@ - Set the external fanout for ports. + Set the external fanout for ports. - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global Set the activity/duty for all non-clock pins. @@ -12471,7 +12499,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -12479,55 +12507,54 @@ - -pins pins + -pins pins Set the pin activity/duty. - - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -density density + -density density - Transitions per library time unit. + Transitions per library time unit. - -duty duty + -duty duty - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -clock clock + -clock clock - The clock to use for the period with -activity. This option is ignored if -density is used. + The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock objects @@ -12546,13 +12573,14 @@ + - set_pvt + set_pvt - [-min][-max][-process process][-voltage voltage] - [-temperature temperature]instances + [-min][-max][-process process][-voltage voltage] + [-temperature temperature]instances @@ -12560,7 +12588,7 @@ -min - Set the PVT values for max delays. + Set the PVT values for max delays. @@ -12568,12 +12596,12 @@ -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process A process value (float). @@ -12581,16 +12609,15 @@ - -voltage voltage + -voltage voltage A voltage value (float). - - -temperature temperature + -temperature temperature A temperature value (float). @@ -12611,7 +12638,7 @@ - set_sense + set_sense [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins @@ -12619,18 +12646,18 @@ - -type clock + -type clock - Set the sense for clock paths. + Set the sense for clock paths. - -type data + -type data - Set the sense for data paths (not supported). + Set the sense for data paths (not supported). @@ -12638,7 +12665,7 @@ -positive - The clock sense is positive unate. + The clock sense is positive unate. @@ -12646,15 +12673,16 @@ -negative - The clock sense is negative unate. + The clock sense is negative unate. + - -pulse pulse_type + -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. @@ -12686,10 +12714,9 @@ - - set_timing_derate + set_timing_derate [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] @@ -12697,18 +12724,18 @@ - -rise + -rise - Set the derating for rising delays. + Set the derating for rising delays. - -fall + -fall - Set the derating for falling delays. + Set the derating for falling delays. @@ -12751,6 +12778,7 @@ Derate net (interconnect) delays. + -cell_delay @@ -12772,7 +12800,7 @@ derate - The derating factor to apply to delays. + The derating factor to apply to delays. @@ -12791,13 +12819,12 @@ - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets - -min @@ -12824,7 +12851,7 @@ - nets + nets A list of nets. @@ -12837,72 +12864,73 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. + + + + + + -voltage voltage_unit + + + The voltage scale factor followed by 'v'. - -voltage voltage_unit + -current current_unit - The voltage scale factor followed by 'v'. + The current scale factor followed by 'A'. - -current current_unit + -power power_unit - The current scale factor followed by 'A'. - - - - - -power power_unit - - - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. - M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 + M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm + set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -12915,7 +12943,7 @@ - set_wire_load_mode + set_wire_load_mode top|enclosed|segmented @@ -12952,15 +12980,16 @@ - set_wire_load_model + set_wire_load_model -name model_name[-library library][-max][-min][objects] + - -name model_name + -name model_name The name of a wire load model. @@ -12968,7 +12997,7 @@ - -library library + -library library Library to look for model_name. @@ -13005,7 +13034,7 @@ - set_wire_load_selection_group + set_wire_load_selection_group [-library library][-max][-min]group_name[objects] @@ -13019,7 +13048,6 @@ Library to look for group_name. - -max @@ -13059,28 +13087,28 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -13095,13 +13123,13 @@ - The unset_case_analysis command removes the constant values defined by the set_case_analysis command. + The unset_case_analysis command removes the constant values defined by the set_case_analysis command. - unset_clock_latency + unset_clock_latency [-source]objects @@ -13130,7 +13158,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -13149,10 +13177,9 @@ - - unset_clock_uncertainty + unset_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] @@ -13160,7 +13187,7 @@ - -from from_clock + -from from_clock @@ -13168,7 +13195,7 @@ - -to to_clock + -to to_clock @@ -13208,7 +13235,7 @@ - uncertainty + uncertainty Clock uncertainty. @@ -13223,21 +13250,21 @@ - The unset_clock_uncertainty command removes clock uncertainty defined with the set_clock_uncertainty command. + The unset_clock_uncertainty command removes clock uncertainty defined with the set_clock_uncertainty command. - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] - -from from_object + -from from_object A pin used as the timing check reference. @@ -13245,7 +13272,7 @@ - -to to_object + -to to_object A pin that the setup/hold check is applied to. @@ -13269,20 +13296,20 @@ - clock + clock The setup/hold check clock. - The unset_clock_transition command removes a setup or hold check defined by the set_data_check command. + The unset_clock_transition command removes a setup or hold check defined by the set_data_check command. - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13297,13 +13324,13 @@ - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing [-from from_port][-to to_port]objects @@ -13314,7 +13341,7 @@ from_port - + @@ -13322,7 +13349,7 @@ to_port - + @@ -13338,9 +13365,10 @@ + - unset_input_delay + unset_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13351,7 +13379,7 @@ -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. @@ -13359,7 +13387,7 @@ -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. @@ -13367,7 +13395,7 @@ -max - Unset the minimum arrival time. + Unset the minimum arrival time. @@ -13375,7 +13403,7 @@ -min - Unset the maximum arrival time. + Unset the maximum arrival time. @@ -13383,7 +13411,7 @@ clock - Unset the arrival time from clock. + Unset the arrival time from clock. @@ -13391,10 +13419,9 @@ -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock - pin_port_list @@ -13410,7 +13437,7 @@ - unset_output_delay + unset_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13456,6 +13483,7 @@ The arrival time is from this clock. + -clock_fall @@ -13479,10 +13507,10 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13490,7 +13518,7 @@ -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. @@ -13498,7 +13526,7 @@ -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. @@ -13506,21 +13534,20 @@ -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. - -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13528,7 +13555,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13536,7 +13563,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13544,66 +13571,67 @@ The unset_path_exceptions command removes any matching set_false_path, set_multicycle_path, set_max_delay, and set_min_delay exceptions. - + - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global - Set the activity/duty for all non-clock pins. + Set the activity/duty for all non-clock pins. - -input + -input - Set the default input port activity/duty. + Set the default input port activity/duty. - -input_ports input_ports + -input_ports input_ports - Set the input port activity/duty. + Set the input port activity/duty. + + + + + + -pins pins + + + Set the pin activity/duty. - -pins pins + -activity activity - Set the pin activity/duty. - - - - - -activity activity - - - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - The unset_power_activity_command is used to undo the effects of the set_power_activity command. + The unset_power_activity_command is used to undo the effects of the set_power_activity command. - unset_propagated_clock + unset_propagated_clock objects @@ -13624,42 +13652,41 @@ - unset_timing_derate + unset_timing_derate - Remove all derating factors set with the set_timing_derate command. + Remove all derating factors set with the set_timing_derate command. - - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time @@ -13672,7 +13699,7 @@ - with_output_to_variable + with_output_to_variable var { commands } @@ -13695,21 +13722,22 @@ - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. + - write_path_spice + write_path_spice - -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] - path_args + path_args -from|-through|-to arguments as in report_checks. @@ -13717,15 +13745,15 @@ - spice_directory + spice_directory - Directory for spice to write output files. + Directory for spice to write output files. - lib_subckts_file + lib_subckts_file Cell transistor level subckts. @@ -13733,7 +13761,7 @@ - model_file + model_file Transistor model definitions .included by spice_file. @@ -13741,7 +13769,7 @@ - power + power Voltage supply name in voltage_map of the default liberty library. @@ -13749,7 +13777,7 @@ - ground + ground Ground supply name in voltage_map of the default liberty library. @@ -13757,30 +13785,31 @@ - -simulator + -simulator - Simulator that will read the spice netlist. + Simulator that will read the spice netlist. The write_path_spice command writes a spice netlist for timing paths. Use path_args to specify -from/-through/-to as arguments to the find_timing_paths command. For each path, a spice netlist and the subckts referenced by the path are written in spice_directory. The spice netlist is written in path_<id>.sp and subckt file is path_<id>.subckt. - The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. - Example command: - write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS - When the simulator is hspice, .measure statements will be added to the spice netlist. - When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. + The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. + Example command: + write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS + When the simulator is hspice, .measure statements will be added to the spice netlist. + When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. - write_sdc + write_sdc [-digits digits][-gzip][-no_timestamp]filename + digits @@ -13794,7 +13823,7 @@ -gzip - Compress the SDC with gzip. + Compress the SDC with gzip. @@ -13820,18 +13849,18 @@ - write_sdf + write_sdf - [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename + [-scene scene][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename - scene + scene - Write delays for scene. + Write delays for scene. @@ -13842,7 +13871,6 @@ Divider to use between hierarchy levels in pin and instance names. - -include_typ @@ -13853,7 +13881,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default is 4. @@ -13864,7 +13892,7 @@ -gzip - Compress the SDF using gzip. + Compress the SDF using gzip. @@ -13888,78 +13916,79 @@ filename - The SDF filename to write. + The SDF filename to write. - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-scene scene]filename + [-library_name lib_name][-cell_name cell_name] + [-scene scene]filename + + + + + + lib_name + + + The name to use for the liberty library. Defaults to cell_name. - lib_name + cell_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty cell. Defaults to the top level module name. - cell_name + scene - The name to use for the liberty cell. Defaults to the top level module name. + The scene to use for extracting the model. - scene + filename - The scene to use for extracting the model. - - - - - filename - - - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. - set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. - The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: - combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths - Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + set_input_delayset_output_delayset_loadset_timing_derate + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: + combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths + Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. - write_verilog + write_verilog - [-include_pwr_gnd][-remove_cells lib_cells]filename + [-include_pwr_gnd][-remove_cells lib_cells]filename - -include_pwr_gnd + -include_pwr_gnd Include power and ground pins on instances. @@ -13967,24 +13996,24 @@ - -remove_cells lib_cells + -remove_cells lib_cells - Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. + Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. - filename + filename - Filename for the liberty library. + Filename for the liberty library. - The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions - The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions + The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -13993,7 +14022,7 @@ property - Return objects with property value equal to 1. + Return objects with property value equal to 1. @@ -14001,61 +14030,61 @@ property==value - Return objects with property value equal to value. + Return objects with property value equal to value. - property=~pattern + property=~pattern - Return objects with property value that matches pattern. + Return objects with property value that matches pattern. - property!=value + property!=value - Return objects with property value not equal to value. + Return objects with property value not equal to value. - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. - expr1&&expr2 + expr1&&expr2 - Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. - expr1||expr2 + expr1||expr2 - Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. @@ -14065,33 +14094,34 @@ - sta_continue_on_error + sta_continue_on_error 0|1 - The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. + The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. - sta_crpr_mode + sta_crpr_mode same_pin|same_transition - When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled 0|1 @@ -14104,7 +14134,7 @@ - sta_crpr_enabled + sta_crpr_enabled 0|1 @@ -14117,7 +14147,7 @@ - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking 0|1 @@ -14130,20 +14160,20 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock 0|1 @@ -14156,7 +14186,7 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled 0|1 @@ -14169,7 +14199,7 @@ - sta_pocv_enabled + sta_pocv_enabled 0|1 @@ -14182,14 +14212,14 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] After all clocks have been defined. The default value is 0. @@ -14197,33 +14227,33 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - sta_report_default_digits + sta_report_default_digits integer @@ -14234,10 +14264,9 @@ - - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled 0|1 @@ -14270,186 +14299,186 @@ - Alphabetical Index + Alphabetical Index - all_clocks7 - all_inputs7 - all_outputs8 - all_registers8 - check_setup9 - Command Line Arguments1 - Commands7 - connect_pin9 - create_generated_clock11 - create_voltage_area12 - current_design12 - current_instance13 - define_scene13 - delete_clock13 - delete_from_list13 - delete_generated_clock13 - delete_instance14 - delete_net14 - disconnect_pin14 - elapsed_run_time14 - Example Command Scripts1 - Filter Expressions84 - find_timing_paths15 - get_cells17 - get_clocks17 - get_fanin18 - get_fanout19 - get_full_name19 - get_lib_pins20 - get_libs21 - get_name22 - get_nets22 - get_pins23 - get_ports23 - get_property24 - get_scenes28 - get_timing_edges28 - group_path29 - hierarchy_separator85 - include30 - link_design30 - make_instance30 - make_net31 - Power Analysis3 - read_liberty31 - read_saif32 - read_sdc33 - read_sdf33 - read_spef34 - read_vcd35 - read_verilog35 - redirection5 - replace_activity_annotation36 - replace_cell35 - report_annotated_check36 - report_annotated_delay37 - report_check_types41 - report_checks38 - report_clock_latency42 - report_clock_min_period42 - report_clock_properties43 - report_clock_skew43 - report_dcalc43 - report_disabled_edges44 - report_edges44 - report_instance44 - report_lib_cell44 - report_net45 - report_parasitic_annotation45 - report_power45 - report_slews46 - report_tns46 - report_units46 - report_wns47 - report_worst_slack47 - set_assigned_check48 - set_assigned_delay49 - set_assigned_transition49 - set_case_analysis50 - set_clock_gating_check50 - set_clock_groups51 - set_clock_latency52 - set_clock_transition52 - set_clock_uncertainty53 - set_cmd_units54 - set_data_check55 - set_disable_inferred_clock_gating55 - set_disable_timing55 - set_drive56 - set_driving_cell57 - set_false_path58 - set_fanout_load59 - set_hierarchy_separator59 - set_ideal_latency59 - set_ideal_network59 - set_ideal_transition59 - set_input_delay59 - set_input_transition61 - set_level_shifter_strategy61 - set_level_shifter_threshold61 - set_load61 - set_logic_dc62 - set_logic_one62 - set_logic_zero63 - set_max_area63 - set_max_capacitance63 - set_max_delay63 - set_max_dynamic_power64 - set_max_fanout64 - set_max_leakage_power64 - set_max_time_borrow64 - set_max_transition65 - set_min_capacitance65 - set_min_delay66 - set_min_pulse_width67 - set_mode67 - set_multicycle_path67 - set_operating_conditions68 - set_output_delay69 - set_port_fanout_number70 - set_power_activity70 - set_propagated_clock71 - set_pvt71 - set_resistance73 - set_sense72 - set_timing_derate73 - set_units74 - set_wire_load_min_block_size75 - set_wire_load_mode75 - set_wire_load_model75 - set_wire_load_selection_group75 - SPEF34 - sta_cond_default_arcs_enabled85 - sta_continue_on_error85 - sta_crpr_enabled85 - sta_crpr_mode85 - sta_dynamic_loop_breaking85 - sta_gated_clock_checks_enabled85 - sta_input_port_default_clock86 - sta_internal_bidirect_instance_paths_enabled86 - sta_pocv_enabled86 - sta_preset_clear_arcs_enabled87 - sta_propagate_all_clocks86 - sta_propagate_gated_clock_enable86 - sta_recovery_removal_checks_enabled86 - sta_report_default_digits86 - suppress_msg76 - TCL Interpreter5 - Timing Analysis using SDF2 - Timing Analysis with Multiple Modes3 - Timing Analysis with Multiple Process Corners2 - unset_case_analysis76 - unset_clock_latency76 - unset_clock_transition76 - unset_clock_uncertainty77 - unset_data_check77 - unset_disable_inferred_clock_gating78 - unset_disable_timing78 - unset_input_delay78 - unset_output_delay79 - unset_path_exceptions79 - unset_power_activity80 - unset_propagated_clock80 - unset_timing_derate80 - unsuppress_msg81 - user_run_time81 - Variables85 - verilog netlist35 - with_output_to_variable81 - write_path_spice81 - write_sdc82 - write_sdf82 - write_timing_model83 - write_verilog84 + all_clocks7 + all_inputs7 + all_outputs8 + all_registers8 + check_setup9 + Command Line Arguments1 + Commands7 + connect_pin9 + create_generated_clock11 + create_voltage_area12 + current_design12 + current_instance13 + define_scene13 + delete_clock13 + delete_from_list13 + delete_generated_clock14 + delete_instance14 + delete_net14 + disconnect_pin14 + elapsed_run_time14 + Example Command Scripts1 + Filter Expressions84 + find_timing_paths15 + get_cells17 + get_clocks17 + get_fanin18 + get_fanout19 + get_full_name19 + get_lib_pins20 + get_libs21 + get_name22 + get_nets22 + get_pins23 + get_ports23 + get_property24 + get_scenes28 + get_timing_edges28 + group_path29 + hierarchy_separator85 + include30 + link_design30 + make_instance30 + make_net31 + Power Analysis3 + read_liberty31 + read_saif32 + read_sdc33 + read_sdf33 + read_spef34 + read_vcd35 + read_verilog35 + redirection5 + replace_activity_annotation36 + replace_cell35 + report_annotated_check36 + report_annotated_delay37 + report_check_types41 + report_checks38 + report_clock_latency42 + report_clock_min_period42 + report_clock_properties43 + report_clock_skew43 + report_dcalc43 + report_disabled_edges44 + report_edges44 + report_instance44 + report_lib_cell44 + report_net45 + report_parasitic_annotation45 + report_power45 + report_slews46 + report_tns46 + report_units46 + report_wns47 + report_worst_slack47 + set_assigned_check48 + set_assigned_delay49 + set_assigned_transition49 + set_case_analysis50 + set_clock_gating_check50 + set_clock_groups51 + set_clock_latency52 + set_clock_transition52 + set_clock_uncertainty53 + set_cmd_units54 + set_data_check55 + set_disable_inferred_clock_gating55 + set_disable_timing55 + set_drive56 + set_driving_cell57 + set_false_path58 + set_fanout_load59 + set_hierarchy_separator59 + set_ideal_latency59 + set_ideal_network59 + set_ideal_transition59 + set_input_delay59 + set_input_transition61 + set_level_shifter_strategy61 + set_level_shifter_threshold61 + set_load61 + set_logic_dc62 + set_logic_one62 + set_logic_zero63 + set_max_area63 + set_max_capacitance63 + set_max_delay63 + set_max_dynamic_power64 + set_max_fanout64 + set_max_leakage_power64 + set_max_time_borrow64 + set_max_transition65 + set_min_capacitance65 + set_min_delay66 + set_min_pulse_width67 + set_mode67 + set_multicycle_path67 + set_operating_conditions68 + set_output_delay69 + set_port_fanout_number70 + set_power_activity70 + set_propagated_clock71 + set_pvt71 + set_resistance73 + set_sense72 + set_timing_derate73 + set_units74 + set_wire_load_min_block_size75 + set_wire_load_mode75 + set_wire_load_model75 + set_wire_load_selection_group75 + SPEF34 + sta_cond_default_arcs_enabled85 + sta_continue_on_error85 + sta_crpr_enabled85 + sta_crpr_mode85 + sta_dynamic_loop_breaking85 + sta_gated_clock_checks_enabled85 + sta_input_port_default_clock86 + sta_internal_bidirect_instance_paths_enabled86 + sta_pocv_enabled86 + sta_preset_clear_arcs_enabled87 + sta_propagate_all_clocks86 + sta_propagate_gated_clock_enable86 + sta_recovery_removal_checks_enabled86 + sta_report_default_digits86 + suppress_msg76 + TCL Interpreter5 + Timing Analysis using SDF2 + Timing Analysis with Multiple Corners and Modes3 + Timing Analysis with Multiple Process Corners2 + unset_case_analysis76 + unset_clock_latency76 + unset_clock_transition76 + unset_clock_uncertainty77 + unset_data_check77 + unset_disable_inferred_clock_gating78 + unset_disable_timing78 + unset_input_delay78 + unset_output_delay79 + unset_path_exceptions79 + unset_power_activity80 + unset_propagated_clock80 + unset_timing_derate80 + unsuppress_msg81 + user_run_time81 + Variables85 + verilog netlist35 + with_output_to_variable81 + write_path_spice81 + write_sdc82 + write_sdf82 + write_timing_model83 + write_verilog84 - - Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. + + Version 3.0.0, Mar 7, 2026Copyright (c) 2026, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <https://www.gnu.org/licenses/>. diff --git a/doc/OpenSTA.pdf b/doc/OpenSTA.pdf index c084d808..77ebd937 100644 Binary files a/doc/OpenSTA.pdf and b/doc/OpenSTA.pdf differ diff --git a/graph/Graph.i b/graph/Graph.i index b6f3c3c5..289ca3ba 100644 --- a/graph/Graph.i +++ b/graph/Graph.i @@ -299,7 +299,7 @@ latch_d_to_q_en() if (enable_port) return stringPrintTmp("%s %s", enable_port->name(), - enable_rf->to_string().c_str()); + enable_rf->shortName()); } return ""; } diff --git a/include/sta/Bfs.hh b/include/sta/Bfs.hh index 9b639624..5fa335c0 100644 --- a/include/sta/Bfs.hh +++ b/include/sta/Bfs.hh @@ -77,9 +77,9 @@ public: void remove(Vertex *vertex); void reportEntries() const; - virtual bool hasNext(); + bool hasNext() override; bool hasNext(Level to_level); - virtual Vertex *next(); + Vertex *next() override; // Apply visitor to all vertices in the queue in level order. // Returns the number of vertices that are visited. @@ -131,19 +131,19 @@ public: SearchPred *search_pred, StaState *sta); virtual ~BfsFwdIterator(); - virtual void enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred); - virtual void enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred, - const Mode *mode); + void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred) override; + void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred, + const Mode *mode) override; using BfsIterator::enqueueAdjacentVertices; protected: - virtual bool levelLessOrEqual(Level level1, - Level level2) const; - virtual bool levelLess(Level level1, - Level level2) const; - virtual void incrLevel(Level &level) const; + bool levelLessOrEqual(Level level1, + Level level2) const override; + bool levelLess(Level level1, + Level level2) const override; + void incrLevel(Level &level) const override; }; class BfsBkwdIterator : public BfsIterator @@ -153,19 +153,19 @@ public: SearchPred *search_pred, StaState *sta); virtual ~BfsBkwdIterator(); - virtual void enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred); - virtual void enqueueAdjacentVertices(Vertex *vertex, - SearchPred *search_pred, - const Mode *mode); + void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred) override; + void enqueueAdjacentVertices(Vertex *vertex, + SearchPred *search_pred, + const Mode *mode) override; using BfsIterator::enqueueAdjacentVertices; protected: - virtual bool levelLessOrEqual(Level level1, - Level level2) const; - virtual bool levelLess(Level level1, - Level level2) const; - virtual void incrLevel(Level &level) const; + bool levelLessOrEqual(Level level1, + Level level2) const override; + bool levelLess(Level level1, + Level level2) const override; + void incrLevel(Level &level) const override; }; } // namespace diff --git a/include/sta/BoundedHeap.hh b/include/sta/BoundedHeap.hh index 45bfdeed..af934e0c 100644 --- a/include/sta/BoundedHeap.hh +++ b/include/sta/BoundedHeap.hh @@ -60,7 +60,6 @@ public: comp_(comp), min_heap_comp_(comp) { - heap_.reserve(max_size); } // Copy constructor @@ -107,7 +106,12 @@ public: setMaxSize(size_t max_size) { max_size_ = max_size; - heap_.reserve(max_size); + } + + void + reserve(size_t size) + { + heap_.reserve(size); } // Insert an element into the heap. @@ -172,8 +176,6 @@ public: { // Convert heap to sorted vector (best to worst) std::sort_heap(heap_.begin(), heap_.end(), min_heap_comp_); - // Reverse to get best first (according to user's comparison) - std::reverse(heap_.begin(), heap_.end()); std::vector result = std::move(heap_); heap_.clear(); return result; @@ -181,11 +183,10 @@ public: // Extract all elements sorted from best to worst (const version). // Creates a copy since we can't modify the heap. - std::vector extract() const + std::vector contents() const { std::vector temp_heap = heap_; std::sort_heap(temp_heap.begin(), temp_heap.end(), min_heap_comp_); - std::reverse(temp_heap.begin(), temp_heap.end()); return temp_heap; } @@ -245,7 +246,7 @@ private: Compare comp_; explicit MinHeapCompare(const Compare& c) : comp_(c) {} bool operator()(const T& a, const T& b) const { - return comp_(b, a); // Inverted: worst is at root + return comp_(a, b); // comp = less puts largest at root (worst) } }; diff --git a/include/sta/ConcreteLibrary.hh b/include/sta/ConcreteLibrary.hh index 48c4db06..69e60dce 100644 --- a/include/sta/ConcreteLibrary.hh +++ b/include/sta/ConcreteLibrary.hh @@ -264,8 +264,8 @@ class ConcreteCellPortBitIterator : public Iterator { public: ConcreteCellPortBitIterator(const ConcreteCell *cell); - virtual bool hasNext(); - virtual ConcretePort *next(); + bool hasNext() override; + ConcretePort *next() override; private: void findNext(); diff --git a/include/sta/DelayCalc.hh b/include/sta/DelayCalc.hh index dbadf0b6..cea48177 100644 --- a/include/sta/DelayCalc.hh +++ b/include/sta/DelayCalc.hh @@ -24,7 +24,9 @@ #pragma once -#include "StringSeq.hh" +#include + +#include "StringUtil.hh" namespace sta { @@ -38,10 +40,10 @@ void registerDelayCalcs(); // Register a delay calculator for the set_delay_calc command. void -registerDelayCalc(const char *name, +registerDelayCalc(const std::string &name, MakeArcDelayCalc maker); bool -isDelayCalcName(const char *name); +isDelayCalcName(const std::string &name); StringSeq delayCalcNames(); void @@ -49,7 +51,7 @@ deleteDelayCalcs(); // Make a registered delay calculator by name. ArcDelayCalc * -makeDelayCalc(const char *name, +makeDelayCalc(const std::string &name, StaState *sta); } // namespace diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index 28625854..7d9557b4 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -427,8 +427,8 @@ class VertexIterator : public Iterator { public: VertexIterator(Graph *graph); - virtual bool hasNext() { return vertex_ || bidir_vertex_; } - virtual Vertex *next(); + bool hasNext() override { return vertex_ || bidir_vertex_; } + Vertex *next() override; private: bool findNextPin(); @@ -450,8 +450,8 @@ public: const Graph *graph); VertexInEdgeIterator(VertexId vertex_id, const Graph *graph); - bool hasNext() { return (next_ != nullptr); } - Edge *next(); + bool hasNext() override { return (next_ != nullptr); } + Edge *next() override; private: Edge *next_; @@ -463,8 +463,8 @@ class VertexOutEdgeIterator : public VertexEdgeIterator public: VertexOutEdgeIterator(Vertex *vertex, const Graph *graph); - bool hasNext() { return (next_ != nullptr); } - Edge *next(); + bool hasNext() override { return (next_ != nullptr); } + Edge *next() override; private: Edge *next_; @@ -478,8 +478,8 @@ public: EdgesThruHierPinIterator(const Pin *hpin, Network *network, Graph *graph); - virtual bool hasNext(); - virtual Edge *next(); + bool hasNext() override; + Edge *next() override; private: EdgeSet edges_; diff --git a/include/sta/Iterator.hh b/include/sta/Iterator.hh index eade8d31..06416b23 100644 --- a/include/sta/Iterator.hh +++ b/include/sta/Iterator.hh @@ -56,8 +56,8 @@ public: { } - bool hasNext() { return seq_ && itr_ != seq_->end(); } - OBJ_TYPE next() { return *itr_++; } + bool hasNext() override { return seq_ && itr_ != seq_->end(); } + OBJ_TYPE next() override { return *itr_++; } protected: const VECTOR_TYPE *seq_; @@ -80,8 +80,8 @@ public: { } - bool hasNext() { return map_ && itr_ != map_->end(); } - OBJ_TYPE next() { + bool hasNext() override { return map_ && itr_ != map_->end(); } + OBJ_TYPE next() override { OBJ_TYPE next = itr_->second; itr_++; return next; @@ -108,8 +108,8 @@ public: { } - bool hasNext() { return set_ && itr_ != set_->end(); } - OBJ_TYPE next() { return *itr_++; } + bool hasNext() override { return set_ && itr_ != set_->end(); } + OBJ_TYPE next() override { return *itr_++; } protected: const SET_TYPE *set_; diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 3f096a81..981b2a26 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -458,8 +458,8 @@ class LibertyCellIterator : public Iterator { public: LibertyCellIterator(const LibertyLibrary *library); - bool hasNext(); - LibertyCell *next(); + bool hasNext() override; + LibertyCell *next() override; private: ConcreteLibraryCellIterator iter_; @@ -715,8 +715,8 @@ class LibertyCellPortIterator : public Iterator { public: LibertyCellPortIterator(const LibertyCell *cell); - bool hasNext(); - LibertyPort *next(); + bool hasNext() override; + LibertyPort *next() override; private: ConcreteCellPortIterator iter_; @@ -727,8 +727,8 @@ class LibertyCellPortBitIterator : public Iterator public: LibertyCellPortBitIterator(const LibertyCell *cell); virtual ~LibertyCellPortBitIterator(); - bool hasNext(); - LibertyPort *next(); + bool hasNext() override; + LibertyPort *next() override; private: ConcreteCellPortBitIterator *iter_; @@ -980,8 +980,8 @@ class LibertyPortMemberIterator : public Iterator public: LibertyPortMemberIterator(const LibertyPort *port); virtual ~LibertyPortMemberIterator(); - virtual bool hasNext(); - virtual LibertyPort *next(); + bool hasNext() override; + LibertyPort *next() override; private: ConcretePortMemberIterator *iter_; diff --git a/include/sta/Mode.hh b/include/sta/Mode.hh index 0c0827e1..b47adc00 100644 --- a/include/sta/Mode.hh +++ b/include/sta/Mode.hh @@ -71,7 +71,7 @@ public: bool unique_edges, float min_slack, float max_slack, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, diff --git a/include/sta/Path.hh b/include/sta/Path.hh index bf938249..c7fcd081 100644 --- a/include/sta/Path.hh +++ b/include/sta/Path.hh @@ -204,8 +204,8 @@ public: const MinMax *min_max, const StaState *sta); virtual ~VertexPathIterator(); - virtual bool hasNext(); - virtual Path *next(); + bool hasNext() override; + Path *next() override; private: void findNext(); diff --git a/include/sta/PathEnd.hh b/include/sta/PathEnd.hh index 4f974f3f..ee8deb39 100644 --- a/include/sta/PathEnd.hh +++ b/include/sta/PathEnd.hh @@ -153,9 +153,13 @@ public: static bool less(const PathEnd *path_end1, const PathEnd *path_end2, + // Compare slack (if constrained), or arrival when false. + bool cmp_slack, const StaState *sta); static int cmp(const PathEnd *path_end1, const PathEnd *path_end2, + // Compare slack (if constrained), or arrival when false. + bool cmp_slack, const StaState *sta); static int cmpSlack(const PathEnd *path_end1, const PathEnd *path_end2, @@ -611,11 +615,13 @@ protected: class PathEndLess { public: - PathEndLess(const StaState *sta); + PathEndLess(bool cmp_slack, + const StaState *sta); bool operator()(const PathEnd *path_end1, const PathEnd *path_end2) const; protected: + bool cmp_slack_; const StaState *sta_; }; @@ -623,11 +629,13 @@ protected: class PathEndSlackLess { public: - PathEndSlackLess(const StaState *sta); + PathEndSlackLess(bool cmp_slack, + const StaState *sta); bool operator()(const PathEnd *path_end1, const PathEnd *path_end2) const; protected: + bool cmp_slack_; const StaState *sta_; }; diff --git a/include/sta/PathGroup.hh b/include/sta/PathGroup.hh index 836804f7..03bcb0c5 100644 --- a/include/sta/PathGroup.hh +++ b/include/sta/PathGroup.hh @@ -29,10 +29,12 @@ #include #include +#include "BoundedHeap.hh" #include "SdcClass.hh" #include "StaState.hh" #include "SearchClass.hh" #include "StringUtil.hh" +#include "PathEnd.hh" namespace sta { @@ -48,7 +50,6 @@ using PathGroupSeq = std::vector; class PathGroup { public: - ~PathGroup(); // Path group that compares compare slacks. static PathGroup *makePathGroupArrival(const char *name, int group_path_count, @@ -66,9 +67,9 @@ public: float min_slack, float max_slack, const StaState *sta); - const char *name() const { return name_.c_str(); } + const std::string &name() const { return name_; } const MinMax *minMax() const { return min_max_;} - const PathEndSeq &pathEnds() const { return path_ends_; } + PathEndSeq pathEnds() const; void insert(PathEnd *path_end); // Push group_path_count into path_ends. void pushEnds(PathEndSeq &path_ends); @@ -76,15 +77,14 @@ public: bool saveable(PathEnd *path_end); bool enumMinSlackUnderMin(PathEnd *path_end); int maxPaths() const { return group_path_count_; } - PathEndSeq &pathEnds() { return path_ends_; } // This does NOT delete the path ends. void clear(); - static size_t group_path_count_max; + static int group_path_count_max; protected: PathGroup(const char *name, - size_t group_path_count, - size_t endpoint_path_count, + int group_path_count, + int endpoint_path_count, bool unique_pins, bool unique_edges, float min_slack, @@ -92,21 +92,17 @@ protected: bool cmp_slack, const MinMax *min_max, const StaState *sta); - void ensureSortedMaxPaths(); - void prune(); - void sort(); std::string name_; - size_t group_path_count_; - size_t endpoint_path_count_; + int group_path_count_; + int endpoint_path_count_; bool unique_pins_; bool unique_edges_; float slack_min_; float slack_max_; - PathEndSeq path_ends_; const MinMax *min_max_; - bool compare_slack_; - float threshold_; + bool cmp_slack_; + BoundedHeap heap_; std::mutex lock_; const StaState *sta_; }; @@ -120,7 +116,7 @@ public: bool unique_edges, float slack_min, float slack_max, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, @@ -144,7 +140,7 @@ public: PathGroup *findPathGroup(const Clock *clock, const MinMax *min_max) const; PathGroupSeq pathGroups(const PathEnd *path_end) const; - static StdStringSeq pathGroupNames(const PathEnd *path_end, + static StringSeq pathGroupNames(const PathEnd *path_end, const StaState *sta); static const char *asyncPathGroupName() { return async_group_name_; } static const char *pathDelayGroupName() { return path_delay_group_name_; } @@ -184,17 +180,17 @@ protected: bool unique_edges, float slack_min, float slack_max, - StdStringSet &group_names, + StringSet &group_names, bool setup_hold, bool async, bool gated_clk, bool unconstrained, const MinMax *min_max); bool reportGroup(const char *group_name, - StdStringSet &group_names) const; + StringSet &group_names) const; static GroupPath *groupPathTo(const PathEnd *path_end, const StaState *sta); - StdStringSeq pathGroupNames(); + StringSeq pathGroupNames(); const Mode *mode_; int group_path_count_; diff --git a/include/sta/PowerClass.hh b/include/sta/PowerClass.hh index 5b1d36be..bedb018b 100644 --- a/include/sta/PowerClass.hh +++ b/include/sta/PowerClass.hh @@ -41,7 +41,6 @@ enum class PwrActivityOrigin propagated, clock, constant, - defaulted, unknown }; diff --git a/include/sta/Scene.hh b/include/sta/Scene.hh index 9b2e61a0..28986377 100644 --- a/include/sta/Scene.hh +++ b/include/sta/Scene.hh @@ -28,7 +28,6 @@ #include #include -#include "StringSeq.hh" #include "GraphClass.hh" #include "SearchClass.hh" diff --git a/include/sta/Sdc.hh b/include/sta/Sdc.hh index 31b363bd..add84e7f 100644 --- a/include/sta/Sdc.hh +++ b/include/sta/Sdc.hh @@ -30,7 +30,6 @@ #include #include "StringUtil.hh" -#include "StringSet.hh" #include "MinMax.hh" #include "StaState.hh" #include "NetworkClass.hh" @@ -149,7 +148,7 @@ using ExceptionPathPtHash = std::map; using ClockLatencies = std::set; using EdgeClockLatencyMap = std::map; using PinClockUncertaintyMap = std::map; -using InterClockUncertaintySet = std::set; +using InterClockUncertaintySet=std::set; using ClockGatingCheckMap = std::map; using InstanceClockGatingCheckMap = std::map; using PinClockGatingCheckMap = std::map; @@ -1306,6 +1305,7 @@ protected: bool clk_hpin_disables_valid_; PinSet propagated_clk_pins_; ClockLatencies clk_latencies_; + PinSet clk_latency_pins_; EdgeClockLatencyMap edge_clk_latency_map_; ClockInsertions clk_insertions_; PinClockUncertaintyMap pin_clk_uncertainty_map_; diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 4c98845c..ba4f8d0d 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -100,14 +100,14 @@ public: bool unconstrained, const SceneSeq &scenes, const MinMaxAll *min_max, - size_t group_path_count, - size_t endpoint_path_count, + int group_path_count, + int endpoint_path_count, bool unique_pins, bool unique_edges, float slack_min, float slack_max, bool sort_by_slack, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, diff --git a/include/sta/SearchClass.hh b/include/sta/SearchClass.hh index 65683966..c8f45627 100644 --- a/include/sta/SearchClass.hh +++ b/include/sta/SearchClass.hh @@ -29,7 +29,6 @@ #include #include "VectorMap.hh" -#include "StringSet.hh" #include "MinMaxValues.hh" #include "Delay.hh" #include "NetworkClass.hh" diff --git a/include/sta/Sta.hh b/include/sta/Sta.hh index b9ec5b00..74408227 100644 --- a/include/sta/Sta.hh +++ b/include/sta/Sta.hh @@ -29,7 +29,6 @@ #include #include -#include "StringSeq.hh" #include "StringUtil.hh" #include "LibertyClass.hh" #include "NetworkClass.hh" @@ -126,11 +125,11 @@ public: void setThreadCount(int thread_count); // define_corners compatibility. - void makeScenes(StringSeq *scene_names); + void makeScenes(const StringSeq &scene_names); void makeScene(const std::string &name, const std::string &mode_name, - const StdStringSeq &liberty_min_files, - const StdStringSeq &liberty_max_files, + const StringSeq &liberty_min_files, + const StringSeq &liberty_max_files, const std::string &spef_min_file, const std::string &spef_max_file); Scene *findScene(const std::string &name) const; @@ -653,7 +652,7 @@ public: const Sdc *sdc) __attribute__ ((deprecated)); bool isPathGroupName(const char *group_name, const Sdc *sdc) const; - StdStringSeq pathGroupNames(const Sdc *sdc) const; + StringSeq pathGroupNames(const Sdc *sdc) const; void resetPath(ExceptionFrom *from, ExceptionThruSeq *thrus, ExceptionTo *to, @@ -966,7 +965,7 @@ public: bool sort_by_slack, // Path groups to report. // Empty list reports all groups. - StdStringSeq &group_names, + StringSeq &group_names, // Predicates to filter the type of path // ends returned. bool setup, @@ -976,7 +975,7 @@ public: bool clk_gating_setup, bool clk_gating_hold); void setReportPathFormat(ReportPathFormat format); - void setReportPathFieldOrder(StringSeq *field_names); + void setReportPathFieldOrder(const StringSeq &field_names); void setReportPathFields(bool report_input_pin, bool report_hier_pins, bool report_net, @@ -1388,7 +1387,7 @@ public: LibertyLibrarySeq *map_libs); LibertyCellSeq *equivCells(LibertyCell *cell); - void writePathSpice(Path *path, + void writePathSpice(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, @@ -1588,8 +1587,8 @@ protected: void setThreadCount1(int thread_count); void updateLibertyScenes(); void updateSceneLiberty(Scene *scene, - const StdStringSeq &liberty_min_files, - const StdStringSeq &liberty_max_files); + const StringSeq &liberty_min_files, + const StringSeq &liberty_max_files); Scene *makeScene(const std::string &name, Mode *mode, diff --git a/include/sta/StringSeq.hh b/include/sta/StringSeq.hh deleted file mode 100644 index 9821b7b2..00000000 --- a/include/sta/StringSeq.hh +++ /dev/null @@ -1,38 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#pragma once - -#include - -#include "StringUtil.hh" - -namespace sta { - -using StringSeq = std::vector; - -void -deleteContents(StringSeq *strings); - -} // namespace diff --git a/include/sta/StringSet.hh b/include/sta/StringSet.hh deleted file mode 100644 index fc3d0d2b..00000000 --- a/include/sta/StringSet.hh +++ /dev/null @@ -1,38 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. -#pragma once - -#include - -#include "StringUtil.hh" - -namespace sta { - -using StringSet = std::set; -using StdStringSet = std::set; - -void -deleteContents(StringSet *strings); - -} // namespace diff --git a/include/sta/StringUtil.hh b/include/sta/StringUtil.hh index cdb9b1b7..b12ae00d 100644 --- a/include/sta/StringUtil.hh +++ b/include/sta/StringUtil.hh @@ -28,12 +28,14 @@ #include #include #include +#include #include "Machine.hh" // __attribute__ namespace sta { -using StdStringSeq = std::vector; +using StringSeq = std::vector; +using StringSet = std::set; inline bool stringEq(const char *str1, @@ -204,7 +206,7 @@ void trimRight(std::string &str); // Spit text into delimiter separated tokens and skip whitepace. -StdStringSeq +StringSeq parseTokens(const std::string &s, const char delimiter); diff --git a/include/sta/TclTypeHelpers.hh b/include/sta/TclTypeHelpers.hh index e521c4a9..a551c584 100644 --- a/include/sta/TclTypeHelpers.hh +++ b/include/sta/TclTypeHelpers.hh @@ -22,33 +22,24 @@ // // This notice may not be removed or altered from any source distribution. -#include "ArcDelayCalc.hh" -#include "StringSet.hh" -#include "StringSeq.hh" - #include +#include "ArcDelayCalc.hh" +#include "StringUtil.hh" + namespace sta { #if TCL_MAJOR_VERSION < 9 typedef int Tcl_Size; #endif -StringSet * -tclListSetConstChar(Tcl_Obj *const source, - Tcl_Interp *interp); - -StringSeq * -tclListSeqConstChar(Tcl_Obj *const source, - Tcl_Interp *interp); - -StdStringSeq +StringSeq tclListSeqStdString(Tcl_Obj *const source, Tcl_Interp *interp); -StdStringSeq * +StringSeq * tclListSeqStdStringPtr(Tcl_Obj *const source, Tcl_Interp *interp); -StdStringSet * +StringSet * tclListSetStdString(Tcl_Obj *const source, Tcl_Interp *interp); diff --git a/include/sta/Transition.hh b/include/sta/Transition.hh index 3f3e03c6..ba671453 100644 --- a/include/sta/Transition.hh +++ b/include/sta/Transition.hh @@ -48,8 +48,7 @@ public: static const RiseFall *fall() { return &fall_; } static int riseIndex() { return rise_.sdf_triple_index_; } static int fallIndex() { return fall_.sdf_triple_index_; } - const std::string &to_string_long() const { return name_; } - const std::string &to_string() const { return short_name_; } + const std::string &to_string(bool use_short = false) const; const char *name() const { return name_.c_str(); } const char *shortName() const { return short_name_.c_str(); } int index() const { return sdf_triple_index_; } @@ -94,7 +93,7 @@ public: static const RiseFallBoth *rise() { return &rise_; } static const RiseFallBoth *fall() { return &fall_; } static const RiseFallBoth *riseFall() { return &rise_fall_; } - const std::string &to_string() const { return short_name_; } + const std::string &to_string(bool use_short = false) const; const char *name() const { return name_.c_str(); } const char *shortName() const { return short_name_.c_str(); } int index() const { return sdf_triple_index_; } diff --git a/include/sta/VerilogReader.hh b/include/sta/VerilogReader.hh index 2b244d0c..e3aa94fa 100644 --- a/include/sta/VerilogReader.hh +++ b/include/sta/VerilogReader.hh @@ -28,7 +28,7 @@ #include #include -#include "StringSet.hh" +#include "StringUtil.hh" #include "NetworkClass.hh" namespace sta { @@ -173,7 +173,7 @@ protected: void makeNamedPortRefCellPorts(Cell *cell, VerilogModule *module, VerilogNet *mod_port, - StdStringSet &port_names); + StringSet &port_names); void checkModuleDcls(VerilogModule *module, std::set &port_names); void makeModuleInstBody(VerilogModule *module, diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 181b0e42..825502f6 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -31,7 +31,6 @@ #include "Debug.hh" #include "Error.hh" #include "StringUtil.hh" -#include "StringSet.hh" #include "PatternMatch.hh" #include "Units.hh" #include "Transition.hh" @@ -1367,17 +1366,14 @@ LibertyCell::makeTimingArcPortMaps() LibertyPort *from = arc_set->from(); LibertyPort *to = arc_set->to(); if (from && to) { - LibertyPortPair from_to_pair(from, to); - TimingArcSetSeq &sets = port_timing_arc_set_map_[from_to_pair]; + TimingArcSetSeq &sets = port_timing_arc_set_map_[{from, to}]; sets.push_back(arc_set); } - LibertyPortPair from_pair(from, nullptr); - TimingArcSetSeq &from_sets = port_timing_arc_set_map_[from_pair]; + TimingArcSetSeq &from_sets = port_timing_arc_set_map_[{from, nullptr}]; from_sets.push_back(arc_set); - LibertyPortPair to_pair(nullptr, to); - TimingArcSetSeq &to_sets = port_timing_arc_set_map_[to_pair]; + TimingArcSetSeq &to_sets = port_timing_arc_set_map_[{nullptr, to}]; to_sets.push_back(arc_set); const TimingRole *role = arc_set->role(); @@ -1411,8 +1407,7 @@ LibertyCell::timingArcSets(const LibertyPort *from, const LibertyPort *to) const { static const TimingArcSetSeq null_set; - const LibertyPortPair port_pair(from, to); - auto itr = port_timing_arc_set_map_.find(port_pair); + auto itr = port_timing_arc_set_map_.find({from, to}); return (itr == port_timing_arc_set_map_.end()) ? null_set : itr->second; } @@ -1437,8 +1432,8 @@ LibertyCell::timingArcSetCount() const bool LibertyCell::hasTimingArcs(LibertyPort *port) const { - return port_timing_arc_set_map_.contains(LibertyPortPair(port, nullptr)) - || port_timing_arc_set_map_.contains(LibertyPortPair(nullptr, port)); + return port_timing_arc_set_map_.contains({port, nullptr}) + || port_timing_arc_set_map_.contains({nullptr, port}); } void diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 6851b501..5d99d1f1 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -78,8 +78,7 @@ LibertyReader::LibertyReader(const char *filename, debug_(network->debug()), network_(network), builder_(debug_, report_), - library_(nullptr), - first_cell_(true) + library_(nullptr) { defineVisitors(); } @@ -148,13 +147,13 @@ LibertyReader::beginLibrary(const LibertyGroup *library_group, } void -LibertyReader::endLibrary(const LibertyGroup *group, +LibertyReader::endLibrary(const LibertyGroup *library_group, LibertyGroup *) { - // If a library hasno cells endCell is not called. - if (first_cell_) - readLibraryAttributes(group); - delete group; + // If a library has no cells endCell is not called. + readLibraryAttributes(library_group); + checkThresholds(library_group); + delete library_group; } //////////////////////////////////////////////////////////////// @@ -167,12 +166,7 @@ LibertyReader::endCell(const LibertyGroup *cell_group, // Normally they are all defined by the first cell, but there // are libraries that define table templates and bus tyupes // between cells. - if (first_cell_) - readLibraryAttributes(library_group); - else { - readTableTemplates(library_group); - readBusTypes(nullptr, library_group); - } + readLibraryAttributes(library_group); const char *name = cell_group->firstName(); if (name) { @@ -182,8 +176,10 @@ LibertyReader::endCell(const LibertyGroup *cell_group, } else libWarn(1193, cell_group, "cell missing name."); + + // Delete the cell group and preceding library attributes + // and groups so they are not revisited and reduce memory peak. library_group->clear(); - first_cell_ = false; } void @@ -524,24 +520,28 @@ void LibertyReader::readThresholds(const LibertyGroup *library_group) { for (const RiseFall *rf : RiseFall::range()) { - std::string suffix = rf->to_string_long(); + std::string suffix = rf->to_string(); readLibAttrFloat(library_group, ("input_threshold_pct_" + suffix).c_str(), &LibertyLibrary::setInputThreshold, rf, 0.01F); - if (library_->inputThreshold(rf) == 0.0) - libWarn(1145, library_group, "input_threshold_pct_%s not found.", rf->name()); - readLibAttrFloat(library_group, ("output_threshold_pct_" + suffix).c_str(), &LibertyLibrary::setOutputThreshold, rf, 0.01F); - if (library_->outputThreshold(rf) == 0.0) - libWarn(1146, library_group, "output_threshold_pct_%s not found.", rf->name()); - readLibAttrFloat(library_group, ("slew_lower_threshold_pct_" + suffix).c_str(), &LibertyLibrary::setSlewLowerThreshold, rf, 0.01F); - if (library_->slewLowerThreshold(rf) == 0.0) - libWarn(1147, library_group, "slew_lower_threshold_pct_%s not found.", rf->name()); - readLibAttrFloat(library_group, ("slew_upper_threshold_pct_" + suffix).c_str(), &LibertyLibrary::setSlewUpperThreshold, rf, 0.01F); + } +} + +void +LibertyReader::checkThresholds(const LibertyGroup *library_group) const +{ + for (const RiseFall *rf : RiseFall::range()) { + if (library_->inputThreshold(rf) == 0.0) + libWarn(1145, library_group, "input_threshold_pct_%s not found.", rf->name()); + if (library_->outputThreshold(rf) == 0.0) + libWarn(1146, library_group, "output_threshold_pct_%s not found.", rf->name()); + if (library_->slewLowerThreshold(rf) == 0.0) + libWarn(1147, library_group, "slew_lower_threshold_pct_%s not found.", rf->name()); if (library_->slewUpperThreshold(rf) == 0.0) libWarn(1148, library_group, "slew_upper_threshold_pct_%s not found.", rf->name()); } @@ -907,7 +907,7 @@ void LibertyReader::readSlewDegradations(const LibertyGroup *library_group) { for (const RiseFall *rf : RiseFall::range()) { - const std::string group_name = rf->to_string_long() + "_transition_degradation"; + const std::string group_name = rf->to_string() + "_transition_degradation"; const LibertyGroup *degradation_group = library_group->findSubgroup(group_name.c_str()); if (degradation_group) { @@ -1480,7 +1480,7 @@ LibertyReader::readCapacitance(const LibertyPortSeq &ports, for (LibertyPort *port : ports) { // rise/fall_capacitance for (const RiseFall *rf : RiseFall::range()) { - std::string attr_name = rf->to_string_long() + "_capacitance"; + std::string attr_name = rf->to_string() + "_capacitance"; float cap; bool exists; port_group->findAttrFloat(attr_name, cap, exists); @@ -1490,7 +1490,7 @@ LibertyReader::readCapacitance(const LibertyPortSeq &ports, } // rise/fall_capacitance_range(min_cap, max_cap); - attr_name = rf->to_string_long() + "_capacitance_range"; + attr_name = rf->to_string() + "_capacitance_range"; const LibertyComplexAttrSeq &range_attrs = port_group->findComplexAttrs(attr_name); if (!range_attrs.empty()) { const LibertyComplexAttr *attr = range_attrs[0]; @@ -1894,8 +1894,8 @@ LibertyReader::makeTimingArcs(LibertyCell *cell, LibertyPort *related_output_port = findLibertyPort(cell, timing_group, "related_output_pin"); - StdStringSeq related_port_names = findAttributStrings(timing_group, "related_pin"); - StdStringSeq related_bus_names=findAttributStrings(timing_group,"related_bus_pins"); + StringSeq related_port_names = findAttributStrings(timing_group, "related_pin"); + StringSeq related_bus_names=findAttributStrings(timing_group,"related_bus_pins"); TimingType timing_type = timing_attrs->timingType(); for (LibertyPort *to_port : ports) { @@ -2081,7 +2081,7 @@ LibertyReader::makeLinearModels(LibertyCell *cell, { LibertyLibrary *library = cell->libertyLibrary(); for (const RiseFall *rf : RiseFall::range()) { - std::string intr_attr_name = "intrinsic_" + rf->to_string_long(); + std::string intr_attr_name = "intrinsic_" + rf->to_string(); float intr = 0.0; bool intr_exists; timing_group->findAttrFloat(intr_attr_name, intr, intr_exists); @@ -2094,7 +2094,7 @@ LibertyReader::makeLinearModels(LibertyCell *cell, if (timingTypeIsCheck(timing_attrs->timingType())) model = new CheckLinearModel(cell, intr); else { - std::string res_attr_name = rf->to_string_long() + "_resistance"; + std::string res_attr_name = rf->to_string() + "_resistance"; float res = 0.0; bool res_exists; timing_group->findAttrFloat(res_attr_name, res, res_exists); @@ -2117,18 +2117,18 @@ LibertyReader::makeTableModels(LibertyCell *cell, { bool found_model = false; for (const RiseFall *rf : RiseFall::range()) { - std::string delay_attr_name = "cell_" + rf->to_string_long(); + std::string delay_attr_name = "cell_" + rf->to_string(); TableModel *delay = readGateTableModel(timing_group, delay_attr_name.c_str(), rf, TableTemplateType::delay, time_scale_, ScaleFactorType::cell); - std::string transition_attr_name = rf->to_string_long() + "_transition"; + std::string transition_attr_name = rf->to_string() + "_transition"; TableModel *transition = readGateTableModel(timing_group, transition_attr_name.c_str(), rf, TableTemplateType::delay, time_scale_, ScaleFactorType::transition); if (delay || transition) { - std::string delay_sigma_attr_name = "ocv_sigma_cell_" + rf->to_string_long(); + std::string delay_sigma_attr_name = "ocv_sigma_cell_" + rf->to_string(); TableModelsEarlyLate delay_sigmas = readEarlyLateTableModels(timing_group, delay_sigma_attr_name.c_str(), @@ -2136,7 +2136,7 @@ LibertyReader::makeTableModels(LibertyCell *cell, time_scale_, ScaleFactorType::unknown); - std::string slew_sigma_attr_name = "ocv_sigma_" + rf->to_string_long() + std::string slew_sigma_attr_name = "ocv_sigma_" + rf->to_string() + "_transition"; TableModelsEarlyLate slew_sigmas = readEarlyLateTableModels(timing_group, @@ -2164,7 +2164,7 @@ LibertyReader::makeTableModels(LibertyCell *cell, found_model = true; } else { - std::string constraint_attr_name = rf->to_string_long() + "_constraint"; + std::string constraint_attr_name = rf->to_string() + "_constraint"; ScaleFactorType scale_factor_type = timingTypeScaleFactorType(timing_attrs->timingType()); TableModel *constraint = readCheckTableModel(timing_group, @@ -2172,7 +2172,7 @@ LibertyReader::makeTableModels(LibertyCell *cell, rf, TableTemplateType::delay, time_scale_, scale_factor_type); if (constraint) { - std::string constraint_sigma_attr_name = "ocv_sigma_" + rf->to_string_long() + std::string constraint_sigma_attr_name = "ocv_sigma_" + rf->to_string() + "_constraint"; TableModelsEarlyLate constraint_sigmas = readEarlyLateTableModels(timing_group, @@ -2298,7 +2298,7 @@ LibertyReader::readReceiverCapacitance(const LibertyGroup *timing_group, ReceiverModelPtr &receiver_model) { std::string cap_group_name1 = cap_group_name; - cap_group_name1 += "_" + rf->to_string_long(); + cap_group_name1 += "_" + rf->to_string(); const LibertyGroup *cap_group = timing_group->findSubgroup(cap_group_name1); if (cap_group) { const LibertySimpleAttr *segment_attr = cap_group->findSimpleAttr("segment"); @@ -2328,7 +2328,7 @@ OutputWaveforms * LibertyReader::readOutputWaveforms(const LibertyGroup *timing_group, const RiseFall *rf) { - const std::string current_group_name = "output_current_" + rf->to_string_long(); + const std::string current_group_name = "output_current_" + rf->to_string(); const LibertyGroup *current_group = timing_group->findSubgroup(current_group_name); if (current_group) { OutputWaveformSeq output_currents; @@ -2680,7 +2680,7 @@ LibertyReader::readInternalPowerGroups(LibertyCell *cell, InternalPowerModels models; // rise/fall_power group for (const RiseFall *rf : RiseFall::range()) { - std::string pwr_attr_name = rf->to_string_long() + "_power"; + std::string pwr_attr_name = rf->to_string() + "_power"; const LibertyGroup *pwr_group = ipwr_group->findSubgroup(pwr_attr_name); if (pwr_group) { TableModel *model = readTableModel(pwr_group, rf, TableTemplateType::power, @@ -2743,7 +2743,7 @@ LibertyReader::findLibertyPort(LibertyCell *cell, return nullptr; } -StdStringSeq +StringSeq LibertyReader::findAttributStrings(const LibertyGroup *group, const char *name_attr) { @@ -2754,7 +2754,7 @@ LibertyReader::findAttributStrings(const LibertyGroup *group, return parseTokens(*strings, ' '); } } - return StdStringSeq(); + return StringSeq(); } LibertyPortSeq @@ -2763,7 +2763,7 @@ LibertyReader::findLibertyPorts(LibertyCell *cell, const char *port_name_attr) { LibertyPortSeq ports; - StdStringSeq port_names = findAttributStrings(group, port_name_attr); + StringSeq port_names = findAttributStrings(group, port_name_attr); for (const std::string &port_name : port_names) { LibertyPort *port = findPort(cell, port_name.c_str()); if (port) @@ -2915,40 +2915,40 @@ LibertyReader::readStatetable(LibertyCell *cell, const char *input_ports_arg = statetable_group->firstName(); const char *internal_ports_arg = statetable_group->params().size() >= 2 ? statetable_group->secondName() : nullptr; - StdStringSeq input_ports; + StringSeq input_ports; if (input_ports_arg) input_ports = parseTokens(input_ports_arg, ' '); - StdStringSeq internal_ports; + StringSeq internal_ports; if (internal_ports_arg) internal_ports = parseTokens(internal_ports_arg, ' '); const LibertySimpleAttr *table_attr = statetable_group->findSimpleAttr("table"); if (table_attr) { const std::string *table_str = table_attr->stringValue(); - StdStringSeq table_rows = parseTokens(table_str->c_str(), ','); + StringSeq table_rows = parseTokens(table_str->c_str(), ','); size_t input_count = input_ports.size(); size_t internal_count = internal_ports.size(); StatetableRows table; for (const std::string &row : table_rows) { - const StdStringSeq row_groups = parseTokens(row, ':'); + const StringSeq row_groups = parseTokens(row, ':'); if (row_groups.size() != 3) { libWarn(1300, table_attr, "table row must have 3 groups separated by ':'."); break; } - StdStringSeq inputs = parseTokens(row_groups[0], ' '); + StringSeq inputs = parseTokens(row_groups[0], ' '); if (inputs.size() != input_count) { libWarn(1301,table_attr,"table row has %zu input values but %zu are required.", inputs.size(), input_count); break; } - StdStringSeq currents = parseTokens(row_groups[1], ' '); + StringSeq currents = parseTokens(row_groups[1], ' '); if (currents.size() != internal_count) { libWarn(1302,table_attr, "table row has %zu current values but %zu are required.", currents.size(), internal_count); break; } - StdStringSeq nexts = parseTokens(row_groups[2], ' '); + StringSeq nexts = parseTokens(row_groups[2], ' '); if (nexts.size() != internal_count) { libWarn(1303, table_attr, "table row has %zu next values but %zu are required.", nexts.size(), internal_count); @@ -3087,7 +3087,7 @@ static EnumNameMap state_internal_value_name_map = }; StateInputValues -LibertyReader::parseStateInputValues(StdStringSeq &inputs, +LibertyReader::parseStateInputValues(StringSeq &inputs, const LibertySimpleAttr *attr) { StateInputValues input_values; @@ -3106,7 +3106,7 @@ LibertyReader::parseStateInputValues(StdStringSeq &inputs, } StateInternalValues -LibertyReader::parseStateInternalValues(StdStringSeq &states, +LibertyReader::parseStateInternalValues(StringSeq &states, const LibertySimpleAttr *attr) { StateInternalValues state_values; @@ -3458,37 +3458,37 @@ LibertyReader::variableValue(const char *var, void LibertyReader::libWarn(int id, - const LibertyGroup *obj, + const LibertyGroup *group, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileWarn(id, filename_, obj->line(), fmt, args); + report_->vfileWarn(id, filename_, group->line(), fmt, args); va_end(args); } void LibertyReader::libWarn(int id, - const LibertySimpleAttr *obj, + const LibertySimpleAttr *attr, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileWarn(id, filename_, obj->line(), fmt, args); + report_->vfileWarn(id, filename_, attr->line(), fmt, args); va_end(args); } void LibertyReader::libWarn(int id, - const LibertyComplexAttr *obj, + const LibertyComplexAttr *attr, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileWarn(id, filename_, obj->line(), fmt, args); + report_->vfileWarn(id, filename_, attr->line(), fmt, args); va_end(args); } @@ -3496,7 +3496,7 @@ void LibertyReader::libWarn(int id, int line, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); @@ -3506,37 +3506,37 @@ LibertyReader::libWarn(int id, void LibertyReader::libError(int id, - const LibertyGroup *obj, + const LibertyGroup *group, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileError(id, filename_, obj->line(), fmt, args); + report_->vfileError(id, filename_, group->line(), fmt, args); va_end(args); } void LibertyReader::libError(int id, - const LibertySimpleAttr *obj, + const LibertySimpleAttr *attr, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileError(id, filename_, obj->line(), fmt, args); + report_->vfileError(id, filename_, attr->line(), fmt, args); va_end(args); } void LibertyReader::libError(int id, - const LibertyComplexAttr *obj, + const LibertyComplexAttr *attr, const char *fmt, - ...) + ...) const { va_list args; va_start(args, fmt); - report_->vfileError(id, filename_, obj->line(), fmt, args); + report_->vfileError(id, filename_, attr->line(), fmt, args); va_end(args); } diff --git a/liberty/LibertyReaderPvt.hh b/liberty/LibertyReaderPvt.hh index c17cdeb8..9cfca58b 100644 --- a/liberty/LibertyReaderPvt.hh +++ b/liberty/LibertyReaderPvt.hh @@ -24,13 +24,13 @@ #pragma once +#include #include #include #include #include #include -#include "StringSeq.hh" #include "StringUtil.hh" #include "MinMax.hh" #include "NetworkClass.hh" @@ -101,7 +101,7 @@ public: LibertyPort *findPort(LibertyCell *cell, const char *port_name); - StdStringSeq findAttributStrings(const LibertyGroup *group, + StringSeq findAttributStrings(const LibertyGroup *group, const char *name_attr); protected: @@ -132,6 +132,7 @@ protected: const char *group_name, TableTemplateType type); void readThresholds(const LibertyGroup *library_group); + void checkThresholds(const LibertyGroup *library_group) const; TableAxisPtr makeTableTemplateAxis(const LibertyGroup *template_group, int axis_index); void readVoltateMaps(const LibertyGroup *library_group); @@ -401,9 +402,9 @@ protected: float defaultCap(LibertyPort *port); void visitPorts(std::function func); - StateInputValues parseStateInputValues(StdStringSeq &inputs, + StateInputValues parseStateInputValues(StringSeq &inputs, const LibertySimpleAttr *attr); - StateInternalValues parseStateInternalValues(StdStringSeq &states, + StateInternalValues parseStateInternalValues(StringSeq &states, const LibertySimpleAttr *attr); void getAttrInt(const LibertySimpleAttr *attr, @@ -445,36 +446,36 @@ protected: const LibertyCell *cell, int line); void libWarn(int id, - const LibertyGroup *obj, + const LibertyGroup *group, const char *fmt, - ...) + ...) const __attribute__((format (printf, 4, 5))); void libWarn(int id, - const LibertySimpleAttr *obj, + const LibertySimpleAttr *attr, const char *fmt, - ...) + ...) const __attribute__((format (printf, 4, 5))); void libWarn(int id, - const LibertyComplexAttr *obj, + const LibertyComplexAttr *attr, const char *fmt, - ...) + ...) const __attribute__((format (printf, 4, 5))); void libWarn(int id, int line, const char *fmt, - ...) + ...) const __attribute__((format (printf, 4, 5))); void libError(int id, - const LibertyGroup *obj, - const char *fmt, ...) + const LibertyGroup *group, + const char *fmt, ...) const __attribute__((format (printf, 4, 5))); void libError(int id, - const LibertySimpleAttr *obj, - const char *fmt, ...) + const LibertySimpleAttr *attr, + const char *fmt, ...) const __attribute__((format (printf, 4, 5))); void libError(int id, - const LibertyComplexAttr *obj, - const char *fmt, ...) + const LibertyComplexAttr *attr, + const char *fmt, ...) const __attribute__((format (printf, 4, 5))); const char *filename_; @@ -485,7 +486,6 @@ protected: LibertyBuilder builder_; LibertyVariableMap var_map_; LibertyLibrary *library_; - bool first_cell_; LibraryGroupVisitorMap group_begin_map_; LibraryGroupVisitorMap group_end_map_; @@ -516,8 +516,8 @@ public: LibertyReader *visitor, int line); ~PortNameBitIterator(); - virtual bool hasNext(); - virtual LibertyPort *next(); + bool hasNext() override; + LibertyPort *next() override; unsigned size() const { return size_; } protected: diff --git a/network/ConcreteNetwork.cc b/network/ConcreteNetwork.cc index 22fd122d..a6a0f65d 100644 --- a/network/ConcreteNetwork.cc +++ b/network/ConcreteNetwork.cc @@ -62,8 +62,8 @@ class ConcreteInstanceChildIterator : public InstanceChildIterator { public: ConcreteInstanceChildIterator(ConcreteInstanceChildMap *map); - bool hasNext(); - Instance *next(); + bool hasNext() override; + Instance *next() override; private: ConcreteInstanceChildMap *map_; @@ -96,8 +96,8 @@ class ConcreteInstanceNetIterator : public InstanceNetIterator { public: ConcreteInstanceNetIterator(ConcreteInstanceNetMap *nets); - bool hasNext(); - Net *next(); + bool hasNext() override; + Net *next() override; private: void findNext(); @@ -152,8 +152,8 @@ class ConcreteInstancePinIterator : public InstancePinIterator public: ConcreteInstancePinIterator(const ConcreteInstance *inst, int pin_count); - bool hasNext(); - Pin *next(); + bool hasNext() override; + Pin *next() override; private: void findNext(); @@ -206,8 +206,8 @@ class ConcreteNetPinIterator : public NetPinIterator { public: ConcreteNetPinIterator(const ConcreteNet *net); - bool hasNext(); - Pin *next(); + bool hasNext() override; + Pin *next() override; private: ConcretePin *next_; @@ -238,8 +238,8 @@ class ConcreteNetTermIterator : public NetTermIterator { public: ConcreteNetTermIterator(const ConcreteNet *net); - bool hasNext(); - Term *next(); + bool hasNext() override; + Term *next() override; private: ConcreteTerm *next_; @@ -322,8 +322,8 @@ class ConcreteLibraryIterator1 : public Iterator { public: ConcreteLibraryIterator1(const ConcreteLibrarySeq &libs); - virtual bool hasNext(); - virtual Library *next(); + bool hasNext() override; + Library *next() override; private: const ConcreteLibrarySeq &libs_; @@ -361,8 +361,8 @@ class ConcreteLibertyLibraryIterator : public Iterator public: ConcreteLibertyLibraryIterator(const ConcreteNetwork *network); virtual ~ConcreteLibertyLibraryIterator(); - virtual bool hasNext(); - virtual LibertyLibrary *next(); + bool hasNext() override; + LibertyLibrary *next() override; private: void findNext(); @@ -719,8 +719,8 @@ class ConcreteCellPortIterator1 : public CellPortIterator public: ConcreteCellPortIterator1(const ConcreteCell *cell); ~ConcreteCellPortIterator1(); - virtual bool hasNext() { return iter_->hasNext(); } - virtual Port *next(); + bool hasNext() override { return iter_->hasNext(); } + Port *next() override; private: ConcreteCellPortIterator *iter_; @@ -756,8 +756,8 @@ class ConcreteCellPortBitIterator1 : public CellPortIterator public: ConcreteCellPortBitIterator1(const ConcreteCell *cell); ~ConcreteCellPortBitIterator1(); - virtual bool hasNext() { return iter_->hasNext(); } - virtual Port *next(); + bool hasNext() override { return iter_->hasNext(); } + Port *next() override; private: ConcreteCellPortBitIterator *iter_; @@ -903,8 +903,8 @@ class ConcretePortMemberIterator1 : public PortMemberIterator public: ConcretePortMemberIterator1(const ConcretePort *port); ~ConcretePortMemberIterator1(); - virtual bool hasNext(); - virtual Port *next(); + bool hasNext() override; + Port *next() override; private: ConcretePortMemberIterator *iter_; diff --git a/network/Network.cc b/network/Network.cc index 78e13b1e..ec77fa7a 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -1221,8 +1221,8 @@ class LeafInstanceIterator1 : public LeafInstanceIterator public: LeafInstanceIterator1(const Instance *inst, const Network *network); - bool hasNext() { return next_; } - Instance *next(); + bool hasNext() override { return next_; } + Instance *next() override; private: void nextInst(); @@ -1366,8 +1366,8 @@ class ConnectedPinIterator1 : public ConnectedPinIterator public: ConnectedPinIterator1(PinSet *pins); virtual ~ConnectedPinIterator1(); - virtual bool hasNext(); - virtual const Pin *next(); + bool hasNext() override; + const Pin *next() override; protected: PinSet *pins_; diff --git a/network/Network.i b/network/Network.i index 349e9405..4334f648 100644 --- a/network/Network.i +++ b/network/Network.i @@ -638,13 +638,16 @@ InstancePinIterator * pin_iterator() { return Sta::sta()->ensureLinked()->pinIterator(self); } InstanceNetIterator * net_iterator() { return Sta::sta()->ensureLinked()->netIterator(self); } + Pin * find_pin(const char *name) { return Sta::sta()->ensureLinked()->findPin(self, name); } + std::string -get_attribute(const char *key) { +get_attribute(const char *key) +{ return Sta::sta()->ensureLinked()->getAttribute(self, key); } diff --git a/parasitics/ReduceParasitics.cc b/parasitics/ReduceParasitics.cc index 311ef35c..f44b1a9f 100644 --- a/parasitics/ReduceParasitics.cc +++ b/parasitics/ReduceParasitics.cc @@ -311,7 +311,7 @@ reduceToPiElmore(const Parasitic *parasitic_network, if (drvr_node) { debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s %s %s", sta->network()->pathName(drvr_pin), - rf->to_string().c_str(), + rf->shortName(), min_max->to_string().c_str()); ReduceToPiElmore reducer(sta); return reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node, diff --git a/parasitics/SpefParse.yy b/parasitics/SpefParse.yy index 39ad246f..921db703 100755 --- a/parasitics/SpefParse.yy +++ b/parasitics/SpefParse.yy @@ -27,7 +27,7 @@ #include "Report.hh" #include "StringUtil.hh" -#include "StringSeq.hh" +#include "StringUtil.hh" #include "parasitics/SpefReaderPvt.hh" #include "parasitics/SpefScanner.hh" @@ -62,7 +62,7 @@ sta::SpefParse::error(const location_type &loc, char *string; int integer; float number; - sta::StringSeq *string_seq; + sta::StringSeq *std_string_seq; sta::PortDirection *port_dir; sta::SpefRspfPi *pi; sta::SpefTriple *triple; @@ -105,7 +105,7 @@ sta::SpefParse::error(const location_type &loc, %type hchar suffix_bus_delim prefix_bus_delim -%type qstrings +%type qstrings %type direction %type par_value total_cap @@ -222,9 +222,12 @@ qstrings: QSTRING { $$ = new sta::StringSeq; $$->push_back($1); + sta::stringDelete($1); } | qstrings QSTRING - { $$->push_back($2); } + { $$->push_back($2); + sta::stringDelete($2); + } ; hierarchy_div_def: diff --git a/parasitics/SpefReader.cc b/parasitics/SpefReader.cc index 7d0751f8..77dea552 100644 --- a/parasitics/SpefReader.cc +++ b/parasitics/SpefReader.cc @@ -92,7 +92,6 @@ SpefReader::SpefReader(const std::string &filename, cap_scale_(1.0), res_scale_(1.0), induct_scale_(1.0), - design_flow_(nullptr), parasitics_(parasitics), parasitic_(nullptr) { @@ -101,11 +100,6 @@ SpefReader::SpefReader(const std::string &filename, SpefReader::~SpefReader() { - if (design_flow_) { - deleteContents(design_flow_); - delete design_flow_; - design_flow_ = nullptr; - } } bool @@ -299,7 +293,8 @@ SpefReader::portDirection(char *spef_dir) void SpefReader::setDesignFlow(StringSeq *flow) { - design_flow_ = flow; + design_flow_ = std::move(*flow); + delete flow; } Pin * diff --git a/parasitics/SpefReaderPvt.hh b/parasitics/SpefReaderPvt.hh index f96480c4..2ddb52ad 100644 --- a/parasitics/SpefReaderPvt.hh +++ b/parasitics/SpefReaderPvt.hh @@ -27,7 +27,7 @@ #include #include "Zlib.hh" -#include "StringSeq.hh" +#include "StringUtil.hh" #include "NetworkClass.hh" #include "ParasiticsClass.hh" #include "StaState.hh" @@ -139,7 +139,7 @@ private: float res_scale_; float induct_scale_; SpefNameMap name_map_; - StringSeq *design_flow_; + StringSeq design_flow_; Parasitics *parasitics_; Parasitic *parasitic_; }; diff --git a/power/Power.cc b/power/Power.cc index f0b590fa..38d1dea1 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -86,7 +86,6 @@ static EnumNameMap pwr_activity_origin_map = {PwrActivityOrigin::propagated, "propagated"}, {PwrActivityOrigin::clock, "clock"}, {PwrActivityOrigin::constant, "constant"}, - {PwrActivityOrigin::defaulted, "defaulted"}, {PwrActivityOrigin::unknown, "unknown"}}; Power::Power(StaState *sta) : diff --git a/sdc/Clock.cc b/sdc/Clock.cc index 3960f670..1b39e585 100644 --- a/sdc/Clock.cc +++ b/sdc/Clock.cc @@ -531,7 +531,7 @@ ClockEdge::ClockEdge(Clock *clock, const RiseFall *rf) : clock_(clock), rf_(rf), - name_(stringPrint("%s %s", clock_->name(), rf_->to_string().c_str())), + name_(stringPrint("%s %s", clock_->name(), rf_->shortName())), time_(0.0), index_(clock_->index() * RiseFall::index_count + rf_->index()) { diff --git a/sdc/DisabledPorts.cc b/sdc/DisabledPorts.cc index 99c99350..0e736b9d 100644 --- a/sdc/DisabledPorts.cc +++ b/sdc/DisabledPorts.cc @@ -96,18 +96,15 @@ DisabledPorts::setDisabledFromTo(LibertyPort *from, { if (from_to_ == nullptr) from_to_ = new LibertyPortPairSet; - LibertyPortPair pair(from, to); - from_to_->insert(pair); + from_to_->insert({from, to}); } void DisabledPorts::removeDisabledFromTo(LibertyPort *from, LibertyPort *to) { - if (from_to_) { - LibertyPortPair from_to(from, to); - from_to_->erase(from_to); - } + if (from_to_) + from_to_->erase({from, to}); } bool @@ -115,12 +112,11 @@ DisabledPorts::isDisabled(LibertyPort *from, LibertyPort *to, const TimingRole *role) { - LibertyPortPair from_to(from, to); // set_disable_timing instance does not disable timing checks. return (all_ && !role->isTimingCheck()) || (from_ && from_->contains(from)) || (to_ && to_->contains(to)) - || (from_to_ && from_to_->contains(from_to)); + || (from_to_ && from_to_->contains({from, to})); } //////////////////////////////////////////////////////////////// diff --git a/sdc/ExceptionPath.cc b/sdc/ExceptionPath.cc index 25ba0d78..8849d9c5 100644 --- a/sdc/ExceptionPath.cc +++ b/sdc/ExceptionPath.cc @@ -2427,8 +2427,7 @@ void InsertPinPairsThru::visit(const Pin *drvr, const Pin *load) { - PinPair pair(drvr, load); - pairs_->insert(pair); + pairs_->insert({drvr, load}); } static void @@ -2475,8 +2474,7 @@ void DeletePinPairsThru::visit(const Pin *drvr, const Pin *load) { - PinPair pair(drvr, load); - pairs_->erase(pair); + pairs_->erase({drvr, load}); } static void diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 001d7567..7517020d 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -101,6 +101,7 @@ Sdc::Sdc(Mode *mode, clk_hpin_disables_(network_), propagated_clk_pins_(network_), clk_latencies_(network_), + clk_latency_pins_(network_), edge_clk_latency_map_(network_), clk_insertions_(network_), clk_sense_map_(network_), @@ -169,6 +170,7 @@ Sdc::clear() clock_pin_map_.clear(); clock_leaf_pin_map_.clear(); clk_latencies_.clear(); + clk_latency_pins_.clear(); edge_clk_latency_map_.clear(); clk_insertions_.clear(); @@ -1344,8 +1346,7 @@ bool FindClkHpinDisables::drvrLoadExists(const Pin *drvr, const Pin *load) { - PinPair probe(drvr, load); - return drvr_loads_.contains(probe); + return drvr_loads_.contains({drvr, load}); } void @@ -1508,6 +1509,8 @@ Sdc::setClockLatency(Clock *clk, } } latency->setDelay(rf, min_max, delay); + if (pin) + clk_latency_pins_.insert(pin); // set_clock_latency removes set_propagated_clock on the same object. if (clk && pin == nullptr) @@ -1580,8 +1583,7 @@ Sdc::deleteClockLatenciesReferencing(Clock *clk) bool Sdc::hasClockLatency(const Pin *pin) const { - ClockLatency probe(nullptr, pin); - return clk_latencies_.contains(&probe); + return clk_latency_pins_.contains(pin); } void @@ -3503,24 +3505,21 @@ void Sdc::disableWire(const Pin *from, const Pin *to) { - PinPair pair(from, to); - disabled_wire_edges_.insert(pair); + disabled_wire_edges_.insert({from, to}); } void Sdc::removeDisableWire(Pin *from, Pin *to) { - PinPair probe(from, to); - disabled_wire_edges_.erase(probe); + disabled_wire_edges_.erase({from, to}); } bool Sdc::isDisabledWire(const Pin *from, const Pin *to) const { - PinPair pair(from, to); - return disabled_wire_edges_.contains(pair); + return disabled_wire_edges_.contains({from, to}); } void @@ -3580,8 +3579,7 @@ void DisableEdgesThruHierPin::visit(const Pin *drvr, const Pin *load) { - PinPair pair(drvr, load); - pairs_->insert(pair); + pairs_->insert({drvr, load}); } void @@ -3622,8 +3620,7 @@ void RemoveDisableEdgesThruHierPin::visit(const Pin *drvr, const Pin *load) { - PinPair pair(drvr, load); - pairs_->erase(pair); + pairs_->erase({drvr, load}); } void @@ -3656,8 +3653,7 @@ Sdc::isDisabled(const Instance *inst, { if (role == TimingRole::wire()) { // Hierarchical thru pin disables. - PinPair pair(from_pin, to_pin); - return disabled_wire_edges_.contains(pair); + return disabled_wire_edges_.contains({from_pin, to_pin}); } else { LibertyCell *cell = network_->libertyCell(inst); diff --git a/sdc/Sdc.i b/sdc/Sdc.i index e6b95667..2bca70b0 100644 --- a/sdc/Sdc.i +++ b/sdc/Sdc.i @@ -1654,6 +1654,14 @@ set_propagate_all_clocks(bool prop) Sta::sta()->setPropagateAllClocks(prop); } +bool +pin_is_constrained(const Pin *pin) +{ + Sta *sta = Sta::sta(); + Sdc *sdc = sta->cmdSdc(); + return sdc->isConstrained(pin); +} + %} // inline //////////////////////////////////////////////////////////////// diff --git a/include/sta/WriteSdc.hh b/sdc/WriteSdc.hh similarity index 100% rename from include/sta/WriteSdc.hh rename to sdc/WriteSdc.hh diff --git a/search/CheckTiming.cc b/search/CheckTiming.cc index f05de24e..965a8d15 100644 --- a/search/CheckTiming.cc +++ b/search/CheckTiming.cc @@ -24,7 +24,6 @@ #include "CheckTiming.hh" -#include "ContainerHelpers.hh" #include "Error.hh" #include "TimingRole.hh" #include "Network.hh" @@ -64,7 +63,6 @@ void CheckTiming::deleteErrors() { for (CheckError *error : errors_) { - deleteContents(error); delete error; } } @@ -204,25 +202,23 @@ CheckTiming::checkLoops() errorMsgSubst("Warning: There %is %d combinational loop%s in the design.", loop_count, error_msg); CheckError *error = new CheckError; - error->push_back(stringCopy(error_msg.c_str())); + error->push_back(error_msg); for (GraphLoop *loop : loops) { if (loop->isCombinational()) { Edge *last_edge = nullptr; for (Edge *edge : *loop->edges()) { Pin *pin = edge->from(graph_)->pin(); - const char *pin_name = stringCopy(sdc_network_->pathName(pin)); - error->push_back(pin_name); + error->push_back(sdc_network_->pathName(pin)); last_edge = edge; } if (last_edge) { - error->push_back(stringCopy("| loop cut point")); + error->push_back("| loop cut point"); const Pin *pin = last_edge->to(graph_)->pin(); - const char *pin_name = stringCopy(sdc_network_->pathName(pin)); - error->push_back(pin_name); + error->push_back(sdc_network_->pathName(pin)); // Separator between loops. - error->push_back(stringCopy("--------------------------------")); + error->push_back("--------------------------------"); } } } @@ -362,15 +358,12 @@ CheckTiming::pushPinErrors(const char *msg, CheckError *error = new CheckError; std::string error_msg; errorMsgSubst(msg, pins.size(), error_msg); - // Copy the error strings because the error deletes them when it - // is deleted. - error->push_back(stringCopy(error_msg.c_str())); + error->push_back(error_msg); // Sort the error pins so the output is independent of the order // the the errors are discovered. PinSeq pins1 = sortByPathName(&pins, network_); for (const Pin *pin : pins1) { - const char *pin_name = stringCopy(sdc_network_->pathName(pin)); - error->push_back(pin_name); + error->push_back(sdc_network_->pathName(pin)); } errors_.push_back(error); } @@ -384,15 +377,12 @@ CheckTiming::pushClkErrors(const char *msg, CheckError *error = new CheckError; std::string error_msg; errorMsgSubst(msg, clks.size(), error_msg); - // Copy the error strings because the error deletes them when it - // is deleted. - error->push_back(stringCopy(error_msg.c_str())); + error->push_back(error_msg); // Sort the error clks so the output is independent of the order // the the errors are discovered. ClockSeq clks1 = sortByName(&clks); for (const Clock *clk : clks1) { - const char *clk_name = stringCopy(clk->name()); - error->push_back(clk_name); + error->push_back(clk->name()); } errors_.push_back(error); } diff --git a/search/CheckTiming.hh b/search/CheckTiming.hh index 26edc150..75bd63ac 100644 --- a/search/CheckTiming.hh +++ b/search/CheckTiming.hh @@ -26,7 +26,7 @@ #include -#include "StringSeq.hh" +#include "StringUtil.hh" #include "NetworkClass.hh" #include "GraphClass.hh" #include "SdcClass.hh" diff --git a/search/ClkSkew.cc b/search/ClkSkew.cc index 09cdf204..9deb4c91 100644 --- a/search/ClkSkew.cc +++ b/search/ClkSkew.cc @@ -106,7 +106,7 @@ ClkSkews::reportClkSkew(ClkSkew &clk_skew, report_->reportLine("%7s source latency %s %s", time_unit->asString(src_latency, digits), sdc_network_->pathName(src_path->pin(this)), - src_path->transition(this)->to_string().c_str()); + src_path->transition(this)->shortName()); if (src_internal_clk_latency != 0.0) report_->reportLine("%7s source internal clock delay", time_unit->asString(src_internal_clk_latency, digits)); @@ -116,7 +116,7 @@ ClkSkews::reportClkSkew(ClkSkew &clk_skew, report_->reportLine("%7s target latency %s %s", time_unit->asString(-tgt_latency, digits), sdc_network_->pathName(tgt_path->pin(this)), - tgt_path->transition(this)->to_string().c_str()); + tgt_path->transition(this)->shortName()); if (tgt_internal_clk_latency != 0.0) report_->reportLine("%7s target internal clock delay", time_unit->asString(-tgt_internal_clk_latency, digits)); @@ -315,10 +315,10 @@ ClkSkews::findClkSkew(Vertex *src_vertex, debugPrint(debug_, "clk_skew", 2, "%s %s %s -> %s %s %s crpr = %s skew = %s", network_->pathName(src_path->pin(this)), - src_path->transition(this)->to_string().c_str(), + src_path->transition(this)->shortName(), time_unit->asString(probe.srcLatency(this)), network_->pathName(tgt_path->pin(this)), - tgt_path->transition(this)->to_string().c_str(), + tgt_path->transition(this)->shortName(), time_unit->asString(probe.tgtLatency(this)), delayAsString(probe.crpr(this), this), time_unit->asString(probe.skew())); diff --git a/search/Genclks.cc b/search/Genclks.cc index bbb26621..225dfcf0 100644 --- a/search/Genclks.cc +++ b/search/Genclks.cc @@ -878,7 +878,7 @@ Genclks::recordSrcPaths(Clock *gclk) debugPrint(debug_, "genclk", 2, " %s insertion %s %s %s", network_->pathName(gclk_pin), early_late->to_string().c_str(), - rf->to_string().c_str(), + rf->shortName(), delayAsString(path->arrival(), this)); src_path = *path; } diff --git a/search/Latches.cc b/search/Latches.cc index 3c113c51..9dcd688a 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -323,6 +323,10 @@ Latches::latchOutArrival(const Path *data_path, ArcDelay &arc_delay, Arrival &q_arrival) { + q_tag = nullptr; + arc_delay = 0.0; + q_arrival = 0.0; + Scene *scene = data_path->scene(this); Sdc *sdc = scene->sdc(); const Mode *mode = scene->mode(); @@ -337,83 +341,110 @@ Latches::latchOutArrival(const Path *data_path, // Latch enable may be missing if library is malformed. switch (state) { case LatchEnableState::closed: - // Latch is disabled by constant enable. + // Latch is always closed because enable is constant. break; case LatchEnableState::open: { + // Latch is always open because enable is constant. ExceptionPath *excpt = exceptionTo(data_path, nullptr); if (!(excpt && excpt->isFalse())) { arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, false, min_max, dcalc_ap, sdc); q_arrival = data_path->arrival() + arc_delay; - q_tag = data_path->tag(this); + // Copy the data tag but remove the drprClkPath. + // Levelization does not traverse latch D->Q edges, so in some cases + // level(Q) < level(D) + // Note that + // level(crprClkPath(data)) < level(D) + // The danger is that + // level(crprClkPath(data)) == level(Q) + // or some other downstream vertex. + // This can lead to data races when finding arrivals at the same level + // use multiple threads. + // Kill the crprClklPath to be safe. + const ClkInfo *data_clk_info = data_path->clkInfo(this); + const ClkInfo *q_clk_info = + search_->findClkInfo(scene, + data_clk_info->clkEdge(), + data_clk_info->clkSrc(), + data_clk_info->isPropagated(), + data_clk_info->genClkSrc(), + data_clk_info->isGenClkSrcPath(), + data_clk_info->pulseClkSense(), + data_clk_info->insertion(), + data_clk_info->latency(), + data_clk_info->uncertainties(), + min_max, nullptr); + q_tag = search_->findTag(scene, d_q_arc->toEdge()->asRiseFall(), + min_max, q_clk_info, false, + nullptr, false, data_path->tag(this)->states(), + false, nullptr); } - } break; + } case LatchEnableState::enabled: { const MinMax *tgt_min_max = data_path->tgtClkMinMax(this); VertexPathIterator enable_iter(enable_vertex, scene, tgt_min_max, enable_rf, this); while (enable_iter.hasNext()) { Path *enable_path = enable_iter.next(); - const ClkInfo *en_clk_info = enable_path->clkInfo(this); - const ClockEdge *en_clk_edge = en_clk_info->clkEdge(); - if (enable_path->isClock(this)) { - ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge); - // D->Q is disabled when if there is a path delay -to D or EN clk. - if (!(excpt && (excpt->isFalse() - || excpt->isPathDelay()))) { - Path *disable_path = latchEnableOtherPath(enable_path); - Delay borrow, time_given_to_startpoint; - Arrival adjusted_data_arrival; - Required required; - latchRequired(data_path, enable_path, disable_path, - required, borrow, adjusted_data_arrival, - time_given_to_startpoint); - if (delayGreater(borrow, 0.0, this)) { - // Latch is transparent when data arrives. - arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, - false, min_max, dcalc_ap, sdc); - q_arrival = adjusted_data_arrival + arc_delay; - // Tag switcheroo - data passing thru gets latch enable tag. - // States and path ap come from Q, everything else from enable. - Path *crpr_clk_path = crprActive(mode) ? enable_path : nullptr; - const ClkInfo *q_clk_info = - search_->findClkInfo(en_clk_info->scene(), - en_clk_edge, - en_clk_info->clkSrc(), - en_clk_info->isPropagated(), - en_clk_info->genClkSrc(), - en_clk_info->isGenClkSrcPath(), - en_clk_info->pulseClkSense(), - en_clk_info->insertion(), - en_clk_info->latency(), - en_clk_info->uncertainties(), - min_max, crpr_clk_path); - const RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall(); - ExceptionStateSet *states = nullptr; - // Latch data pin is a valid exception -from pin. - if (sdc->exceptionFromStates(data_path->pin(this), - data_path->transition(this), - nullptr, nullptr, // clk below - MinMax::max(), states) - // -from enable non-filter exceptions apply. - && sdc->exceptionFromStates(enable_vertex->pin(), - enable_rf, - en_clk_edge->clock(), - en_clk_edge->transition(), - MinMax::max(), false, states)) - q_tag = search_->findTag(enable_path->tag(this)->scene(), - q_rf, MinMax::max(), q_clk_info, false, - nullptr, false, states, true, nullptr); - } - return; - } - } + const ClkInfo *en_clk_info = enable_path->clkInfo(this); + const ClockEdge *en_clk_edge = en_clk_info->clkEdge(); + if (enable_path->isClock(this)) { + ExceptionPath *excpt = exceptionTo(data_path, en_clk_edge); + // D->Q is disabled when if there is a path delay -to D or EN clk. + if (!(excpt && (excpt->isFalse() + || excpt->isPathDelay()))) { + Path *disable_path = latchEnableOtherPath(enable_path); + Delay borrow, time_given_to_startpoint; + Arrival adjusted_data_arrival; + Required required; + latchRequired(data_path, enable_path, disable_path, + required, borrow, adjusted_data_arrival, + time_given_to_startpoint); + if (delayGreater(borrow, 0.0, this)) { + // Latch is transparent when data arrives. + arc_delay = search_->deratedDelay(data_vertex, d_q_arc, d_q_edge, + false, min_max, dcalc_ap, sdc); + q_arrival = adjusted_data_arrival + arc_delay; + // Tag switcheroo - data passing thru gets latch enable tag. + // States and path ap come from Q, everything else from enable. + Path *crpr_clk_path = crprActive(mode) ? enable_path : nullptr; + const ClkInfo *q_clk_info = + search_->findClkInfo(scene, + en_clk_edge, + en_clk_info->clkSrc(), + en_clk_info->isPropagated(), + en_clk_info->genClkSrc(), + en_clk_info->isGenClkSrcPath(), + en_clk_info->pulseClkSense(), + en_clk_info->insertion(), + en_clk_info->latency(), + en_clk_info->uncertainties(), + min_max, crpr_clk_path); + ExceptionStateSet *states = nullptr; + // Latch data pin is a valid exception -from pin. + if (sdc->exceptionFromStates(data_path->pin(this), + data_path->transition(this), + nullptr, nullptr, // clk below + MinMax::max(), states) + // -from enable non-filter exceptions apply. + && sdc->exceptionFromStates(enable_vertex->pin(), + enable_rf, + en_clk_edge->clock(), + en_clk_edge->transition(), + MinMax::max(), false, states)) + q_tag = search_->findTag(scene, d_q_arc->toEdge()->asRiseFall(), + MinMax::max(), q_clk_info, false, + nullptr, false, states, true, nullptr); + } + return; + } + } } // No enable path found. - } break; } + } } ExceptionPath * diff --git a/search/Mode.cc b/search/Mode.cc index 80e5b5fd..1c44a73f 100644 --- a/search/Mode.cc +++ b/search/Mode.cc @@ -105,7 +105,7 @@ Mode::makePathGroups(int group_path_count, bool unique_edges, float slack_min, float slack_max, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, diff --git a/search/Path.cc b/search/Path.cc index 40d96baf..5514d559 100644 --- a/search/Path.cc +++ b/search/Path.cc @@ -201,7 +201,7 @@ Path::to_string(const StaState *sta) const else return stringPrintTmp("%s %s %s/%s %d", vertex(sta)->to_string(sta).c_str(), - transition(sta)->to_string().c_str(), + transition(sta)->shortName(), scene(sta)->name().c_str(), minMax(sta)->to_string().c_str(), tagIndex(sta)); diff --git a/search/PathEnd.cc b/search/PathEnd.cc index 7e72e6fb..33b6e1cd 100644 --- a/search/PathEnd.cc +++ b/search/PathEnd.cc @@ -2030,32 +2030,22 @@ PathEndPathDelay::exceptPathCmp(const PathEnd *path_end, //////////////////////////////////////////////////////////////// -PathEndLess::PathEndLess(const StaState *sta) : - sta_(sta) -{ -} - -bool -PathEndLess::operator()(const PathEnd *path_end1, - const PathEnd *path_end2) const -{ - return PathEnd::less(path_end1, path_end2, sta_); -} - bool PathEnd::less(const PathEnd *path_end1, const PathEnd *path_end2, + bool cmp_slack, const StaState *sta) { - return cmp(path_end1, path_end2, sta) < 0; + return cmp(path_end1, path_end2, cmp_slack, sta) < 0; } int PathEnd::cmp(const PathEnd *path_end1, const PathEnd *path_end2, + bool cmp_slack, const StaState *sta) { - int cmp = path_end1->isUnconstrained() + int cmp = !cmp_slack || path_end1->isUnconstrained() ? -cmpArrival(path_end1, path_end2, sta) : cmpSlack(path_end1, path_end2, sta); if (cmp == 0) { @@ -2139,7 +2129,25 @@ PathEnd::cmpNoCrpr(const PathEnd *path_end1, //////////////////////////////////////////////////////////////// -PathEndSlackLess::PathEndSlackLess(const StaState *sta) : +PathEndLess::PathEndLess(bool cmp_slack, + const StaState *sta) : + cmp_slack_(cmp_slack), + sta_(sta) +{ +} + +bool +PathEndLess::operator()(const PathEnd *path_end1, + const PathEnd *path_end2) const +{ + return PathEnd::less(path_end1, path_end2, cmp_slack_, sta_); +} + +//////////////////////////////////////////////////////////////// + +PathEndSlackLess::PathEndSlackLess(bool cmp_slack, + const StaState *sta) : + cmp_slack_(cmp_slack), sta_(sta) { } diff --git a/search/PathEnum.cc b/search/PathEnum.cc index e53b0889..67465a1b 100644 --- a/search/PathEnum.cc +++ b/search/PathEnum.cc @@ -91,7 +91,7 @@ DiversionGreater::operator()(Diversion *div1, { PathEnd *path_end1 = div1->pathEnd(); PathEnd *path_end2 = div2->pathEnd(); - return PathEnd::cmp(path_end1, path_end2, sta_) > 0; + return PathEnd::cmp(path_end1, path_end2, true, sta_) > 0; } static void @@ -426,7 +426,7 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *, debugPrint(debug_, "path_enum", 3, "visit fanin %s -> %s %s %s", from_path->to_string(this).c_str(), to_vertex->to_string(this).c_str(), - to_rf->to_string().c_str(), + to_rf->shortName(), delayAsString(search_->deratedDelay(from_vertex, arc, edge, false, from_path->minMax(this), from_path->dcalcAnalysisPtIndex(this), diff --git a/search/PathEnum.hh b/search/PathEnum.hh index f2f68cd8..72b2ddb8 100644 --- a/search/PathEnum.hh +++ b/search/PathEnum.hh @@ -68,8 +68,8 @@ public: // Insert path ends that are enumerated in slack/arrival order. void insert(PathEnd *path_end); virtual ~PathEnum(); - virtual bool hasNext(); - virtual PathEnd *next(); + bool hasNext() override; + PathEnd *next() override; private: void makeDiversions(PathEnd *path_end, diff --git a/search/PathGroup.cc b/search/PathGroup.cc index ca842db5..8f3738c6 100644 --- a/search/PathGroup.cc +++ b/search/PathGroup.cc @@ -50,7 +50,7 @@ namespace sta { -size_t PathGroup::group_path_count_max = std::numeric_limits::max(); +int PathGroup::group_path_count_max = std::numeric_limits::max(); PathGroup * PathGroup::makePathGroupSlack(const char *name, @@ -82,8 +82,8 @@ PathGroup::makePathGroupArrival(const char *name, } PathGroup::PathGroup(const char *name, - size_t group_path_count, - size_t endpoint_path_count, + int group_path_count, + int endpoint_path_count, bool unique_pins, bool unique_edges, float slack_min, @@ -99,43 +99,36 @@ PathGroup::PathGroup(const char *name, slack_min_(slack_min), slack_max_(slack_max), min_max_(min_max), - compare_slack_(cmp_slack), - threshold_(min_max->initValue()), + cmp_slack_(cmp_slack), + heap_(group_path_count, PathEndLess(cmp_slack, sta)), sta_(sta) { } -PathGroup::~PathGroup() +PathEndSeq +PathGroup::pathEnds() const { - deleteContents(path_ends_); + return heap_.contents(); } bool PathGroup::saveable(PathEnd *path_end) { - float threshold; - { - LockGuard lock(lock_); - threshold = threshold_; - } - if (compare_slack_) { + if (cmp_slack_) { // Crpr increases the slack, so check the slack // without crpr first because it is expensive to find. Slack slack = path_end->slackNoCrpr(sta_); if (!delayIsInitValue(slack, min_max_) - && delayLessEqual(slack, threshold, sta_) && delayLessEqual(slack, slack_max_, sta_)) { // Now check with crpr. slack = path_end->slack(sta_); - return delayLessEqual(slack, threshold, sta_) - && delayLessEqual(slack, slack_max_, sta_) + return delayLessEqual(slack, slack_max_, sta_) && delayGreaterEqual(slack, slack_min_, sta_); } } else { const Arrival &arrival = path_end->dataArrivalTime(sta_); - return !delayIsInitValue(arrival, min_max_) - && delayGreaterEqual(arrival, threshold, min_max_, sta_); + return !delayIsInitValue(arrival, min_max_); } return false; } @@ -148,7 +141,7 @@ PathGroup::saveable(PathEnd *path_end) bool PathGroup::enumMinSlackUnderMin(PathEnd *path_end) { - if (compare_slack_ + if (cmp_slack_ && endpoint_path_count_ > 1 && slack_min_ > -INF) { const Path *path = path_end->path(); @@ -177,72 +170,28 @@ void PathGroup::insert(PathEnd *path_end) { LockGuard lock(lock_); - path_ends_.push_back(path_end); + heap_.insert(path_end); path_end->setPathGroup(this); - if (group_path_count_ != group_path_count_max - && path_ends_.size() > group_path_count_ * 2) - prune(); -} - -void -PathGroup::prune() -{ - sort(); - VertexPathCountMap path_counts; - size_t end_count = 0; - for (unsigned i = 0; i < path_ends_.size(); i++) { - PathEnd *path_end = path_ends_[i]; - Vertex *vertex = path_end->vertex(sta_); - // Squish up to endpoint_path_count path ends per vertex - // up to the front of path_ends_. - if (end_count < group_path_count_ - && path_counts[vertex] < endpoint_path_count_) { - path_ends_[end_count++] = path_end; - path_counts[vertex]++; - } - else - delete path_end; - } - path_ends_.resize(end_count); - - // Set a threshold to the bottom of the sorted list that future - // inserts need to beat. - PathEnd *last_end = path_ends_[end_count - 1]; - if (compare_slack_) - threshold_ = delayAsFloat(last_end->slack(sta_)); - else - threshold_ = delayAsFloat(last_end->dataArrivalTime(sta_)); } void PathGroup::pushEnds(PathEndSeq &path_ends) { - ensureSortedMaxPaths(); - for (PathEnd *path_end : path_ends_) - path_ends.push_back(path_end); -} - -void -PathGroup::ensureSortedMaxPaths() -{ - if (path_ends_.size() > group_path_count_) - prune(); - else - sort(); -} - -void -PathGroup::sort() -{ - sta::sort(path_ends_, PathEndLess(sta_)); + if (!heap_.empty()) { + PathEndSeq ends = heap_.extract(); + path_ends.reserve(path_ends.size() + ends.size()); + // Append heap path ends to path_ends. + path_ends.insert(path_ends.end(), + std::make_move_iterator(ends.begin()), + std::make_move_iterator(ends.end())); + } } void PathGroup::clear() { LockGuard lock(lock_); - threshold_ = min_max_->initValue(); - path_ends_.clear(); + heap_.clear(); } //////////////////////////////////////////////////////////////// @@ -258,7 +207,7 @@ PathGroups::PathGroups(int group_path_count, bool unique_edges, float slack_min, float slack_max, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, @@ -276,7 +225,7 @@ PathGroups::PathGroups(int group_path_count, slack_min_(slack_min), slack_max_(slack_max) { - StdStringSet groups; + StringSet groups; for (std::string &group_name : group_names) groups.insert(group_name); @@ -297,7 +246,7 @@ PathGroups::makeGroups(int group_path_count, bool unique_edges, float slack_min, float slack_max, - StdStringSet &group_names, + StringSet &group_names, bool setup_hold, bool async, bool gated_clk, @@ -417,7 +366,7 @@ PathGroups::findPathGroup(const Clock *clock, bool PathGroups::reportGroup(const char *group_name, - StdStringSet &group_names) const + StringSet &group_names) const { return group_names.empty() || group_names.contains(group_name); @@ -479,11 +428,11 @@ PathGroups::pathGroups(const PathEnd *path_end) const } // Mirrors PathGroups::pathGroup. -StdStringSeq +StringSeq PathGroups::pathGroupNames(const PathEnd *path_end, const StaState *sta) { - StdStringSeq group_names; + StringSeq group_names; const char *group_name = nullptr; const Search *search = sta->search(); ExceptionPathSeq group_paths = search->groupPathsTo(path_end); @@ -576,14 +525,14 @@ PathGroups::pushEnds(PathEndSeq &path_ends) } } -StdStringSeq +StringSeq PathGroups::pathGroupNames() { std::set group_names1; const Sdc *sdc = mode_->sdc(); for (const auto& [name, group] : sdc->groupPaths()) group_names1.insert(name); - StdStringSeq group_names2; + StringSeq group_names2; for (const std::string &name : group_names1) group_names2.push_back(name); sort(group_names2); @@ -632,9 +581,8 @@ PathGroups::makePathEnds(ExceptionTo *to, unique_pins_, unique_edges_, scenes, min_max); pushEnds(path_ends); - if (sort_by_slack) { - sort(path_ends, PathEndLess(this)); - } + if (sort_by_slack) + sort(path_ends, PathEndLess(true, this)); if (unconstrained_paths && path_ends.empty()) @@ -663,12 +611,12 @@ private: PathGroups *path_groups_; PathGroupEndMap ends_; - PathEndLess cmp_; + PathEndLess less_; }; MakePathEnds1::MakePathEnds1(PathGroups *path_groups) : path_groups_(path_groups), - cmp_(path_groups) + less_(true, path_groups) { } @@ -693,7 +641,7 @@ MakePathEnds1::visitPathEnd(PathEnd *path_end, // Only keep the path end with the smallest slack/latest arrival. PathEnd *worst_end = findKey(ends_, group); if (worst_end) { - if (cmp_(path_end, worst_end)) { + if (less_(path_end, worst_end)) { ends_[group] = path_end->copy(); delete worst_end; } @@ -741,8 +689,8 @@ private: PathGroups *path_groups_; const StaState *sta_; PathGroupEndsMap ends_; - PathEndSlackLess slack_cmp_; - PathEndNoCrprLess path_no_crpr_cmp_; + PathEndSlackLess less_; + PathEndNoCrprLess path_no_crpr_less_; }; MakePathEndsAll::MakePathEndsAll(int endpoint_path_count, @@ -750,8 +698,8 @@ MakePathEndsAll::MakePathEndsAll(int endpoint_path_count, endpoint_path_count_(endpoint_path_count), path_groups_(path_groups), sta_(path_groups), - slack_cmp_(path_groups), - path_no_crpr_cmp_(path_groups) + less_(true, path_groups), + path_no_crpr_less_(path_groups) { } @@ -792,8 +740,8 @@ MakePathEndsAll::vertexEnd(Vertex *) Debug *debug = sta_->debug(); for (auto [group, ends] : ends_) { if (ends) { - sort(ends, slack_cmp_); - PathEndNoCrprSet unique_ends(path_no_crpr_cmp_); + sort(ends, less_); + PathEndNoCrprSet unique_ends(path_no_crpr_less_); auto end_iter = ends->begin(); int n = 0; while (end_iter != ends->end() @@ -805,7 +753,7 @@ MakePathEndsAll::vertexEnd(Vertex *) debugPrint(debug, "path_group", 2, "insert %s %s %s %d", path_end->vertex(sta_)->to_string(sta_).c_str(), path_end->typeName(), - path_end->transition(sta_)->to_string().c_str(), + path_end->transition(sta_)->shortName(), path_end->path()->tag(sta_)->index()); // Give the group a copy of the path end because // it may delete it during pruning. @@ -820,7 +768,7 @@ MakePathEndsAll::vertexEnd(Vertex *) debugPrint(debug, "path_group", 3, "prune %s %s %s %d", path_end->vertex(sta_)->to_string(sta_).c_str(), path_end->typeName(), - path_end->transition(sta_)->to_string().c_str(), + path_end->transition(sta_)->shortName(), path_end->path()->tag(sta_)->index()); } // Clear ends for next vertex. @@ -898,11 +846,8 @@ PathGroups::enumPathEnds(PathGroup *group, // enumerator. PathEnum path_enum(group_path_count, endpoint_path_count, unique_pins, unique_edges, cmp_slack, this); - for (PathEnd *end : group->pathEnds()) { - if (group->saveable(end) - || group->enumMinSlackUnderMin(end)) - path_enum.insert(end); - } + for (PathEnd *end : group->pathEnds()) + path_enum.insert(end); group->clear(); // Parallel path enumeratation to find the endpoint_path_count/max path ends. diff --git a/search/ReportPath.cc b/search/ReportPath.cc index ad9b9f11..bf6d83fe 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -211,15 +211,15 @@ ReportPath::findField(const char *name) const } void -ReportPath::setReportFieldOrder(StringSeq *field_names) +ReportPath::setReportFieldOrder(const StringSeq &field_names) { // Disable all fields. for (ReportField *field : fields_) field->setEnabled(false); ReportFieldSeq next_fields; - for (const char *field_name : *field_names) { - ReportField *field = findField(field_name); + for (const std::string &field_name : field_names) { + ReportField *field = findField(field_name.c_str()); if (field) { next_fields.push_back(field); field->setEnabled(true); @@ -406,7 +406,7 @@ ReportPath::reportEndpointHeader(const PathEnd *end, : "max_delay/setup"; report_->reportLine("%s group %s", setup_hold, - group->name()); + group->name().c_str()); reportBlankLine(); reportEndHeader(); } @@ -1079,11 +1079,17 @@ ReportPath::reportJson(const PathEnd *end, { std::string result; result += "{\n"; - stringAppend(result, " \"type\": \"%s\",\n", end->typeName()); - stringAppend(result, " \"path_group\": \"%s\",\n", - end->pathGroup()->name()); - stringAppend(result, " \"path_type\": \"%s\",\n", - end->minMax(this)->to_string().c_str()); + result += " \"type\": \""; + result += end->typeName(); + result += "\",\n"; + + result += " \"path_group\": \""; + result += end->pathGroup()->name(); + result += "\",\n"; + + result += " \"path_type\": \""; + result += end->minMax(this)->to_string(); + result += "\",\n"; PathExpanded expanded(end->path(), this); const Pin *startpoint = expanded.startPath()->vertex(this)->pin(); @@ -1269,7 +1275,7 @@ ReportPath::reportSlackOnly(const PathEnd *end) const { std::string line; const EarlyLate *early_late = end->pathEarlyLate(this); - reportDescription(end->pathGroup()->name(), line); + reportDescription(end->pathGroup()->name().c_str(), line); if (end->isUnconstrained()) reportSpaceFieldDelay(end->dataArrivalTimeOffset(this), early_late, line); else diff --git a/search/ReportPath.hh b/search/ReportPath.hh index 39c8b1a5..b934bc9e 100644 --- a/search/ReportPath.hh +++ b/search/ReportPath.hh @@ -27,7 +27,7 @@ #include #include -#include "StringSeq.hh" +#include "StringUtil.hh" #include "SearchClass.hh" #include "PathEnd.hh" #include "CheckMinPulseWidths.hh" @@ -49,7 +49,7 @@ public: virtual ~ReportPath(); ReportPathFormat pathFormat() const { return format_; } void setPathFormat(ReportPathFormat format); - void setReportFieldOrder(StringSeq *field_names); + void setReportFieldOrder(const StringSeq &field_names); void setReportFields(bool report_input_pin, bool report_hier_pins, bool report_net, diff --git a/search/Search.cc b/search/Search.cc index 25683114..871b0e0d 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -497,14 +497,14 @@ Search::findPathEnds(ExceptionFrom *from, bool unconstrained, const SceneSeq &scenes, const MinMaxAll *min_max, - size_t group_path_count, - size_t endpoint_path_count, + int group_path_count, + int endpoint_path_count, bool unique_pins, bool unique_edges, float slack_min, float slack_max, bool sort_by_slack, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, @@ -1365,8 +1365,8 @@ ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */, debugPrint(debug_, "search", 3, " %s", from_vertex->to_string(this).c_str()); debugPrint(debug_, "search", 3, " %s -> %s %s", - from_rf->to_string().c_str(), - to_rf->to_string().c_str(), + from_rf->shortName(), + to_rf->shortName(), min_max->to_string().c_str()); debugPrint(debug_, "search", 3, " from tag: %s", from_tag->to_string(this).c_str()); @@ -2919,7 +2919,7 @@ Search::reportArrivals(Vertex *vertex, prev_str += "NULL"; } report_->reportLine(" %s %s %s / %s %s%s", - rf->to_string().c_str(), + rf->shortName(), path->minMax(this)->to_string().c_str(), delayAsString(path->arrival(), this), req, @@ -3654,10 +3654,10 @@ RequiredVisitor::visitFromToPath(const Pin *, const MinMax *min_max) { // Don't propagate required times through latch D->Q edges. - if (edge->role() != TimingRole::latchDtoQ()) { + if (!edge->role()->isLatchDtoQ()) { debugPrint(debug_, "search", 3, " %s -> %s %s", - from_rf->to_string().c_str(), - to_rf->to_string().c_str(), + from_rf->shortName(), + to_rf->shortName(), min_max->to_string().c_str()); debugPrint(debug_, "search", 3, " from tag %2u: %s", from_tag->index(), diff --git a/search/Search.i b/search/Search.i index 31a53d6f..d75cbf8d 100644 --- a/search/Search.i +++ b/search/Search.i @@ -242,7 +242,7 @@ endpoint_slack(const Pin *pin, } } -StdStringSeq +StringSeq path_group_names() { Sta *sta = Sta::sta(); @@ -359,7 +359,7 @@ find_path_ends(ExceptionFrom *from, float slack_min, float slack_max, bool sort_by_slack, - StdStringSeq path_groups, + StringSeq path_groups, bool setup, bool hold, bool recovery, @@ -395,10 +395,9 @@ set_report_path_format(ReportPathFormat format) } void -set_report_path_field_order(StringSeq *field_names) +set_report_path_field_order(const StringSeq &field_names) { Sta::sta()->setReportPathFieldOrder(field_names); - delete field_names; } void @@ -741,8 +740,8 @@ write_timing_model_cmd(const char *lib_name, void define_scene_cmd(const char *name, const char *mode_name, - const StdStringSeq liberty_min_files, - const StdStringSeq liberty_max_files, + const StringSeq liberty_min_files, + const StringSeq liberty_max_files, const char *spef_min_file, const char *spef_max_file) { @@ -753,11 +752,10 @@ define_scene_cmd(const char *name, } void -define_scenes_cmd(StringSeq *scene_names) +define_scenes_cmd(const StringSeq &scene_names) { Sta *sta = Sta::sta(); sta->makeScenes(scene_names); - delete scene_names; } Scene * diff --git a/search/Sta.cc b/search/Sta.cc index 9ecc2e5b..4da53008 100644 --- a/search/Sta.cc +++ b/search/Sta.cc @@ -52,7 +52,7 @@ #include "Sdc.hh" #include "Mode.hh" #include "Variables.hh" -#include "WriteSdc.hh" +#include "sdc/WriteSdc.hh" #include "ExceptionPath.hh" #include "Parasitics.hh" #include "parasitics/SpefReader.hh" @@ -299,6 +299,7 @@ Sta::makeComponents() makeReportPath(); makePower(); makeClkSkews(); + makeCheckTiming(); setCmdNamespace1(CmdNamespace::sdc); setThreadCount1(defaultThreadCount()); @@ -355,8 +356,7 @@ Sta::updateComponentsState() latches_->copyState(this); graph_delay_calc_->copyState(this); report_path_->copyState(this); - if (check_timing_) - check_timing_->copyState(this); + check_timing_->copyState(this); clk_skews_->copyState(this); if (power_) @@ -2075,10 +2075,10 @@ Sta::isPathGroupName(const char *group_name, || stringEq(group_name, PathGroups::unconstrainedGroupName()); } -StdStringSeq +StringSeq Sta::pathGroupNames(const Sdc *sdc) const { - StdStringSeq names; + StringSeq names; for (const Clock *clk : sdc->clocks()) names.push_back(clk->name()); @@ -2214,8 +2214,8 @@ Sta::checkTiming(const Mode *mode, bool generated_clks) { if (unconstrained_endpoints) { - // Only arrivals to find unconstrained_endpoints. - searchPreamble(); + // Only need non-clock arrivals to find unconstrained_endpoints. + searchPreamble(); search_->findAllArrivals(); } else { @@ -2224,8 +2224,6 @@ Sta::checkTiming(const Mode *mode, mode->sim()->ensureConstantsPropagated(); mode->clkNetwork()->ensureClkNetwork(); } - if (check_timing_ == nullptr) - makeCheckTiming(); return check_timing_->check(mode, no_input_delay, no_output_delay, reg_multiple_clks, reg_no_clks, unconstrained_endpoints, @@ -2468,9 +2466,9 @@ Sta::makeDefaultScene() // define_corners (before read_liberty). void -Sta::makeScenes(StringSeq *scene_names) +Sta::makeScenes(const StringSeq &scene_names) { - if (scene_names->size() > scene_count_max) + if (scene_names.size() > scene_count_max) report_->error(1553, "maximum scene count exceeded"); Parasitics *parasitics = findParasitics("default"); Mode *mode = modes_[0]; @@ -2478,7 +2476,7 @@ Sta::makeScenes(StringSeq *scene_names) mode->clear(); deleteScenes(); - for (const char *name : *scene_names) + for (const std::string &name : scene_names) makeScene(name, mode, parasitics); cmd_scene_ = scenes_[0]; @@ -2490,8 +2488,8 @@ Sta::makeScenes(StringSeq *scene_names) void Sta::makeScene(const std::string &name, const std::string &mode_name, - const StdStringSeq &liberty_min_files, - const StdStringSeq &liberty_max_files, + const StringSeq &liberty_min_files, + const StringSeq &liberty_max_files, const std::string &spef_min_file, const std::string &spef_max_file) { @@ -2598,12 +2596,12 @@ Sta::findScenes(const std::string &name, void Sta::updateSceneLiberty(Scene *scene, - const StdStringSeq &liberty_min_files, - const StdStringSeq &liberty_max_files) + const StringSeq &liberty_min_files, + const StringSeq &liberty_max_files) { - StdStringSet warned_files; + StringSet warned_files; for (const MinMax *min_max : MinMax::range()) { - const StdStringSeq &liberty_files = min_max == MinMax::min() + const StringSeq &liberty_files = min_max == MinMax::min() ? liberty_min_files : liberty_max_files; for (const std::string &lib_file : liberty_files) { @@ -2678,7 +2676,7 @@ Sta::findPathEnds(ExceptionFrom *from, float slack_min, float slack_max, bool sort_by_slack, - StdStringSeq &group_names, + StringSeq &group_names, bool setup, bool hold, bool recovery, @@ -2729,7 +2727,7 @@ Sta::setReportPathFormat(ReportPathFormat format) } void -Sta::setReportPathFieldOrder(StringSeq *field_names) +Sta::setReportPathFieldOrder(const StringSeq &field_names) { report_path_->setReportFieldOrder(field_names); } @@ -3239,7 +3237,7 @@ void EndpointPathEndVisitor::visit(PathEnd *path_end) { if (path_end->minMax(sta_) == min_max_) { - StdStringSeq group_names = PathGroups::pathGroupNames(path_end, sta_); + StringSeq group_names = PathGroups::pathGroupNames(path_end, sta_); for (std::string &group_name : group_names) { if (group_name == path_group_name_) { Slack end_slack = path_end->slack(sta_); @@ -6037,7 +6035,7 @@ Sta::activity(const Pin *pin, //////////////////////////////////////////////////////////////// void -Sta::writePathSpice(Path *path, +Sta::writePathSpice(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, diff --git a/search/Tag.cc b/search/Tag.cc index 5e368d80..ece8b14c 100644 --- a/search/Tag.cc +++ b/search/Tag.cc @@ -104,8 +104,7 @@ Tag::to_string(bool report_index, if (report_rf_min_max) { const RiseFall *rf = transition(); const MinMax *min_max = minMax(); - result += rf->to_string(); - result += " "; + result += rf->shortName(); result += min_max->to_string(); result += " "; } diff --git a/spice/WritePathSpice.cc b/spice/WritePathSpice.cc index 1368cd51..6c7034be 100644 --- a/spice/WritePathSpice.cc +++ b/spice/WritePathSpice.cc @@ -57,7 +57,7 @@ typedef int Stage; class WritePathSpice : public WriteSpice { public: - WritePathSpice(Path *path, + WritePathSpice(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, @@ -80,8 +80,8 @@ private: void writeGateStage(Stage stage); void writeStageParasitics(Stage stage); void writeSubckts(); - StdStringSet findPathCellNames(); - void findPathCellSubckts(StdStringSet &path_cell_names); + StringSet findPathCellNames(); + void findPathCellSubckts(StringSet &path_cell_names); float maxTime(); float pathMaxTime(); void writeMeasureDelayStmt(Stage stage, @@ -116,24 +116,24 @@ private: const Path *stageLoadPath(Stage stage); const TimingArc *stageGateArc(Stage stage); const TimingArc *stageWireArc(Stage stage); - Edge *stageGateEdge(Stage stage); - Edge *stageWireEdge(Stage stage); - Pin *stageGateInputPin(Stage stage); - Pin *stageDrvrPin(Stage stage); - LibertyPort *stageGateInputPort(Stage stage); - LibertyPort *stageDrvrPort(Stage stage); - Pin *stageLoadPin(Stage stage); + const Edge *stageGateEdge(Stage stage); + const Edge *stageWireEdge(Stage stage); + const Pin *stageGateInputPin(Stage stage); + const Pin *stageDrvrPin(Stage stage); + const LibertyPort *stageGateInputPort(Stage stage); + const LibertyPort *stageDrvrPort(Stage stage); + const Pin *stageLoadPin(Stage stage); const char *stageGateInputPinName(Stage stage); const char *stageDrvrPinName(Stage stage); const char *stageLoadPinName(Stage stage); - LibertyCell *stageLibertyCell(Stage stage); - Instance *stageInstance(Stage stage); + const LibertyCell *stageLibertyCell(Stage stage); + const Instance *stageInstance(Stage stage); float findSlew(const Path *path); float findSlew(const Path *path, const RiseFall *rf, const TimingArc *next_arc); - Path *path_; + const Path *path_; PathExpanded path_expanded_; // Input clock waveform cycles. int clk_cycle_count_; @@ -152,7 +152,7 @@ private: //////////////////////////////////////////////////////////////// void -writePathSpice(Path *path, +writePathSpice(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, @@ -168,7 +168,7 @@ writePathSpice(Path *path, writer.writeSpice(); } -WritePathSpice::WritePathSpice(Path *path, +WritePathSpice::WritePathSpice(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, @@ -215,10 +215,10 @@ WritePathSpice::writeHeader() { const Path *start_path = path_expanded_.startPath(); std::string title = stdstrPrint("Path from %s %s to %s %s", - network_->pathName(start_path->pin(this)), - start_path->transition(this)->to_string().c_str(), - network_->pathName(path_->pin(this)), - path_->transition(this)->to_string().c_str()); + network_->pathName(start_path->pin(this)), + start_path->transition(this)->shortName(), + network_->pathName(path_->pin(this)), + path_->transition(this)->shortName()); float max_time = maxTime(); float time_step = 1e-13; writeHeader(title, max_time, time_step); @@ -227,7 +227,7 @@ WritePathSpice::writeHeader() void WritePathSpice::writePrintStmt() { - StdStringSeq node_names; + StringSeq node_names; for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { node_names.push_back(stageDrvrPinName(stage)); node_names.push_back(stageLoadPinName(stage)); @@ -497,8 +497,8 @@ WritePathSpice::writeGateStage(Stage stage) std::string subckt_name = "stage" + std::to_string(stage); const Instance *inst = stageInstance(stage); - LibertyPort *input_port = stageGateInputPort(stage); - LibertyPort *drvr_port = stageDrvrPort(stage); + const LibertyPort *input_port = stageGateInputPort(stage); + const LibertyPort *drvr_port = stageDrvrPort(stage); streamPrint(spice_stream_, ".subckt %s %s %s %s\n", subckt_name.c_str(), @@ -515,7 +515,7 @@ WritePathSpice::writeGateStage(Stage stage) const Path *drvr_path = stageDrvrPath(stage); const RiseFall *drvr_rf = drvr_path->transition(this); - Edge *gate_edge = stageGateEdge(stage); + const Edge *gate_edge = stageGateEdge(stage); LibertyPortLogicValues port_values; bool is_clked; @@ -562,14 +562,14 @@ WritePathSpice::writeStageParasitics(Stage stage) void WritePathSpice::writeSubckts() { - StdStringSet cell_names = findPathCellNames(); + StringSet cell_names = findPathCellNames(); writeSubckts(cell_names); } -StdStringSet +StringSet WritePathSpice::findPathCellNames() { - StdStringSet path_cell_names; + StringSet path_cell_names; for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { const TimingArc *arc = stageGateArc(stage); if (arc) { @@ -579,7 +579,7 @@ WritePathSpice::findPathCellNames() path_cell_names.insert(cell->name()); } // Include side receivers. - Pin *drvr_pin = stageDrvrPin(stage); + const Pin *drvr_pin = stageDrvrPin(stage); auto pin_iter = network_->connectedPinIterator(drvr_pin); while (pin_iter->hasNext()) { const Pin *pin = pin_iter->next(); @@ -673,49 +673,49 @@ WritePathSpice::stageWireArc(Stage stage) return path_expanded_.path(path_index)->prevArc(this); } -Edge * +const Edge * WritePathSpice::stageGateEdge(Stage stage) { const Path *path = stageDrvrPath(stage); return path->prevEdge(this); } -Edge * +const Edge * WritePathSpice::stageWireEdge(Stage stage) { const Path *path = stageLoadPath(stage); return path->prevEdge(this); } -Pin * +const Pin * WritePathSpice::stageGateInputPin(Stage stage) { const Path *path = stageGateInputPath(stage); return path->pin(this); } -LibertyPort * +const LibertyPort * WritePathSpice::stageGateInputPort(Stage stage) { - Pin *pin = stageGateInputPin(stage); + const Pin *pin = stageGateInputPin(stage); return network_->libertyPort(pin); } -Pin * +const Pin * WritePathSpice::stageDrvrPin(Stage stage) { const Path *path = stageDrvrPath(stage); return path->pin(this); } -LibertyPort * +const LibertyPort * WritePathSpice::stageDrvrPort(Stage stage) { - Pin *pin = stageDrvrPin(stage); + const Pin *pin = stageDrvrPin(stage); return network_->libertyPort(pin); } -Pin * +const Pin * WritePathSpice::stageLoadPin(Stage stage) { const Path *path = stageLoadPath(stage); @@ -725,35 +725,35 @@ WritePathSpice::stageLoadPin(Stage stage) const char * WritePathSpice::stageGateInputPinName(Stage stage) { - Pin *pin = stageGateInputPin(stage); + const Pin *pin = stageGateInputPin(stage); return network_->pathName(pin); } const char * WritePathSpice::stageDrvrPinName(Stage stage) { - Pin *pin = stageDrvrPin(stage); + const Pin *pin = stageDrvrPin(stage); return network_->pathName(pin); } const char * WritePathSpice::stageLoadPinName(Stage stage) { - Pin *pin = stageLoadPin(stage); + const Pin *pin = stageLoadPin(stage); return network_->pathName(pin); } -Instance * +const Instance * WritePathSpice::stageInstance(Stage stage) { - Pin *pin = stageDrvrPin(stage); + const Pin *pin = stageDrvrPin(stage); return network_->instance(pin); } -LibertyCell * +const LibertyCell * WritePathSpice::stageLibertyCell(Stage stage) { - Pin *pin = stageDrvrPin(stage); + const Pin *pin = stageDrvrPin(stage); return network_->libertyPort(pin)->libertyCell(); } diff --git a/spice/WritePathSpice.hh b/spice/WritePathSpice.hh index a6d014d1..c8823aeb 100644 --- a/spice/WritePathSpice.hh +++ b/spice/WritePathSpice.hh @@ -24,7 +24,6 @@ #pragma once -#include "StringSet.hh" #include "CircuitSim.hh" namespace sta { @@ -35,7 +34,7 @@ class StaState; // Write a spice deck for path. // Throws FileNotReadable, FileNotWritable, SubcktEndsMissing void -writePathSpice(Path *path, +writePathSpice(const Path *path, // Spice file written for path. const char *spice_filename, // Subckts used by path included in spice file. diff --git a/spice/WriteSpice.cc b/spice/WriteSpice.cc index 9b1bf2c3..1e5cfb12 100644 --- a/spice/WriteSpice.cc +++ b/spice/WriteSpice.cc @@ -151,7 +151,7 @@ WriteSpice::writeHeader(std::string &title, } void -WriteSpice::writePrintStmt(StdStringSeq &node_names) +WriteSpice::writePrintStmt(StringSeq &node_names) { streamPrint(spice_stream_, ".print tran"); if (ckt_sim_ == CircuitSim::xyce) { @@ -176,7 +176,7 @@ WriteSpice::replaceFileExt(std::string filename, // Write gnuplot command file for use with xyce csv file. void -WriteSpice::writeGnuplotFile(StdStringSeq &node_nanes) +WriteSpice::writeGnuplotFile(StringSeq &node_nanes) { std::string gnuplot_filename = replaceFileExt(spice_filename_, "gnuplot"); std::string csv_filename = replaceFileExt(spice_filename_, "csv"); @@ -199,7 +199,7 @@ WriteSpice::writeGnuplotFile(StdStringSeq &node_nanes) } void -WriteSpice::writeSubckts(StdStringSet &cell_names) +WriteSpice::writeSubckts(StringSet &cell_names) { findCellSubckts(cell_names); std::ifstream lib_subckts_stream(lib_subckt_filename_); @@ -209,7 +209,7 @@ WriteSpice::writeSubckts(StdStringSet &cell_names) std::string line; while (std::getline(lib_subckts_stream, line)) { // .subckt [args..] - StdStringSeq tokens = parseTokens(line, ' '); + StringSeq tokens = parseTokens(line, ' '); if (tokens.size() >= 2 && stringEqual(tokens[0].c_str(), ".subckt")) { const char *cell_name = tokens[1].c_str(); @@ -256,11 +256,11 @@ WriteSpice::writeSubckts(StdStringSet &cell_names) void WriteSpice::recordSpicePortNames(const char *cell_name, - StdStringSeq &tokens) + StringSeq &tokens) { LibertyCell *cell = network_->findLibertyCell(cell_name); if (cell) { - StdStringSeq &spice_port_names = cell_spice_port_names_[cell_name]; + StringSeq &spice_port_names = cell_spice_port_names_[cell_name]; for (size_t i = 2; i < tokens.size(); i++) { const char *port_name = tokens[i].c_str(); LibertyPort *port = cell->findLibertyPort(port_name); @@ -278,14 +278,14 @@ WriteSpice::recordSpicePortNames(const char *cell_name, // Subckts can call subckts (asap7). void -WriteSpice::findCellSubckts(StdStringSet &cell_names) +WriteSpice::findCellSubckts(StringSet &cell_names) { std::ifstream lib_subckts_stream(lib_subckt_filename_); if (lib_subckts_stream.is_open()) { std::string line; while (std::getline(lib_subckts_stream, line)) { // .subckt [args..] - StdStringSeq tokens = parseTokens(line, ' '); + StringSeq tokens = parseTokens(line, ' '); if (tokens.size() >= 2 && stringEqual(tokens[0].c_str(), ".subckt")) { const char *cell_name = tokens[1].c_str(); @@ -298,7 +298,7 @@ WriteSpice::findCellSubckts(StdStringSet &cell_names) else { // Process previous statement. if (tolower(stmt[0]) == 'x') { - StdStringSeq tokens = parseTokens(line, ' '); + StringSeq tokens = parseTokens(line, ' '); std::string &subckt_cell = tokens[tokens.size() - 1]; cell_names.insert(subckt_cell); } @@ -323,7 +323,7 @@ WriteSpice::writeSubcktInst(const Instance *inst) const char *inst_name = network_->pathName(inst); LibertyCell *cell = network_->libertyCell(inst); const char *cell_name = cell->name(); - StdStringSeq &spice_port_names = cell_spice_port_names_[cell_name]; + StringSeq &spice_port_names = cell_spice_port_names_[cell_name]; streamPrint(spice_stream_, "x%s", inst_name); for (std::string subckt_port_name : spice_port_names) { const char *subckt_port_cname = subckt_port_name.c_str(); @@ -351,7 +351,7 @@ WriteSpice::writeSubcktInstVoltSrcs(const Instance *inst, { LibertyCell *cell = network_->libertyCell(inst); const char *cell_name = cell->name(); - StdStringSeq &spice_port_names = cell_spice_port_names_[cell_name]; + StringSeq &spice_port_names = cell_spice_port_names_[cell_name]; const char *inst_name = network_->pathName(inst); debugPrint(debug_, "write_spice", 2, "subckt %s", cell->name()); @@ -825,7 +825,7 @@ WriteSpice::railToRailSlew(float slew, //////////////////////////////////////////////////////////////// -// Find the logic values for expression inputs to enable paths from input_port. +// Find the logic values for expression inputs to sensitize the path from input_port. void WriteSpice::gatePortValues(const Pin *input_pin, const Pin *drvr_pin, diff --git a/spice/WriteSpice.hh b/spice/WriteSpice.hh index 81bd15b7..b728d154 100644 --- a/spice/WriteSpice.hh +++ b/spice/WriteSpice.hh @@ -30,7 +30,6 @@ #include #include "StaState.hh" -#include "StringSet.hh" #include "StringUtil.hh" #include "Liberty.hh" #include "GraphClass.hh" @@ -41,7 +40,7 @@ namespace sta { using ParasiticNodeMap = std::map; -using CellSpicePortNames = std::map; +using CellSpicePortNames = std::map; using LibertyPortLogicValues = std::map; // Utilities for writing a spice deck. @@ -64,12 +63,12 @@ protected: void writeHeader(std::string &title, float max_time, float time_step); - void writePrintStmt(StdStringSeq &node_names); - void writeGnuplotFile(StdStringSeq &node_nanes); - void writeSubckts(StdStringSet &cell_names); - void findCellSubckts(StdStringSet &cell_names); + void writePrintStmt(StringSeq &node_names); + void writeGnuplotFile(StringSeq &node_nanes); + void writeSubckts(StringSet &cell_names); + void findCellSubckts(StringSet &cell_names); void recordSpicePortNames(const char *cell_name, - StdStringSeq &tokens); + StringSeq &tokens); void writeSubcktInst(const Instance *inst); void writeSubcktInstVoltSrcs(const Instance *inst, LibertyPortLogicValues &port_values, diff --git a/spice/WriteSpice.i b/spice/WriteSpice.i index e7adadbe..30bf14e4 100644 --- a/spice/WriteSpice.i +++ b/spice/WriteSpice.i @@ -33,7 +33,7 @@ %inline %{ void -write_path_spice_cmd(Path *path, +write_path_spice_cmd(const Path *path, const char *spice_filename, const char *subckt_filename, const char *lib_subckt_filename, diff --git a/spice/Xyce.cc b/spice/Xyce.cc index a4a0f3b6..500a677b 100644 --- a/spice/Xyce.cc +++ b/spice/Xyce.cc @@ -37,7 +37,7 @@ namespace sta { void readXyceCsv(const char *csv_filename, // Return values. - StdStringSeq &titles, + StringSeq &titles, WaveformSeq &waveforms) { std::ifstream file(csv_filename); diff --git a/spice/Xyce.hh b/spice/Xyce.hh index ce8e5e6c..79db5821 100644 --- a/spice/Xyce.hh +++ b/spice/Xyce.hh @@ -37,7 +37,7 @@ using WaveformSeq = std::vector; void readXyceCsv(const char *csv_filename, // Return values. - StdStringSeq &titles, + StringSeq &titles, WaveformSeq &waveforms); } // namespace diff --git a/tcl/StaTclTypes.i b/tcl/StaTclTypes.i index a7a2d6eb..f8de82fd 100644 --- a/tcl/StaTclTypes.i +++ b/tcl/StaTclTypes.i @@ -27,8 +27,6 @@ #include "Machine.hh" #include "StringUtil.hh" -#include "StringSet.hh" -#include "StringSeq.hh" #include "PatternMatch.hh" #include "Network.hh" #include "Liberty.hh" @@ -53,7 +51,6 @@ namespace sta { typedef MinMaxAll MinMaxAllNull; -typedef std::vector StdStringSeq; #if TCL_MAJOR_VERSION < 9 typedef int Tcl_Size; @@ -293,53 +290,34 @@ using namespace sta; Tcl_SetResult(interp, nullptr, TCL_STATIC); } -%typemap(in) StringSeq* { - $1 = tclListSeqConstChar($input, interp); -} - -%typemap(in) StdStringSet* { +%typemap(in) StringSet* { $1 = tclListSetStdString($input, interp); } -%typemap(in) StdStringSeq { +%typemap(in) StringSeq { $1 = tclListSeqStdString($input, interp); } -%typemap(in) StdStringSeq* { - $1 = tclListSeqStdString($input, interp); +%typemap(in) const StringSeq & (StringSeq seq) { + seq = tclListSeqStdString($input, interp); + $1 = &seq; } -%typemap(out) StringSeq* { - StringSeq *strs = $1; - Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - for (const char *str : *strs) { - Tcl_Obj *obj = Tcl_NewStringObj(str, strlen(str)); - Tcl_ListObjAppendElement(interp, list, obj); - } - Tcl_SetObjResult(interp, list); +%typemap(in) StringSeq* { + $1 = tclListSeqStdStringPtr($input, interp); +} + +%typemap(in) StringSet* { + $1 = tclListSetStdString($input, interp); +} + +%typemap(in) StringSeq { + $1 = tclListSeqStdString($input, interp); } %typemap(out) StringSeq { StringSeq &strs = $1; Tcl_Obj *list = Tcl_NewListObj(0, nullptr); - for (const char *str : strs) { - Tcl_Obj *obj = Tcl_NewStringObj(str, strlen(str)); - Tcl_ListObjAppendElement(interp, list, obj); - } - Tcl_SetObjResult(interp, list); -} - -%typemap(in) StdStringSet* { - $1 = tclListSetStdString($input, interp); -} - -%typemap(in) StdStringSeq { - $1 = tclListSeqStdString($input, interp); -} - -%typemap(out) StdStringSeq { - StdStringSeq &strs = $1; - Tcl_Obj *list = Tcl_NewListObj(0, nullptr); for (const std::string &str : strs) { Tcl_Obj *obj = Tcl_NewStringObj(str.c_str(), str.size()); Tcl_ListObjAppendElement(interp, list, obj); @@ -497,7 +475,7 @@ using namespace sta; const RiseFall *rf = $1; const char *str = ""; if (rf) - str = rf->to_string().c_str(); + str = rf->shortName(); Tcl_SetResult(interp, const_cast(str), TCL_STATIC); } @@ -517,7 +495,7 @@ using namespace sta; RiseFallBoth *tr = $1; const char *str = ""; if (tr) - str = tr->asString(); + str = tr->shortName(); Tcl_SetResult(interp, const_cast(str), TCL_STATIC); } @@ -1137,10 +1115,9 @@ using namespace sta; CheckErrorSeq *check_errors = $1; for (CheckError *error : *check_errors) { Tcl_Obj *string_list = Tcl_NewListObj(0, nullptr); - for (const char *str : *error) { - size_t str_len = strlen(str); - Tcl_Obj *obj = Tcl_NewStringObj(const_cast(str), - static_cast(str_len)); + for (const std::string &str : *error) { + Tcl_Obj *obj = Tcl_NewStringObj(str.c_str(), + static_cast(str.size())); Tcl_ListObjAppendElement(interp, string_list, obj); } Tcl_ListObjAppendElement(interp, error_list, string_list); @@ -1249,10 +1226,6 @@ using namespace sta; Tcl_SetObjResult(interp,Tcl_NewDoubleObj(delayAsFloat($1))); } -%typemap(in) StringSet* { - $1 = tclListSetConstChar($input, interp); -} - %typemap(out) Mode* { const Mode *mode = $1; if (mode) diff --git a/tcl/TclTypeHelpers.cc b/tcl/TclTypeHelpers.cc index c5cc219d..48104690 100644 --- a/tcl/TclTypeHelpers.cc +++ b/tcl/TclTypeHelpers.cc @@ -30,29 +30,27 @@ namespace sta { -StringSet * -tclListSetConstChar(Tcl_Obj *const source, +StringSeq +tclListSeqStdString(Tcl_Obj *const source, Tcl_Interp *interp) { Tcl_Size argc; Tcl_Obj **argv; + StringSeq seq; if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { - StringSet *set = new StringSet; for (int i = 0; i < argc; i++) { int length; const char *str = Tcl_GetStringFromObj(argv[i], &length); - set->insert(str); + seq.push_back(str); } - return set; } - else - return nullptr; + return seq; } StringSeq * -tclListSeqConstChar(Tcl_Obj *const source, - Tcl_Interp *interp) +tclListSeqStdStringPtr(Tcl_Obj *const source, + Tcl_Interp *interp) { Tcl_Size argc; Tcl_Obj **argv; @@ -70,45 +68,7 @@ tclListSeqConstChar(Tcl_Obj *const source, return nullptr; } -StdStringSeq -tclListSeqStdString(Tcl_Obj *const source, - Tcl_Interp *interp) -{ - Tcl_Size argc; - Tcl_Obj **argv; - - StdStringSeq seq; - if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { - for (int i = 0; i < argc; i++) { - int length; - const char *str = Tcl_GetStringFromObj(argv[i], &length); - seq.push_back(str); - } - } - return seq; -} - -StdStringSeq * -tclListSeqStdStringPtr(Tcl_Obj *const source, - Tcl_Interp *interp) -{ - Tcl_Size argc; - Tcl_Obj **argv; - - if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { - StdStringSeq *seq = new StdStringSeq; - for (int i = 0; i < argc; i++) { - int length; - const char *str = Tcl_GetStringFromObj(argv[i], &length); - seq->push_back(str); - } - return seq; - } - else - return nullptr; -} - -StdStringSet * +StringSet * tclListSetStdString(Tcl_Obj *const source, Tcl_Interp *interp) { @@ -116,7 +76,7 @@ tclListSetStdString(Tcl_Obj *const source, Tcl_Obj **argv; if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) { - StdStringSet *set = new StdStringSet; + StringSet *set = new StringSet; for (int i = 0; i < argc; i++) { int length; const char *str = Tcl_GetStringFromObj(argv[i], &length); diff --git a/util/StringSeq.cc b/util/StringSeq.cc deleted file mode 100644 index f5615d6c..00000000 --- a/util/StringSeq.cc +++ /dev/null @@ -1,36 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "StringSeq.hh" - -namespace sta { - -void -deleteContents(StringSeq *strings) -{ - for (const char *string : *strings) - stringDelete(string); -} - -} // namespace diff --git a/util/StringSet.cc b/util/StringSet.cc deleted file mode 100644 index 79863547..00000000 --- a/util/StringSet.cc +++ /dev/null @@ -1,36 +0,0 @@ -// OpenSTA, Static Timing Analyzer -// Copyright (c) 2025, Parallax Software, Inc. -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. -// -// Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// -// This notice may not be removed or altered from any source distribution. - -#include "StringSet.hh" - -namespace sta { - -void -deleteContents(StringSet *strings) -{ - for (const char *string : *strings) - stringDelete(string); -} - -} // namespace diff --git a/util/StringUtil.cc b/util/StringUtil.cc index 991d25db..2b93704c 100644 --- a/util/StringUtil.cc +++ b/util/StringUtil.cc @@ -265,11 +265,11 @@ trimRight(std::string &str) str.erase(str.find_last_not_of(" ") + 1); } -StdStringSeq +StringSeq split(const std::string &text, const std::string &delims) { - StdStringSeq tokens; + StringSeq tokens; auto start = text.find_first_not_of(delims); auto end = text.find_first_of(delims, start); while (end != std::string::npos) { @@ -283,11 +283,11 @@ split(const std::string &text, } // Parse space separated tokens. -StdStringSeq +StringSeq parseTokens(const std::string &s, const char delimiter) { - StdStringSeq tokens; + StringSeq tokens; size_t i = 0; while (i < s.size()) { while (i < s.size() && std::isspace(s[i])) diff --git a/util/Transition.cc b/util/Transition.cc index 0e09243c..41b28643 100644 --- a/util/Transition.cc +++ b/util/Transition.cc @@ -44,6 +44,15 @@ RiseFall::RiseFall(const char *name, { } +const std::string & +RiseFall::to_string(bool use_short) const +{ + if (use_short) + return short_name_; + else + return name_; +} + const RiseFall * RiseFall::opposite() const { @@ -134,6 +143,15 @@ RiseFallBoth::RiseFallBoth(const char *name, { } +const std::string & +RiseFallBoth::to_string(bool use_short) const +{ + if (use_short) + return short_name_; + else + return name_; +} + const RiseFallBoth * RiseFallBoth::find(const char *tr_str) { diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index e101d0f9..de6099a5 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -285,7 +285,7 @@ VerilogReader::makeCellPorts(Cell *cell, VerilogModule *module, VerilogNetSeq *ports) { - StdStringSet port_names; + StringSet port_names; for (VerilogNet *mod_port : *ports) { const std::string &port_name = mod_port->name(); if (!port_names.contains(port_name)) { @@ -335,7 +335,7 @@ void VerilogReader::makeNamedPortRefCellPorts(Cell *cell, VerilogModule *module, VerilogNet *mod_port, - StdStringSet &port_names) + StringSet &port_names) { PortSeq *member_ports = new PortSeq; VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module,this); @@ -535,7 +535,7 @@ VerilogReader::makeModuleInst(const std::string *module_vname, if (liberty_cell && hasScalarNamedPortRefs(liberty_cell, pins)) { const int port_count = liberty_cell->portBitCount(); - StdStringSeq net_names(port_count); + StringSeq net_names(port_count); for (VerilogNet *vnet : *pins) { VerilogNetPortRefScalarNet *vpin = dynamic_cast(vnet); @@ -805,7 +805,7 @@ VerilogModule::~VerilogModule() void VerilogModule::parseStmts(VerilogReader *reader) { - StdStringSet inst_names; + StringSet inst_names; for (VerilogStmt *stmt : *stmts_) { if (stmt->isDeclaration()) parseDcl(dynamic_cast(stmt), reader); @@ -861,7 +861,7 @@ VerilogModule::parseDcl(VerilogDcl *dcl, // expansion so errors are only reported once. void VerilogModule::checkInstanceName(VerilogInst *inst, - StdStringSet &inst_names, + StringSet &inst_names, VerilogReader *reader) { std::string inst_name = inst->instanceName(); @@ -953,7 +953,7 @@ VerilogModuleInst::namedPins() VerilogLibertyInst::VerilogLibertyInst(LibertyCell *cell, const std::string &inst_name, - const StdStringSeq &net_names, + const StringSeq &net_names, VerilogAttrStmtSeq *attr_stmts, const int line) : VerilogInst(inst_name, attr_stmts, line), @@ -1080,8 +1080,8 @@ VerilogAssign::~VerilogAssign() class VerilogNullNetNameIterator : public VerilogNetNameIterator { public: - virtual bool hasNext() { return false; } - virtual const std::string &next(); + bool hasNext() override { return false; } + const std::string &next() override; }; const std::string & @@ -1095,8 +1095,8 @@ class VerilogOneNetNameIterator : public VerilogNetNameIterator { public: VerilogOneNetNameIterator(const std::string &name); - virtual bool hasNext(); - virtual const std::string &next(); + bool hasNext() override; + const std::string &next() override; protected: std::string name_; @@ -1128,8 +1128,8 @@ public: VerilogBusNetNameIterator(const std::string bus_name, int from_index, int to_index); - virtual bool hasNext(); - virtual const std::string &next(); + bool hasNext() override; + const std::string &next() override; protected: const std::string bus_name_; @@ -1182,8 +1182,8 @@ public: VerilogConstantNetNameIterator(VerilogConstantValue *value, const std::string &zero, const std::string &one); - virtual bool hasNext(); - virtual const std::string &next(); + bool hasNext() override; + const std::string &next() override; private: VerilogConstantValue *value_; @@ -1222,8 +1222,8 @@ public: VerilogModule *module, VerilogReader *reader); virtual ~VerilogNetConcatNameIterator(); - virtual bool hasNext(); - virtual const std::string &next(); + bool hasNext() override; + const std::string &next() override; private: VerilogModule *module_; @@ -2008,7 +2008,7 @@ VerilogReader::makeLibertyInst(VerilogLibertyInst *lib_inst, network_->setAttribute(inst, entry->key(), entry->value()); } } - const StdStringSeq &net_names = lib_inst->netNames(); + const StringSeq &net_names = lib_inst->netNames(); LibertyCellPortBitIterator port_iter(lib_cell); while (port_iter.hasNext()) { LibertyPort *port = port_iter.next(); diff --git a/verilog/VerilogReaderPvt.hh b/verilog/VerilogReaderPvt.hh index 6bbe8288..23f24305 100644 --- a/verilog/VerilogReaderPvt.hh +++ b/verilog/VerilogReaderPvt.hh @@ -28,7 +28,6 @@ #include #include -#include "StringSeq.hh" #include "StringUtil.hh" namespace sta { @@ -76,7 +75,7 @@ public: private: void parseStmts(VerilogReader *reader); void checkInstanceName(VerilogInst *inst, - StdStringSet &inst_names, + StringSet &inst_names, VerilogReader *reader); std::string name_; @@ -217,16 +216,16 @@ class VerilogLibertyInst : public VerilogInst public: VerilogLibertyInst(LibertyCell *cell, const std::string &inst_name, - const StdStringSeq &net_names, + const StringSeq &net_names, VerilogAttrStmtSeq *attr_stmts, const int line); virtual bool isLibertyInst() const { return true; } LibertyCell *cell() const { return cell_; } - const StdStringSeq &netNames() const { return net_names_; } + const StringSeq &netNames() const { return net_names_; } private: LibertyCell *cell_; - StdStringSeq net_names_; + StringSeq net_names_; }; // Abstract base class for nets.