diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh
index f35ad33d..b8572693 100644
--- a/include/sta/Liberty.hh
+++ b/include/sta/Liberty.hh
@@ -442,6 +442,7 @@ public:
 		    bool &exists) const;
   bool leakagePowerExists() const { return leakage_power_exists_; }
 
+  const SequentialSeq &sequentials() const { return sequentials_; }
   bool hasSequentials() const;
   // Find the sequential with the output connected to an (internal) port.
   Sequential *outputPortSequential(LibertyPort *port);
@@ -584,7 +585,6 @@ private:
   friend class LibertyCellPgPortIterator;
   friend class LibertyPort;
   friend class LibertyBuilder;
-  friend class LibertyCellSequentialIterator;
 };
 
 class LibertyCellPortIterator : public Iterator<LibertyPort*>
@@ -621,13 +621,6 @@ private:
   LibertyPgPortMap::Iterator iter_;
 };
 
-class LibertyCellSequentialIterator : public SequentialSeq::ConstIterator
-{
-public:
-  LibertyCellSequentialIterator(const LibertyCell *cell) :
-    SequentialSeq::ConstIterator(cell->sequentials_) {}
-};
-
 ////////////////////////////////////////////////////////////////
 
 class LibertyPort : public ConcretePort
diff --git a/include/sta/LibertyClass.hh b/include/sta/LibertyClass.hh
index 8b8c01e9..ee508752 100644
--- a/include/sta/LibertyClass.hh
+++ b/include/sta/LibertyClass.hh
@@ -54,7 +54,6 @@ class TimingRole;
 class Transition;
 class RiseFall;
 class RiseFallBoth;
-class LibertyCellSequentialIterator;
 
 typedef Vector<LibertyLibrary*> LibertyLibrarySeq;
 typedef Vector<LibertyCell*> LibertyCellSeq;
diff --git a/liberty/EquivCells.cc b/liberty/EquivCells.cc
index dcde932a..4a2aacd8 100644
--- a/liberty/EquivCells.cc
+++ b/liberty/EquivCells.cc
@@ -221,9 +221,7 @@ static unsigned
 hashCellSequentials(const LibertyCell *cell)
 {
   unsigned hash = 0;
-  LibertyCellSequentialIterator seq_iter(cell);
-  while (seq_iter.hasNext()) {
-    Sequential *seq = seq_iter.next();
+  for (Sequential *seq : cell->sequentials()) {
     hash += hashFuncExpr(seq->clock()) * 3;
     hash += hashFuncExpr(seq->data()) * 5;
     hash += hashPort(seq->output()) * 7;
@@ -332,11 +330,14 @@ bool
 equivCellSequentials(const LibertyCell *cell1,
 		     const LibertyCell *cell2)
 {
-  LibertyCellSequentialIterator seq_iter1(cell1);
-  LibertyCellSequentialIterator seq_iter2(cell2);
-  while (seq_iter1.hasNext() && seq_iter2.hasNext()) {
-    Sequential *seq1 = seq_iter1.next();
-    Sequential *seq2 = seq_iter2.next();
+  const SequentialSeq &seqs1 = cell1->sequentials();
+  const SequentialSeq &seqs2 = cell2->sequentials();
+  auto seq_itr1 = seqs1.begin(), seq_itr2 = seqs2.begin();
+  for (;
+       seq_itr1 != seqs1.end() && seq_itr2 != seqs2.end();
+       seq_itr1++, seq_itr2++) {
+    const Sequential *seq1 = *seq_itr1;
+    const Sequential *seq2 = *seq_itr2;
     if (!(FuncExpr::equiv(seq1->clock(), seq2->clock())
 	  && FuncExpr::equiv(seq1->data(), seq2->data())
 	  && LibertyPort::equiv(seq1->output(), seq2->output())
@@ -345,7 +346,7 @@ equivCellSequentials(const LibertyCell *cell1,
 	  && FuncExpr::equiv(seq1->preset(), seq2->preset())))
       return false;
   }
-  return !seq_iter1.hasNext() && !seq_iter2.hasNext();
+  return seq_itr1 == seqs1.end() && seq_itr2 == seqs2.end();
 }
 
 bool
diff --git a/search/FindRegister.cc b/search/FindRegister.cc
index 983d4703..63e30b32 100644
--- a/search/FindRegister.cc
+++ b/search/FindRegister.cc
@@ -235,10 +235,8 @@ FindRegVisitor::findSequential(const Pin *clk_pin,
 {
   has_seqs = false;
   matches = false;
-  LibertyCellSequentialIterator seq_iter(cell);
-  while (seq_iter.hasNext()) {
+  for (Sequential *seq : cell->sequentials()) {
     has_seqs = true;
-    Sequential *seq = seq_iter.next();
     if ((seq->isRegister() && edge_triggered)
 	|| (seq->isLatch() && latches)) {
       if (clk_rf == RiseFallBoth::riseFall()) {
diff --git a/search/Power.cc b/search/Power.cc
index f4b82a95..ae22903a 100644
--- a/search/Power.cc
+++ b/search/Power.cc
@@ -532,9 +532,7 @@ Power::seedRegOutputActivities(const Instance *inst,
 			       BfsFwdIterator &bfs)
 {
   LibertyCell *cell = network_->libertyCell(inst);
-  LibertyCellSequentialIterator seq_iter(cell);
-  while (seq_iter.hasNext()) {
-    Sequential *seq = seq_iter.next();
+  for (Sequential *seq : cell->sequentials()) {
     seedRegOutputActivities(inst, seq, seq->output(), false);
     seedRegOutputActivities(inst, seq, seq->outputInv(), true);
     // Enqueue register output pins with functions that reference