diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl
index e1cfbf71..d7a46617 100644
--- a/test/regression_vars.tcl
+++ b/test/regression_vars.tcl
@@ -152,12 +152,13 @@ record_sta_tests {
   package_require
   path_group_names
   prima3
+  report_checks_sorted
   report_checks_src_attr
   report_json1
   report_json2
   suppress_msg
   verilog_attribute
-  report_checks_sorted
+  verilog_specify
 }
 
 define_test_group fast [group_tests all]
diff --git a/test/verilog_specify.ok b/test/verilog_specify.ok
new file mode 100644
index 00000000..e69de29b
diff --git a/test/verilog_specify.tcl b/test/verilog_specify.tcl
new file mode 100644
index 00000000..f7a8cb21
--- /dev/null
+++ b/test/verilog_specify.tcl
@@ -0,0 +1,2 @@
+# try to load verilog language file
+read_verilog verilog_specify.v
\ No newline at end of file
diff --git a/test/verilog_specify.v b/test/verilog_specify.v
new file mode 100644
index 00000000..3e8f9ce6
--- /dev/null
+++ b/test/verilog_specify.v
@@ -0,0 +1,20 @@
+
+module counter(clk, reset, in, out);
+  input clk;
+  output out;
+  input reset;
+  input in;
+  wire mid;
+
+  parameter PARAM1=1;
+  parameter PARAM2="test";
+
+  specify
+    specparam SPARAM1=2;
+    specparam SPARAM2="test2";
+  endspecify
+
+  defparam _1415_.PARAM2 = 1;
+
+
+endmodule
diff --git a/verilog/VerilogLex.ll b/verilog/VerilogLex.ll
index af6a01be..e55801b6 100644
--- a/verilog/VerilogLex.ll
+++ b/verilog/VerilogLex.ll
@@ -132,6 +132,9 @@ output { return token::OUTPUT; }
 parameter { return token::PARAMETER; }
 defparam { return token::DEFPARAM; }
 reg { return token::REG; }
+specify { return token::SPECIFY; }
+endspecify { return token::ENDSPECIFY; }
+specparam { return token::SPECPARAM; }
 supply0 { return token::SUPPLY0; }
 supply1 { return token::SUPPLY1; }
 tri { return token::TRI; }
diff --git a/verilog/VerilogParse.yy b/verilog/VerilogParse.yy
index c25de12a..530e9cf2 100644
--- a/verilog/VerilogParse.yy
+++ b/verilog/VerilogParse.yy
@@ -83,6 +83,7 @@ sta::VerilogParse::error(const location_type &loc,
 }
 
 %token INT CONSTANT ID STRING MODULE ENDMODULE ASSIGN PARAMETER DEFPARAM
+%token SPECIFY ENDSPECIFY SPECPARAM
 %token WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0 REG
 %token ATTR_OPEN ATTR_CLOSED
 
@@ -99,6 +100,8 @@ sta::VerilogParse::error(const location_type &loc,
 %type <stmt> stmt declaration instance parameter parameter_dcls parameter_dcl
 %type <stmt> defparam param_values param_value port_dcl
 %type <stmt_seq> stmts stmt_seq net_assignments continuous_assign port_dcls
+%type <stmt> specify_block
+%type <stmt_seq> specify_stmts
 %type <assign> net_assignment
 %type <dcl_arg> dcl_arg
 %type <dcl_arg_seq> dcl_args
@@ -232,6 +235,7 @@ stmt:
 |	defparam
 |	declaration
 |	instance
+|	specify_block
 |	error ';'
 	{ yyerrok; $$ = nullptr; }
 	;
@@ -240,6 +244,25 @@ stmt_seq:
 	continuous_assign
 	;
 
+/* specify blocks are used by some comercial tools to convey macro timing
+ * and other metadata.
+ * Their presence is not forbidden in structural verilog, this is a placeholder
+ * that just ignores them and allows verilog processing to proceed
+ * <<TODO>> if someone in the future wants implement support for timing info
+ * via specify blocks, implement proper parsing here
+ */
+specify_block:
+	SPECIFY specify_stmts ENDSPECIFY
+	{ $$ = nullptr; }
+	;
+
+specify_stmts:
+	SPECPARAM parameter_dcl ';'
+	{ $$ = nullptr; }
+|   specify_stmts SPECPARAM parameter_dcl ';'
+	{ $$ = nullptr; }
+	;
+
 /* Parameters are parsed and ignored. */
 parameter:
 	PARAMETER parameter_dcls ';'