diff --git a/dcalc/ArnoldiDelayCalc.cc b/dcalc/ArnoldiDelayCalc.cc index 9c801e4a..5b3f278f 100644 --- a/dcalc/ArnoldiDelayCalc.cc +++ b/dcalc/ArnoldiDelayCalc.cc @@ -370,7 +370,7 @@ ArnoldiDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { input_port_ = false; - drvr_rf_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toEdge()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); drvr_parasitic_ = drvr_parasitic; ConcreteParasitic *drvr_cparasitic = diff --git a/dcalc/DelayCalc.tcl b/dcalc/DelayCalc.tcl index cd0e2fdb..5dbb9b98 100644 --- a/dcalc/DelayCalc.tcl +++ b/dcalc/DelayCalc.tcl @@ -91,9 +91,9 @@ proc report_edge_dcalc { edge corner min_max digits } { while {[$arc_iter has_next]} { set arc [$arc_iter next] set from [get_name [$from_pin port]] - set from_rf [$arc from_trans] + set from_rf [$arc from_edge] set to [get_name [$to_pin port]] - set to_rf [$arc to_trans] + set to_rf [$arc to_edge] report_line "$from $from_rf -> $to $to_rf" report_line [report_delay_calc_cmd $edge $arc $corner $min_max $digits] if { [$edge delay_annotated $arc $corner $min_max] } { diff --git a/dcalc/DmpCeff.cc b/dcalc/DmpCeff.cc index fa6c5255..3575f945 100644 --- a/dcalc/DmpCeff.cc +++ b/dcalc/DmpCeff.cc @@ -1566,7 +1566,7 @@ DmpCeffDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { input_port_ = false; - drvr_rf_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toEdge()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); drvr_parasitic_ = drvr_parasitic; GateTimingModel *model = gateModel(arc, dcalc_ap); diff --git a/dcalc/DmpDelayCalc.cc b/dcalc/DmpDelayCalc.cc index ba2e9362..2bd7f86c 100644 --- a/dcalc/DmpDelayCalc.cc +++ b/dcalc/DmpDelayCalc.cc @@ -285,7 +285,7 @@ DmpCeffTwoPoleDelayCalc::gateDelay(const LibertyCell *drvr_cell, { parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(drvr_parasitic); const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary(); - const RiseFall *rf = arc->toTrans()->asRiseFall(); + const RiseFall *rf = arc->toEdge()->asRiseFall(); vth_ = drvr_library->outputThreshold(rf); vl_ = drvr_library->slewLowerThreshold(rf); vh_ = drvr_library->slewUpperThreshold(rf); diff --git a/dcalc/GraphDelayCalc1.cc b/dcalc/GraphDelayCalc1.cc index 7d994cc0..c3dd9d0b 100644 --- a/dcalc/GraphDelayCalc1.cc +++ b/dcalc/GraphDelayCalc1.cc @@ -766,8 +766,8 @@ GraphDelayCalc1::findInputDriverDelay(LibertyCell *drvr_cell, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - if (arc->toTrans()->asRiseFall() == rf) { - float from_slew = from_slews[arc->fromTrans()->index()]; + if (arc->toEdge()->asRiseFall() == rf) { + float from_slew = from_slews[arc->fromEdge()->index()]; findInputArcDelay(drvr_cell, drvr_pin, drvr_vertex, arc, from_slew, dcalc_ap); } @@ -789,11 +789,11 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell, { debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)", arc->from()->name(), - arc->fromTrans()->asString(), + arc->fromEdge()->asString(), arc->to()->name(), - arc->toTrans()->asString(), + arc->toEdge()->asString(), arc->role()->asString()); - RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + RiseFall *drvr_rf = arc->toEdge()->asRiseFall(); if (drvr_rf) { DcalcAPIndex ap_index = dcalc_ap->index(); const Pvt *pvt = dcalc_ap->operatingConditions(); @@ -1023,7 +1023,7 @@ GraphDelayCalc1::findDriverEdgeDelays(LibertyCell *drvr_cell, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - const RiseFall *rf = arc->toTrans()->asRiseFall(); + const RiseFall *rf = arc->toEdge()->asRiseFall(); Parasitic *parasitic = arc_delay_calc->findParasitic(drvr_pin, rf, dcalc_ap); float related_out_cap = 0.0; @@ -1267,16 +1267,16 @@ GraphDelayCalc1::findArcDelay(LibertyCell *drvr_cell, ArcDelayCalc *arc_delay_calc) { bool delay_changed = false; - RiseFall *from_rf = arc->fromTrans()->asRiseFall(); - RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromEdge()->asRiseFall(); + RiseFall *drvr_rf = arc->toEdge()->asRiseFall(); if (from_rf && drvr_rf) { DcalcAPIndex ap_index = dcalc_ap->index(); debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s) corner:%s/%s", arc->from()->name(), - arc->fromTrans()->asString(), + arc->fromEdge()->asString(), arc->to()->name(), - arc->toTrans()->asString(), + arc->toEdge()->asString(), arc->role()->asString(), dcalc_ap->corner()->name(), dcalc_ap->delayMinMax()->asString()); @@ -1350,7 +1350,7 @@ GraphDelayCalc1::multiDrvrGateDelay(MultiDrvrNet *multi_drvr, intrinsic_delay, intrinsic_slew); ArcDelay parallel_delay; Slew parallel_slew; - const RiseFall *drvr_rf = arc->toTrans()->asRiseFall(); + const RiseFall *drvr_rf = arc->toEdge()->asRiseFall(); multi_drvr->parallelDelaySlew(drvr_rf, dcalc_ap, arc_delay_calc, this, parallel_delay, parallel_slew); @@ -1396,10 +1396,10 @@ GraphDelayCalc1::findMultiDrvrGateDelay(MultiDrvrNet *multi_drvr, TimingArcSetArcIterator arc_iter(arc_set1); while (arc_iter.hasNext()) { TimingArc *arc1 = arc_iter.next(); - RiseFall *drvr_rf1 = arc1->toTrans()->asRiseFall(); + RiseFall *drvr_rf1 = arc1->toEdge()->asRiseFall(); if (drvr_rf1 == drvr_rf) { Vertex *from_vertex1 = edge1->from(graph_); - RiseFall *from_rf1 = arc1->fromTrans()->asRiseFall(); + RiseFall *from_rf1 = arc1->fromEdge()->asRiseFall(); Slew from_slew1 = edgeFromSlew(from_vertex1, from_rf1, edge1, dcalc_ap); ArcDelay intrinsic_delay1; Slew intrinsic_slew1; @@ -1538,8 +1538,8 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - RiseFall *from_rf = arc->fromTrans()->asRiseFall(); - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromEdge()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; @@ -1558,9 +1558,9 @@ GraphDelayCalc1::findCheckEdgeDelays(Edge *edge, debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)", arc_set->from()->name(), - arc->fromTrans()->asString(), + arc->fromEdge()->asString(), arc_set->to()->name(), - arc->toTrans()->asString(), + arc->toEdge()->asString(), arc_set->role()->asString()); debugPrint(debug_, "delay_calc", 3, " from_slew = %s to_slew = %s", @@ -1624,8 +1624,8 @@ GraphDelayCalc1::ceff(Edge *edge, const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax()); if (pvt == nullptr) pvt = dcalc_ap->operatingConditions(); - RiseFall *from_rf = arc->fromTrans()->asRiseFall(); - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromEdge()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; @@ -1671,8 +1671,8 @@ GraphDelayCalc1::reportDelayCalc(Edge *edge, const Pvt *pvt = sdc_->pvt(inst, dcalc_ap->constraintMinMax()); if (pvt == nullptr) pvt = dcalc_ap->operatingConditions(); - RiseFall *from_rf = arc->fromTrans()->asRiseFall(); - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromEdge()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (from_rf && to_rf) { const LibertyPort *related_out_port = arc_set->relatedOut(); const Pin *related_out_pin = 0; diff --git a/dcalc/LumpedCapDelayCalc.cc b/dcalc/LumpedCapDelayCalc.cc index 69b0ec11..5d5ab7aa 100644 --- a/dcalc/LumpedCapDelayCalc.cc +++ b/dcalc/LumpedCapDelayCalc.cc @@ -174,7 +174,7 @@ LumpedCapDelayCalc::gateDelay(const LibertyCell *drvr_cell, drvr_slew = delay_zero; drvr_slew_ = 0.0; } - drvr_rf_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toEdge()->asRiseFall(); drvr_library_ = drvr_cell->libertyLibrary(); multi_drvr_slew_factor_ = 1.0F; } diff --git a/dcalc/SimpleRCDelayCalc.cc b/dcalc/SimpleRCDelayCalc.cc index 7ce21f03..7b8c3c02 100644 --- a/dcalc/SimpleRCDelayCalc.cc +++ b/dcalc/SimpleRCDelayCalc.cc @@ -67,7 +67,7 @@ SimpleRCDelayCalc::gateDelay(const LibertyCell *drvr_cell, Slew &drvr_slew) { drvr_parasitic_ = drvr_parasitic; - drvr_rf_ = arc->toTrans()->asRiseFall(); + drvr_rf_ = arc->toEdge()->asRiseFall(); drvr_cell_ = drvr_cell; drvr_library_ = drvr_cell->libertyLibrary(); pvt_ = pvt; diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index 3a52c663..47dfb2ec 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -459,7 +459,7 @@ public: LibertyPort *&enable_port, FuncExpr *&enable_func, RiseFall *&enable_rf) const; - RiseFall *latchCheckEnableTrans(TimingArcSet *check_set); + RiseFall *latchCheckEnableEdge(TimingArcSet *check_set); bool isDisabledConstraint() const { return is_disabled_constraint_; } LibertyCell *cornerCell(int ap_index); diff --git a/include/sta/TimingArc.hh b/include/sta/TimingArc.hh index 8e377fe7..b363d940 100644 --- a/include/sta/TimingArc.hh +++ b/include/sta/TimingArc.hh @@ -247,8 +247,10 @@ public: ~TimingArc(); LibertyPort *from() const { return set_->from(); } LibertyPort *to() const { return set_->to(); } - Transition *fromTrans() const { return from_rf_; } - Transition *toTrans() const { return to_rf_; } + Transition *fromEdge() const { return from_rf_; } + Transition *fromTrans() const __attribute__ ((deprecated)) { return from_rf_; } + Transition *toEdge() const { return to_rf_; } + Transition *toTrans() const __attribute__ ((deprecated)) { return to_rf_; } TimingRole *role() const { return set_->role(); } TimingArcSet *set() const { return set_; } TimingSense sense() const; diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index e1d85b3e..be683828 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -1567,7 +1567,7 @@ class LatchEnable public: LatchEnable(LibertyPort *data, LibertyPort *enable, - RiseFall *enable_rf, + RiseFall *enable_edge, FuncExpr *enable_func, LibertyPort *output, TimingArcSet *d_to_q, @@ -1577,7 +1577,7 @@ public: LibertyPort *output() const { return output_; } LibertyPort *enable() const { return enable_; } FuncExpr *enableFunc() const { return enable_func_; } - RiseFall *enableTransition() const { return enable_rf_; } + RiseFall *enableEdge() const { return enable_edge_; } TimingArcSet *dToQ() const { return d_to_q_; } TimingArcSet *enToQ() const { return en_to_q_; } TimingArcSet *setupCheck() const { return setup_check_; } @@ -1587,7 +1587,7 @@ private: LibertyPort *data_; LibertyPort *enable_; - RiseFall *enable_rf_; + RiseFall *enable_edge_; FuncExpr *enable_func_; LibertyPort *output_; TimingArcSet *d_to_q_; @@ -1597,7 +1597,7 @@ private: LatchEnable::LatchEnable(LibertyPort *data, LibertyPort *enable, - RiseFall *enable_rf, + RiseFall *enable_edge, FuncExpr *enable_func, LibertyPort *output, TimingArcSet *d_to_q, @@ -1605,7 +1605,7 @@ LatchEnable::LatchEnable(LibertyPort *data, TimingArcSet *setup_check) : data_(data), enable_(enable), - enable_rf_(enable_rf), + enable_edge_(enable_edge), enable_func_(enable_func), output_(output), d_to_q_(d_to_q), @@ -1643,8 +1643,8 @@ LibertyCell::makeLatchEnables(Report *report, TimingArcSetArcIterator check_arc_iter(setup_check); if (check_arc_iter.hasNext()) { TimingArc *check_arc = check_arc_iter.next(); - RiseFall *en_rf = latch_enable->enableTransition(); - RiseFall *check_rf = check_arc->fromTrans()->asRiseFall(); + RiseFall *en_rf = latch_enable->enableEdge(); + RiseFall *check_rf = check_arc->fromEdge()->asRiseFall(); if (check_rf == en_rf) { report->warn(4, "cell %s/%s %s -> %s latch enable %s_edge timing arc is inconsistent with %s -> %s setup_%s check.", library_->name(), @@ -1780,23 +1780,23 @@ LibertyCell::latchEnable(TimingArcSet *d_to_q_set, // Return values. LibertyPort *&enable_port, FuncExpr *&enable_func, - RiseFall *&enable_rf) const + RiseFall *&enable_edge) const { enable_port = nullptr; LatchEnable *latch_enable = latch_d_to_q_map_.findKey(d_to_q_set); if (latch_enable) { enable_port = latch_enable->enable(); enable_func = latch_enable->enableFunc(); - enable_rf = latch_enable->enableTransition(); + enable_edge = latch_enable->enableEdge(); } } RiseFall * -LibertyCell::latchCheckEnableTrans(TimingArcSet *check_set) +LibertyCell::latchCheckEnableEdge(TimingArcSet *check_set) { LatchEnable *latch_enable = latch_check_map_.findKey(check_set); if (latch_enable) - return latch_enable->enableTransition(); + return latch_enable->enableEdge(); else return nullptr; } @@ -2024,7 +2024,7 @@ LibertyPort::driveResistance(const RiseFall *rf, while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); if (rf == nullptr - || arc->toTrans()->asRiseFall() == rf) { + || arc->toEdge()->asRiseFall() == rf) { float drive = arc->driveResistance(); if (drive > 0.0) { if (min_max->compare(drive, max_drive)) @@ -2062,7 +2062,7 @@ LibertyPort::intrinsicDelay(const RiseFall *rf, while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); if (rf == nullptr - || arc->toTrans()->asRiseFall() == rf) { + || arc->toEdge()->asRiseFall() == rf) { ArcDelay delay = arc->intrinsicDelay(); if (delayGreater(delay, 0.0, sta)) { if (delayGreater(delay, max_delay, min_max, sta)) diff --git a/liberty/TimingArc.cc b/liberty/TimingArc.cc index 8d232955..ef498a3d 100644 --- a/liberty/TimingArc.cc +++ b/liberty/TimingArc.cc @@ -257,7 +257,7 @@ TimingArcSet::addTimingArc(TimingArc *arc) criticalError(243, "timing arc max index exceeded\n"); arcs_.push_back(arc); - int from_rf_index = arc->fromTrans()->asRiseFall()->index(); + int from_rf_index = arc->fromEdge()->asRiseFall()->index(); if (from_arc1_[from_rf_index] == nullptr) from_arc1_[from_rf_index] = arc; else if (from_arc2_[from_rf_index] == nullptr) @@ -277,7 +277,7 @@ TimingArcSet::deleteTimingArc(TimingArc *arc) arcs_[arc->index()] = last_arc; arcs_.pop_back(); } - int from_rf_index = arc->fromTrans()->asRiseFall()->index(); + int from_rf_index = arc->fromEdge()->asRiseFall()->index(); if (from_arc1_[from_rf_index] == arc) { from_arc1_[from_rf_index] = from_arc2_[from_rf_index]; from_arc2_[from_rf_index] = nullptr; @@ -332,13 +332,13 @@ TimingArcSet::isRisingFallingEdge() const { int arc_count = arcs_.size(); if (arc_count == 2) { - RiseFall *from_rf1 = arcs_[0]->fromTrans()->asRiseFall(); - RiseFall *from_rf2 = arcs_[1]->fromTrans()->asRiseFall(); + RiseFall *from_rf1 = arcs_[0]->fromEdge()->asRiseFall(); + RiseFall *from_rf2 = arcs_[1]->fromEdge()->asRiseFall(); if (from_rf1 == from_rf2) return from_rf1; } if (arcs_.size() == 1) - return arcs_[0]->fromTrans()->asRiseFall(); + return arcs_[0]->fromEdge()->asRiseFall(); else return nullptr; } @@ -476,15 +476,15 @@ timingArcsLess(const TimingArcSet *set1, while (arc_iter1.hasNext() && arc_iter2.hasNext()) { TimingArc *arc1 = arc_iter1.next(); TimingArc *arc2 = arc_iter2.next(); - int from_index1 = arc1->fromTrans()->index(); - int from_index2 = arc2->fromTrans()->index(); + int from_index1 = arc1->fromEdge()->index(); + int from_index2 = arc2->fromEdge()->index(); if (from_index1 < from_index2) return true; if (from_index1 > from_index2) return false; // from_index1 == from_index2 - int to_index1 = arc1->toTrans()->index(); - int to_index2 = arc2->toTrans()->index(); + int to_index1 = arc1->toEdge()->index(); + int to_index2 = arc2->toEdge()->index(); if (to_index1 < to_index2) return true; if (to_index1 > to_index2) @@ -575,8 +575,8 @@ bool TimingArc::equiv(const TimingArc *arc1, const TimingArc *arc2) { - return arc1->fromTrans() == arc2->fromTrans() - && arc1->toTrans() == arc2->toTrans(); + return arc1->fromEdge() == arc2->fromEdge() + && arc1->toEdge() == arc2->toEdge(); } void diff --git a/sdf/SdfReader.cc b/sdf/SdfReader.cc index 8c740263..dee88b66 100644 --- a/sdf/SdfReader.cc +++ b/sdf/SdfReader.cc @@ -282,7 +282,7 @@ SdfReader::setEdgeDelays(Edge *edge, if (triple_count == 1) triple_index = 0; else - triple_index = arc->toTrans()->sdfTripleIndex(); + triple_index = arc->toEdge()->sdfTripleIndex(); SdfTriple *triple = (*triples)[triple_index]; setEdgeArcDelays(edge, arc, triple); } @@ -388,8 +388,8 @@ SdfReader::iopath(SdfPortSpec *from_edge, while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); if ((from_edge->transition() == Transition::riseFall()) - || (arc->fromTrans() == from_edge->transition())) { - size_t triple_index = arc->toTrans()->sdfTripleIndex(); + || (arc->fromEdge() == from_edge->transition())) { + size_t triple_index = arc->toEdge()->sdfTripleIndex(); SdfTriple *triple = nullptr; if (triple_index < triple_count) triple = (*triples)[triple_index]; @@ -532,9 +532,9 @@ SdfReader::annotateCheckEdges(Pin *data_pin, while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); if (((data_edge->transition() == Transition::riseFall()) - || (arc->toTrans() == data_edge->transition())) + || (arc->toEdge() == data_edge->transition())) && ((clk_edge->transition() == Transition::riseFall()) - || (arc->fromTrans() == clk_edge->transition()))) { + || (arc->fromEdge() == clk_edge->transition()))) { setEdgeArcDelays(edge, arc, triple); } } diff --git a/sdf/SdfWriter.cc b/sdf/SdfWriter.cc index 61d2a96b..e1b6feff 100644 --- a/sdf/SdfWriter.cc +++ b/sdf/SdfWriter.cc @@ -425,7 +425,7 @@ SdfWriter::writeArcDelays(Edge *edge) TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - RiseFall *rf = arc->toTrans()->asRiseFall(); + RiseFall *rf = arc->toEdge()->asRiseFall(); ArcDelay min_delay = graph_->arcDelay(edge, arc, arc_delay_min_index_); delays.setValue(rf, MinMax::min(), delayAsFloat(min_delay)); @@ -582,8 +582,8 @@ SdfWriter::writeCheck(Edge *edge, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - RiseFall *clk_rf = arc->fromTrans()->asRiseFall(); - RiseFall *data_rf = arc->toTrans()->asRiseFall();; + RiseFall *clk_rf = arc->fromEdge()->asRiseFall(); + RiseFall *data_rf = arc->toEdge()->asRiseFall();; arcs[clk_rf->index()][data_rf->index()] = arc; } @@ -662,7 +662,7 @@ SdfWriter::writeCheck(Edge *edge, if (use_data_edge) gzprintf(stream_, "(%s %s)", - sdfEdge(arc->toTrans()), + sdfEdge(arc->toEdge()), sdfPortName(to_pin)); else gzprintf(stream_, "%s", sdfPortName(to_pin)); @@ -677,7 +677,7 @@ SdfWriter::writeCheck(Edge *edge, if (use_clk_edge) gzprintf(stream_, "(%s %s)", - sdfEdge(arc->fromTrans()), + sdfEdge(arc->fromEdge()), sdfPortName(from_pin)); else gzprintf(stream_, "%s", sdfPortName(from_pin)); diff --git a/search/CheckMaxSkews.cc b/search/CheckMaxSkews.cc index e9f24d44..1ae733a4 100644 --- a/search/CheckMaxSkews.cc +++ b/search/CheckMaxSkews.cc @@ -198,8 +198,8 @@ CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - RiseFall *clk_rf = arc->fromTrans()->asRiseFall(); - RiseFall *ref_rf = arc->toTrans()->asRiseFall(); + RiseFall *clk_rf = arc->fromEdge()->asRiseFall(); + RiseFall *ref_rf = arc->toEdge()->asRiseFall(); VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search); while (clk_path_iter.hasNext()) { PathVertex *clk_path = clk_path_iter.next(); diff --git a/search/FindRegister.cc b/search/FindRegister.cc index d444fd02..595bee2b 100644 --- a/search/FindRegister.cc +++ b/search/FindRegister.cc @@ -284,7 +284,7 @@ FindRegVisitor::findInferedSequential(LibertyCell *cell, TimingArcSet *set = set_iter.next(); TimingArcSetArcIterator arc_iter(set); TimingArc *arc = arc_iter.next(); - RiseFall *arc_clk_rf = arc->fromTrans()->asRiseFall(); + RiseFall *arc_clk_rf = arc->fromEdge()->asRiseFall(); bool tr_matches = (clk_rf == RiseFallBoth::riseFall() || (arc_clk_rf == clk_rf1 && clk_sense == TimingSense::positive_unate) diff --git a/search/Latches.cc b/search/Latches.cc index 0dfd5c2c..febeeb48 100644 --- a/search/Latches.cc +++ b/search/Latches.cc @@ -363,7 +363,7 @@ Latches::latchOutArrival(Path *data_path, en_clk_info->uncertainties(), path_ap, crpr_clk_path); - RiseFall *q_rf = d_q_arc->toTrans()->asRiseFall(); + RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall(); ExceptionStateSet *states = nullptr; // Latch data pin is a valid exception -from pin. if (sdc_->exceptionFromStates(data_path->pin(this), @@ -425,8 +425,8 @@ Latches::latchSetupMargin(Vertex *data_vertex, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - if (check_arc->toTrans()->asRiseFall() == data_rf - && check_arc->fromTrans()->asRiseFall() == disable_rf) + if (check_arc->toEdge()->asRiseFall() == data_rf + && check_arc->fromEdge()->asRiseFall() == disable_rf) return search_->deratedDelay(from_vertex, check_arc, edge, false, path_ap); } diff --git a/search/Property.cc b/search/Property.cc index edaff1e1..bb64d8d3 100644 --- a/search/Property.cc +++ b/search/Property.cc @@ -905,7 +905,7 @@ edgeDelayProperty(Edge *edge, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *arc = arc_iter.next(); - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (to_rf == rf) { for (auto corner : *sta->corners()) { DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max); diff --git a/search/ReportPath.cc b/search/ReportPath.cc index 31c47140..f1af4199 100644 --- a/search/ReportPath.cc +++ b/search/ReportPath.cc @@ -586,7 +586,7 @@ ReportPath::latchDesc(const PathEndLatchCheck *end) TimingArc *check_arc = end->checkArc(); TimingArcSet *check_set = check_arc->set(); LibertyCell *cell = check_set->from()->libertyCell(); - RiseFall *enable_rf = cell->latchCheckEnableTrans(check_set); + RiseFall *enable_rf = cell->latchCheckEnableEdge(check_set); return latchDesc(enable_rf); } @@ -1394,8 +1394,8 @@ ReportPath::reportShort(MaxSkewCheck *check) TimingArc *check_arc = check->checkArc(); auto what = stdstrPrint("%s (%s->%s)", clk_pin_name, - check_arc->fromTrans()->asString(), - check_arc->toTrans()->asString()); + check_arc->fromEdge()->asString(), + check_arc->toEdge()->asString()); reportDescription(what.c_str(), line); const EarlyLate *early_late = EarlyLate::early(); reportSpaceFieldDelay(check->maxSkew(this), early_late, line); @@ -1797,7 +1797,7 @@ ReportPath::clkRegLatchDesc(const PathEnd *end) { // Goofy libraries can have registers with both rising and falling // clk->q timing arcs. Try and match the timing check transition. - const RiseFall *check_clk_rf=end->checkArc()->fromTrans()->asRiseFall(); + const RiseFall *check_clk_rf=end->checkArc()->fromEdge()->asRiseFall(); TimingArcSet *clk_set = nullptr; TimingArcSet *clk_rf_set = nullptr; Vertex *tgt_clk_vertex = end->targetClkPath()->vertex(this); @@ -3286,11 +3286,11 @@ ReportPath::edgeRegLatchDesc(Edge *first_edge, } } else if (role == TimingRole::regClkToQ()) - return regDesc(first_arc->fromTrans()->asRiseFall()); + return regDesc(first_arc->fromEdge()->asRiseFall()); else if (role == TimingRole::latchEnToQ()) - return latchDesc(first_arc->fromTrans()->asRiseFall()); + return latchDesc(first_arc->fromEdge()->asRiseFall()); // Who knows... - return regDesc(first_arc->fromTrans()->asRiseFall()); + return regDesc(first_arc->fromEdge()->asRiseFall()); } const char * diff --git a/search/Search.cc b/search/Search.cc index daf43498..85543f94 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -2063,7 +2063,7 @@ PathVisitor::visitArc(const Pin *from_pin, PathAnalysisPt *path_ap) { if (arc) { - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); if (searchThru(from_vertex, from_rf, edge, to_vertex, to_rf)) return visitFromPath(from_pin, from_vertex, from_rf, from_path, edge, arc, to_pin, to_vertex, to_rf, @@ -3006,7 +3006,7 @@ Search::timingDerate(Vertex *from_vertex, TimingRole *role = edge->role(); const Pin *pin = from_vertex->pin(); if (role->isWire()) { - const RiseFall *rf = arc->toTrans()->asRiseFall(); + const RiseFall *rf = arc->toEdge()->asRiseFall(); return sdc_->timingDerateNet(pin, derate_clk_data, rf, path_ap->pathMinMax()); } @@ -3015,11 +3015,11 @@ Search::timingDerate(Vertex *from_vertex, const RiseFall *rf; if (role->isTimingCheck()) { derate_type = TimingDerateCellType::cell_check; - rf = arc->toTrans()->asRiseFall(); + rf = arc->toEdge()->asRiseFall(); } else { derate_type = TimingDerateCellType::cell_delay; - rf = arc->fromTrans()->asRiseFall(); + rf = arc->fromEdge()->asRiseFall(); } return sdc_->timingDerateInstance(pin, derate_type, derate_clk_data, rf, path_ap->pathMinMax()); diff --git a/search/SearchPred.cc b/search/SearchPred.cc index 459aee75..e5adc3a1 100644 --- a/search/SearchPred.cc +++ b/search/SearchPred.cc @@ -176,8 +176,8 @@ searchThru(const Edge *edge, const TimingArc *arc, const Graph *graph) { - RiseFall *from_rf = arc->fromTrans()->asRiseFall(); - RiseFall *to_rf = arc->toTrans()->asRiseFall(); + RiseFall *from_rf = arc->fromEdge()->asRiseFall(); + RiseFall *to_rf = arc->toEdge()->asRiseFall(); // Ignore transitions other than rise/fall. return from_rf && to_rf && searchThru(edge->from(graph), from_rf, edge, edge->to(graph), to_rf); diff --git a/search/VisitPathEnds.cc b/search/VisitPathEnds.cc index e559ac22..b6ae62f0 100644 --- a/search/VisitPathEnds.cc +++ b/search/VisitPathEnds.cc @@ -149,8 +149,8 @@ VisitPathEnds::visitCheckEnd(const Pin *pin, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - RiseFall *clk_rf = check_arc->fromTrans()->asRiseFall(); - if (check_arc->toTrans()->asRiseFall() == end_rf + RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); + if (check_arc->toEdge()->asRiseFall() == end_rf && clk_rf) { VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, clk_rf, tgt_clk_path_ap, this); @@ -253,8 +253,8 @@ VisitPathEnds::visitCheckEndUnclked(const Pin *pin, TimingArcSetArcIterator arc_iter(arc_set); while (arc_iter.hasNext()) { TimingArc *check_arc = arc_iter.next(); - RiseFall *clk_rf = check_arc->fromTrans()->asRiseFall(); - if (check_arc->toTrans()->asRiseFall() == end_rf + RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall(); + if (check_arc->toEdge()->asRiseFall() == end_rf && clk_rf && (!filtered || search_->matchesFilter(path, nullptr))) { diff --git a/tcl/Graph.tcl b/tcl/Graph.tcl index 46ad571c..bc727847 100644 --- a/tcl/Graph.tcl +++ b/tcl/Graph.tcl @@ -125,7 +125,7 @@ proc report_edge_ { edge vertex_from_name_proc vertex_to_name_proc } { if { [timing_arc_disabled $edge $arc] } { set disable_reason " disabled" } - report_line " [$arc from_trans] -> [$arc to_trans] $delays_fmt$disable_reason" + report_line " [$arc from_edge] -> [$arc to_edge] $delays_fmt$disable_reason" } $iter finish } diff --git a/tcl/Sta.tcl b/tcl/Sta.tcl index ba2b4379..6b702e90 100644 --- a/tcl/Sta.tcl +++ b/tcl/Sta.tcl @@ -721,7 +721,7 @@ proc set_assigned_delay2 {from_vertex to_vertex to_rf corner min_max delay} { while {[$arc_iter has_next]} { set arc [$arc_iter next] if { $to_rf == "rise_fall" \ - || $to_rf eq [$arc to_trans_name] } { + || $to_rf eq [$arc to_edge_name] } { set_arc_delay $edge $arc $corner $min_max $delay } } @@ -833,9 +833,9 @@ proc set_assigned_check2 { from_vertex from_rf to_vertex to_rf \ while {[$arc_iter has_next]} { set arc [$arc_iter next] if { ($from_rf eq "rise_fall" \ - || $from_rf eq [$arc from_trans_name]) \ + || $from_rf eq [$arc from_edge_name]) \ && ($to_rf eq "rise_fall" \ - || $to_rf eq [$arc to_trans_name]) \ + || $to_rf eq [$arc to_edge_name]) \ && [$arc role] eq $role \ && ($cond eq "" || [$arc sdf_cond] eq $cond) } { set_arc_delay $edge $arc $corner $min_max $check_value diff --git a/tcl/StaTcl.i b/tcl/StaTcl.i index 8d7339cd..7c0c3c0f 100644 --- a/tcl/StaTcl.i +++ b/tcl/StaTcl.i @@ -5727,10 +5727,10 @@ void finish() { delete self; } %extend TimingArc { LibertyPort *from() { return self->from(); } LibertyPort *to() { return self->to(); } -Transition *from_trans() { return self->fromTrans(); } -const char *from_trans_name() { return self->fromTrans()->asRiseFall()->name(); } -Transition *to_trans() { return self->toTrans(); } -const char *to_trans_name() { return self->toTrans()->asRiseFall()->name(); } +Transition *from_edge() { return self->fromEdge(); } +const char *from_edge_name() { return self->fromEdge()->asRiseFall()->name(); } +Transition *to_edge() { return self->toEdge(); } +const char *to_edge_name() { return self->toEdge()->asRiseFall()->name(); } TimingRole *role() { return self->role(); } } // TimingArc methods