diff --git a/liberty/test/liberty_busport_mem_iter.tcl b/liberty/test/liberty_busport_mem_iter.tcl
index 7b17d2b0..6c4a1553 100644
--- a/liberty/test/liberty_busport_mem_iter.tcl
+++ b/liberty/test/liberty_busport_mem_iter.tcl
@@ -242,10 +242,4 @@ set outfile [make_result_file liberty_busport_mem_iter_write.lib]
 sta::write_liberty fakeram45_64x7 $outfile
 
 # Read back
-# catch: roundtrip read-back of written liberty may produce parser warnings
-catch {
-  read_liberty $outfile
-} msg
-if {[string match "Error*" $msg]} {
-  puts "INFO: roundtrip issue: [string range $msg 0 80]"
-}
+read_liberty $outfile
diff --git a/liberty/test/liberty_cell_classify_pgpin.tcl b/liberty/test/liberty_cell_classify_pgpin.tcl
index 57772bc6..18a0f5c5 100644
--- a/liberty/test/liberty_cell_classify_pgpin.tcl
+++ b/liberty/test/liberty_cell_classify_pgpin.tcl
@@ -117,27 +117,6 @@ foreach cell_obj $asap7_cells {
 # Port capacitance with corner/min_max
 ############################################################
 puts "--- port capacitance corner ---"
-foreach cell_name {INV_X1 INV_X4 INV_X16 BUF_X1 BUF_X8 NAND2_X1 DFF_X1} {
-  set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
-  set port_iter [$cell liberty_port_iterator]
-  while {[$port_iter has_next]} {
-    set port [$port_iter next]
-    set dir [sta::liberty_port_direction $port]
-    if {$dir == "input"} {
-      # catch: capacitance method argument format may differ across port types
-      catch {
-        set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "max"]]
-        puts "$cell_name/[$port bus_name] cap(max)=$cap"
-      }
-      # catch: capacitance method argument format may differ across port types
-      catch {
-        set cap [$port capacitance [sta::cmd_corner] [sta::find_min_max "min"]]
-        puts "$cell_name/[$port bus_name] cap(min)=$cap"
-      }
-    }
-  }
-  $port_iter finish
-}
 
 ############################################################
 # Timing arc set queries
diff --git a/liberty/test/liberty_cell_deep.tcl b/liberty/test/liberty_cell_deep.tcl
index 7be52ff1..f384e273 100644
--- a/liberty/test/liberty_cell_deep.tcl
+++ b/liberty/test/liberty_cell_deep.tcl
@@ -69,14 +69,6 @@ foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
 ############################################################
 # Leakage power queries
 ############################################################
-foreach cell_name {INV_X1 BUF_X1 DFF_X1 NAND2_X1 NOR2_X1 AOI21_X1} {
-  # catch: cell_leakage_power is not a supported get_property property
-  catch {
-    set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
-    set lp [get_property $cell cell_leakage_power]
-    puts "$cell_name leakage_power = $lp"
-  }
-}
 
 ############################################################
 # Timing arc property queries
@@ -165,8 +157,8 @@ report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
 set outfile [make_result_file liberty_cell_deep_write.lib]
 sta::write_liberty NangateOpenCellLibrary $outfile
 
-# Read back and verify roundtrip (may have minor syntax issues)
-# catch: roundtrip read-back of written liberty may produce parser warnings
+# Read back and verify roundtrip
+# TODO: write_liberty produces liberty with syntax errors. Need to debug.
 catch {
   read_liberty $outfile
 } msg
diff --git a/liberty/test/liberty_clkgate_lvlshift.ok b/liberty/test/liberty_clkgate_lvlshift.ok
index bb487313..580a25e6 100644
--- a/liberty/test/liberty_clkgate_lvlshift.ok
+++ b/liberty/test/liberty_clkgate_lvlshift.ok
@@ -9,6 +9,42 @@ VPWRIN exists: 1
 VSS exists: 1
 FAKE_SUPPLY exists: 0
 --- clock gate cell queries ---
+sky130_fd_sc_hd__dlclkp_1 area=17.516800
+Cell sky130_fd_sc_hd__dlclkp_1
+Library sky130_fd_sc_hd__tt_025C_1v80
+File ../../test/sky130hd/sky130hd_tt.lib
+ VGND ground
+ VNB unknown
+ VPB unknown
+ VPWR power
+ CLK input 0.00-0.00
+ GATE input 0.00-0.00
+ GCLK output
+ M0 internal
+sky130_fd_sc_hd__dlclkp_2 area=18.768000
+Cell sky130_fd_sc_hd__dlclkp_2
+Library sky130_fd_sc_hd__tt_025C_1v80
+File ../../test/sky130hd/sky130hd_tt.lib
+ VGND ground
+ VNB unknown
+ VPB unknown
+ VPWR power
+ CLK input 0.00-0.00
+ GATE input 0.00-0.00
+ GCLK output
+ M0 internal
+sky130_fd_sc_hd__dlclkp_4 area=21.270399
+Cell sky130_fd_sc_hd__dlclkp_4
+Library sky130_fd_sc_hd__tt_025C_1v80
+File ../../test/sky130hd/sky130hd_tt.lib
+ VGND ground
+ VNB unknown
+ VPB unknown
+ VPWR power
+ CLK input 0.00-0.01
+ GATE input 0.00-0.00
+ GCLK output
+ M0 internal
 sky130_fd_sc_hd__sdlclkp_1 area=18.768000
   VGND dir=ground func=
   VNB dir=unknown func=
@@ -40,6 +76,27 @@ sky130_fd_sc_hd__sdlclkp_4 area=22.521601
   M0 dir=internal func=
   SCE dir=input func=
 --- level shifter cell queries ---
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 area=35.033600
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 area=35.033600
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 area=40.038399
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 area=40.038399
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 area=35.033600
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 area=35.033600
+  A dir=input
+  X dir=output
+sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 area=40.038399
+  A dir=input
+  X dir=output
 --- pg_pin queries ---
 sky130_fd_sc_hd__inv_1: pwr_pins=4 signal_pins=2
 sky130_fd_sc_hd__buf_1: pwr_pins=4 signal_pins=2
@@ -49,9 +106,20 @@ sky130_fd_sc_hd__dlclkp_1: pwr_pins=4 signal_pins=4
 sky130_fd_sc_hd__sdfxtp_1: pwr_pins=4 signal_pins=7
 --- clock gate timing arcs ---
 dlclkp_1 arc_sets = 4
+  CLK -> CLK role=width
+  CLK -> GATE role=setup
+  CLK -> GATE role=hold
+  CLK -> GCLK role=combinational
 sdlclkp_1 arc_sets = 6
+  CLK -> CLK role=width
+  CLK -> GATE role=setup
+  CLK -> GATE role=hold
+  CLK -> GCLK role=combinational
+  CLK -> SCE role=setup
+  CLK -> SCE role=hold
 --- level shifter timing arcs ---
 lsbuf_lh_hl_isowell_tap_1 arcs = 1
+  A -> X role=combinational
 --- cell classification ---
 sky130_fd_sc_hd__inv_1: is_buffer=0 is_inverter=1 is_leaf=1
 sky130_fd_sc_hd__inv_2: is_buffer=0 is_inverter=1 is_leaf=1
diff --git a/liberty/test/liberty_clkgate_lvlshift.tcl b/liberty/test/liberty_clkgate_lvlshift.tcl
index 96fe7bf7..3c4e7922 100644
--- a/liberty/test/liberty_clkgate_lvlshift.tcl
+++ b/liberty/test/liberty_clkgate_lvlshift.tcl
@@ -51,17 +51,13 @@ puts "--- clock gate cell queries ---"
 
 foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
                    sky130_fd_sc_hd__dlclkp_4} {
-  # catch: clock gate cell variant may not exist in loaded library
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name area=$area leakage=$lp"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      # Report the cell to exercise arc enumeration
-      report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name
-    }
+    # Report the cell to exercise arc enumeration
+    report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name
   }
 }
 
@@ -98,26 +94,22 @@ foreach cell_name {sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
                    sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4} {
-  # catch: level shifter cell variant may not exist in loaded library
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name area=$area leakage=$lp"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      # Iterate ports
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set dir [sta::liberty_port_direction $port]
-        set is_pwr [$port is_pwr_gnd]
-        if {!$is_pwr} {
-          puts "  [get_name $port] dir=$dir"
-        }
+    # Iterate ports
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set dir [sta::liberty_port_direction $port]
+      set is_pwr [$port is_pwr_gnd]
+      if {!$is_pwr} {
+        puts "  [get_name $port] dir=$dir"
       }
-      $port_iter finish
     }
+    $port_iter finish
   }
 }
 
@@ -155,32 +147,29 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
 ############################################################
 puts "--- clock gate timing arcs ---"
 
-# catch: dlclkp_1 cell may not exist in library
-catch {
-  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    set arc_count [llength $arcs]
-    puts "dlclkp_1 arc_sets = $arc_count"
-    foreach arc $arcs {
-      set from_port [$arc from]
-      set to_port [$arc to]
-      set role [$arc role]
-      puts "  [$arc full_name] role=[$role name]"
-    }
+set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlclkp_1]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  set arc_count [llength $arcs]
+  puts "dlclkp_1 arc_sets = $arc_count"
+  foreach arc $arcs {
+    set from_port [$arc from]
+    set to_port [$arc to]
+    set role [$arc role]
+    puts "  [$from_port bus_name] -> [$to_port bus_name] role=$role"
   }
 }
 
-# catch: sdlclkp_1 cell may not exist in library
-catch {
-  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    set arc_count [llength $arcs]
-    puts "sdlclkp_1 arc_sets = $arc_count"
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[$role name]"
-    }
+set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  set arc_count [llength $arcs]
+  puts "sdlclkp_1 arc_sets = $arc_count"
+  foreach arc $arcs {
+    set from_port [$arc from]
+    set to_port [$arc to]
+    set role [$arc role]
+    puts "  [$from_port bus_name] -> [$to_port bus_name] role=$role"
   }
 }
 
@@ -189,15 +178,15 @@ catch {
 ############################################################
 puts "--- level shifter timing arcs ---"
 
-# catch: lsbuf level shifter cell may not exist in library
-catch {
-  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    puts "lsbuf_lh_hl_isowell_tap_1 arcs = [llength $arcs]"
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[[$arc role] name]"
-    }
+set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  puts "lsbuf_lh_hl_isowell_tap_1 arcs = [llength $arcs]"
+  foreach arc $arcs {
+    set from_port [$arc from]
+    set to_port [$arc to]
+    set role [$arc role]
+    puts "  [$from_port bus_name] -> [$to_port bus_name] role=$role"
   }
 }
 
diff --git a/liberty/test/liberty_equiv_cross_lib.tcl b/liberty/test/liberty_equiv_cross_lib.tcl
index 64f9fcc4..7d9fbd3a 100644
--- a/liberty/test/liberty_equiv_cross_lib.tcl
+++ b/liberty/test/liberty_equiv_cross_lib.tcl
@@ -20,17 +20,14 @@ sta::make_equiv_cells $rvt_lib
 # Find equiv cells in ASAP7 RVT
 foreach cell_prefix {INVx BUFx} {
   foreach size {1 2 3 4 5 8 11 13 16} {
-    # catch: cell with specific size variant may not exist in library
-    catch {
-      set cell_name "${cell_prefix}${size}_ASAP7_75t_R"
-      set cell [get_lib_cell asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/$cell_name]
-      if {$cell != "NULL" && $cell ne ""} {
-        set equivs [sta::find_equiv_cells $cell]
-        if {$equivs != ""} {
-          puts "$cell_name equiv count = [llength $equivs]"
-        } else {
-          puts "$cell_name equiv count = 0"
-        }
+    set cell_name "${cell_prefix}${size}_ASAP7_75t_R"
+    set cell [get_lib_cell asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/$cell_name]
+    if {$cell != "NULL" && $cell ne ""} {
+      set equivs [sta::find_equiv_cells $cell]
+      if {$equivs != ""} {
+        puts "$cell_name equiv count = [llength $equivs]"
+      } else {
+        puts "$cell_name equiv count = 0"
       }
     }
   }
@@ -47,17 +44,14 @@ sta::make_equiv_cells $lvt_lib
 
 foreach cell_prefix {INVx BUFx} {
   foreach size {1 2 4 8} {
-    # catch: cell with specific size variant may not exist in library
-    catch {
-      set cell_name "${cell_prefix}${size}_ASAP7_75t_L"
-      set cell [get_lib_cell asap7sc7p5t_INVBUF_LVT_FF_nldm_211120/$cell_name]
-      if {$cell != "NULL" && $cell ne ""} {
-        set equivs [sta::find_equiv_cells $cell]
-        if {$equivs != ""} {
-          puts "LVT $cell_name equiv count = [llength $equivs]"
-        } else {
-          puts "LVT $cell_name equiv count = 0"
-        }
+    set cell_name "${cell_prefix}${size}_ASAP7_75t_L"
+    set cell [get_lib_cell asap7sc7p5t_INVBUF_LVT_FF_nldm_211120/$cell_name]
+    if {$cell != "NULL" && $cell ne ""} {
+      set equivs [sta::find_equiv_cells $cell]
+      if {$equivs != ""} {
+        puts "LVT $cell_name equiv count = [llength $equivs]"
+      } else {
+        puts "LVT $cell_name equiv count = 0"
       }
     }
   }
@@ -98,9 +92,8 @@ set seq_rvt_lib [lindex [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123] 0]
 sta::make_equiv_cells $seq_rvt_lib
 
 # Find equiv cells for DFF cells
-# catch: ASAP7 DFFHQNx1 cell may not exist
-catch {
-  set dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
+set dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
+if {$dff != "NULL" && $dff ne ""} {
   set equivs [sta::find_equiv_cells $dff]
   if {$equivs != ""} {
     puts "SEQ RVT DFFHQNx1 equiv count = [llength $equivs]"
@@ -113,9 +106,8 @@ catch {
 }
 
 # ICG equiv cells
-# catch: ASAP7 ICGx1 cell may not exist
-catch {
-  set icg [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
+set icg [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
+if {$icg != "NULL" && $icg ne ""} {
   set equivs [sta::find_equiv_cells $icg]
   if {$equivs != ""} {
     puts "SEQ RVT ICGx1 equiv count = [llength $equivs]"
@@ -125,9 +117,8 @@ catch {
 }
 
 # Latch equiv cells
-# catch: ASAP7 DLLx1 cell may not exist
-catch {
-  set dll [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
+set dll [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
+if {$dll != "NULL" && $dll ne ""} {
   set equivs [sta::find_equiv_cells $dll]
   if {$equivs != ""} {
     puts "SEQ RVT DLLx1 equiv count = [llength $equivs]"
@@ -137,9 +128,8 @@ catch {
 }
 
 # SDFF equiv cells
-# catch: ASAP7 SDFHQNx1 cell may not exist
-catch {
-  set sdff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R]
+set sdff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R]
+if {$sdff != "NULL" && $sdff ne ""} {
   set equivs [sta::find_equiv_cells $sdff]
   if {$equivs != ""} {
     puts "SEQ RVT SDFHQNx1 equiv count = [llength $equivs]"
@@ -167,9 +157,8 @@ set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
 sta::make_equiv_cells $sky_lib
 
 # Find equiv cells for Sky130 inverters
-# catch: find_equiv_cells may fail if equivalence mapping is not configured
-catch {
-  set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
+set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
+if {$sky_inv != "NULL" && $sky_inv ne ""} {
   set equivs [sta::find_equiv_cells $sky_inv]
   if {$equivs != ""} {
     puts "Sky130 inv_1 equiv count = [llength $equivs]"
@@ -182,9 +171,8 @@ catch {
 }
 
 # Find equiv for Sky130 DFF
-# catch: find_equiv_cells may fail if equivalence mapping is not configured
-catch {
-  set sky_dff [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1]
+set sky_dff [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1]
+if {$sky_dff != "NULL" && $sky_dff ne ""} {
   set equivs [sta::find_equiv_cells $sky_dff]
   if {$equivs != ""} {
     puts "Sky130 dfxtp_1 equiv count = [llength $equivs]"
diff --git a/liberty/test/liberty_leakage_power_deep.tcl b/liberty/test/liberty_leakage_power_deep.tcl
index e7e4d60f..5b0d1700 100644
--- a/liberty/test/liberty_leakage_power_deep.tcl
+++ b/liberty/test/liberty_leakage_power_deep.tcl
@@ -13,68 +13,8 @@ read_liberty ../../test/sky130hd/sky130hd_tt.lib
 ############################################################
 puts "--- leakage power queries ---"
 
-# Combinational cells
-foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
-                   sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2
-                   sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nand3_1
-                   sky130_fd_sc_hd__nor2_1 sky130_fd_sc_hd__nor3_1
-                   sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__or2_1
-                   sky130_fd_sc_hd__xor2_1 sky130_fd_sc_hd__xnor2_1
-                   sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1
-                   sky130_fd_sc_hd__o21a_1 sky130_fd_sc_hd__o21ai_0
-                   sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2i_1} {
-  # catch: cell may not exist or cell_leakage_power property is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage=$lp"
-    }
-  }
-}
-
-# Sequential cells (these have more leakage states)
-foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
-                   sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfstp_1
-                   sky130_fd_sc_hd__dlxtp_1 sky130_fd_sc_hd__dlxtn_1
-                   sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfrtp_1
-                   sky130_fd_sc_hd__sdfstp_1 sky130_fd_sc_hd__dfbbp_1} {
-  # catch: cell may not exist or cell_leakage_power property is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      set area [get_property $cell area]
-      puts "$cell_name leakage=$lp area=$area"
-    }
-  }
-}
-
-# Tristate cells
-foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
-                   sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
-  # catch: cell may not exist or cell_leakage_power property is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage=$lp"
-    }
-  }
-}
-
-# Clock gate cells
-foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
-                   sky130_fd_sc_hd__sdlclkp_1} {
-  # catch: cell may not exist or cell_leakage_power property is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage=$lp"
-    }
-  }
-}
+# Note: cell_leakage_power is not a supported get_property property.
+# Leakage power is exercised through report_power and report_lib_cell below.
 
 ############################################################
 # Report lib cells to exercise detailed leakage/power info
@@ -92,23 +32,6 @@ report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1
 ############################################################
 read_liberty ../../test/nangate45/Nangate45_typ.lib
 
-# Query Nangate cell leakage
-foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
-                   NAND2_X1 NOR2_X1 AND2_X1 OR2_X1 XOR2_X1
-                   AOI21_X1 OAI21_X1 MUX2_X1 HA_X1 FA_X1
-                   DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
-                   SDFF_X1 SDFFR_X1 SDFFRS_X1
-                   TINV_X1 TLAT_X1 CLKGATETST_X1} {
-  # catch: cell_leakage_power property is not supported via get_property
-  catch {
-    set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage=$lp"
-    }
-  }
-}
-
 ############################################################
 # Link design and run power analysis to exercise internal power
 ############################################################
@@ -136,19 +59,6 @@ foreach inst_name {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3} {
 ############################################################
 read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
-foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
-                   sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1} {
-  # catch: IHP cell may not exist or may not have leakage data
-  catch {
-    set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      set area [get_property $cell area]
-      puts "IHP $cell_name leakage=$lp area=$area"
-    }
-  }
-}
-
 ############################################################
 # Write liberty roundtrip for Sky130 (exercises power writer)
 ############################################################
diff --git a/liberty/test/liberty_pgpin_voltage.ok b/liberty/test/liberty_pgpin_voltage.ok
index 6e037365..82b3713f 100644
--- a/liberty/test/liberty_pgpin_voltage.ok
+++ b/liberty/test/liberty_pgpin_voltage.ok
@@ -18,7 +18,55 @@ sky130_fd_sc_hd__dlclkp_1 pg_pin_count=4
 sky130_fd_sc_hd__mux2_1 pg_pin_count=4
 sky130_fd_sc_hd__sdfxtp_1 pg_pin_count=4
 --- leakage power per-state queries ---
+sky130_fd_sc_hd__inv_1 area=3.753600
+sky130_fd_sc_hd__inv_2 area=3.753600
+sky130_fd_sc_hd__inv_4 area=6.256000
+sky130_fd_sc_hd__inv_8 area=11.260800
+sky130_fd_sc_hd__buf_1 area=3.753600
+sky130_fd_sc_hd__buf_2 area=5.004800
+sky130_fd_sc_hd__nand2_1 area=3.753600
+sky130_fd_sc_hd__nand3_1 area=5.004800
+sky130_fd_sc_hd__nor2_1 area=3.753600
+sky130_fd_sc_hd__nor3_1 area=5.004800
+sky130_fd_sc_hd__and2_1 area=6.256000
+sky130_fd_sc_hd__and3_1 area=6.256000
+sky130_fd_sc_hd__or2_1 area=6.256000
+sky130_fd_sc_hd__or3_1 area=6.256000
+sky130_fd_sc_hd__xor2_1 area=8.758400
+sky130_fd_sc_hd__xnor2_1 area=8.758400
+sky130_fd_sc_hd__a21o_1 area=7.507200
+sky130_fd_sc_hd__a21oi_1 area=5.004800
+sky130_fd_sc_hd__a22o_1 area=8.758400
+sky130_fd_sc_hd__a22oi_1 area=7.507200
+sky130_fd_sc_hd__o21a_1 area=7.507200
+sky130_fd_sc_hd__o21ai_0 area=5.004800
+sky130_fd_sc_hd__o22a_1 area=8.758400
+sky130_fd_sc_hd__o22ai_1 area=6.256000
+sky130_fd_sc_hd__mux2_1 area=11.260800
+sky130_fd_sc_hd__mux2i_1 area=10.009600
+sky130_fd_sc_hd__mux4_1 area=26.275200
+sky130_fd_sc_hd__ha_1 area=12.512000
+sky130_fd_sc_hd__fa_1 area=20.019199
+sky130_fd_sc_hd__dfxtp_1 area=20.019199
+sky130_fd_sc_hd__dfxtp_2 area=21.270399
+sky130_fd_sc_hd__dfxtp_4 area=23.772800
+sky130_fd_sc_hd__dfrtp_1 area=25.024000
+sky130_fd_sc_hd__dfrtp_2 area=26.275200
+sky130_fd_sc_hd__dfrtp_4 area=28.777599
+sky130_fd_sc_hd__dfstp_1 area=26.275200
+sky130_fd_sc_hd__dfstp_2 area=26.275200
+sky130_fd_sc_hd__dfstp_4 area=30.028799
+sky130_fd_sc_hd__dfbbp_1 area=32.531200
 Warning: liberty_pgpin_voltage.tcl line 1, cell 'sky130_fd_sc_hd__dfbbp_2' not found.
+sky130_fd_sc_hd__dlxtp_1 area=15.014400
+sky130_fd_sc_hd__dlxtn_1 area=15.014400
+sky130_fd_sc_hd__dlxbn_1 area=18.768000
+sky130_fd_sc_hd__sdfxtp_1 area=26.275200
+sky130_fd_sc_hd__sdfxtp_2 area=27.526400
+sky130_fd_sc_hd__sdfrtp_1 area=31.280001
+sky130_fd_sc_hd__sdfstp_1 area=33.782398
+sky130_fd_sc_hd__sdlclkp_1 area=18.768000
+sky130_fd_sc_hd__dlclkp_1 area=17.516800
 --- detailed cell reports with pg_pin ---
 Cell sky130_fd_sc_hd__inv_1
 Library sky130_fd_sc_hd__tt_025C_1v80
@@ -75,6 +123,22 @@ File ../../test/sky130hd/sky130hd_tt.lib
  GATE input 0.00-0.00
  GCLK output
  M0 internal
+IHP sg13g2_inv_1 area=5.443200
+IHP sg13g2_inv_1 pg_pins=0
+IHP sg13g2_buf_1 area=7.257600
+IHP sg13g2_buf_1 pg_pins=0
+IHP sg13g2_nand2_1 area=7.257600
+IHP sg13g2_nand2_1 pg_pins=0
+IHP sg13g2_nor2_1 area=7.257600
+IHP sg13g2_nor2_1 pg_pins=0
+IHP sg13g2_and2_1 area=9.072000
+IHP sg13g2_and2_1 pg_pins=0
+IHP sg13g2_or2_1 area=9.072000
+IHP sg13g2_or2_1 pg_pins=0
+IHP sg13g2_dfrbp_1 area=47.174400
+IHP sg13g2_dfrbp_1 pg_pins=0
+IHP sg13g2_dlhq_1 area=30.844801
+IHP sg13g2_dlhq_1 pg_pins=0
 Warning: liberty_pgpin_voltage.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
 Group                  Internal  Switching    Leakage      Total
                           Power      Power      Power      Power (Watts)
diff --git a/liberty/test/liberty_pgpin_voltage.tcl b/liberty/test/liberty_pgpin_voltage.tcl
index 096dfc6a..17c9598c 100644
--- a/liberty/test/liberty_pgpin_voltage.tcl
+++ b/liberty/test/liberty_pgpin_voltage.tcl
@@ -89,17 +89,14 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
                    sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2i_1
                    sky130_fd_sc_hd__mux4_1 sky130_fd_sc_hd__ha_1
                    sky130_fd_sc_hd__fa_1} {
-  # catch: cell may not exist or cell_leakage_power is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage=$lp"
-    }
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
   }
 }
 
-# Sequential cells with more leakage states
+# Sequential cells
 foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
                    sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfrtp_1
                    sky130_fd_sc_hd__dfrtp_2 sky130_fd_sc_hd__dfrtp_4
@@ -110,14 +107,10 @@ foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
                    sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
                    sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfstp_1
                    sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__dlclkp_1} {
-  # catch: cell may not exist or cell_leakage_power is not supported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      set area [get_property $cell area]
-      puts "$cell_name leakage=$lp area=$area"
-    }
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
   }
 }
 
@@ -140,25 +133,21 @@ read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
                    sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1
                    sg13g2_dfrbp_1 sg13g2_dlhq_1} {
-  # catch: IHP cell may not exist in loaded library
-  catch {
-    set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      set area [get_property $cell area]
-      puts "IHP $cell_name leakage=$lp area=$area"
-      # Query pg pins
-      set pg_count 0
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        if {[$port is_pwr_gnd]} {
-          incr pg_count
-        }
+  set cell [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "IHP $cell_name area=$area"
+    # Query pg pins
+    set pg_count 0
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      if {[$port is_pwr_gnd]} {
+        incr pg_count
       }
-      $port_iter finish
-      puts "IHP $cell_name pg_pins=$pg_count"
     }
+    $port_iter finish
+    puts "IHP $cell_name pg_pins=$pg_count"
   }
 }
 
@@ -191,10 +180,4 @@ set outfile [make_result_file liberty_pgpin_voltage_write.lib]
 sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
 
 # Read back the written library to verify
-# catch: roundtrip read-back of written liberty may produce parser warnings
-catch {
-  read_liberty $outfile
-} msg
-if {[string match "Error*" $msg]} {
-  puts "INFO: roundtrip issue: [string range $msg 0 80]"
-}
+read_liberty $outfile
diff --git a/liberty/test/liberty_power.tcl b/liberty/test/liberty_power.tcl
index 1773efa2..08e936c3 100644
--- a/liberty/test/liberty_power.tcl
+++ b/liberty/test/liberty_power.tcl
@@ -51,20 +51,11 @@ report_power -instances [get_cells {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3
 ############################################################
 
 set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "INV_X1 leakage_power: [get_property $inv_cell cell_leakage_power]" }
-
 set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "BUF_X1 leakage_power: [get_property $buf_cell cell_leakage_power]" }
 
 set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "DFF_X1 leakage_power: [get_property $dff_cell cell_leakage_power]" }
 
 set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "NAND2_X1 leakage_power: [get_property $nand_cell cell_leakage_power]" }
 
 # Area property
 puts "INV_X1 area: [get_property $inv_cell area]"
@@ -80,8 +71,6 @@ puts "INV_X1 is_buffer: [get_property $inv_cell is_buffer]"
 puts "BUF_X1 is_buffer: [get_property $buf_cell is_buffer]"
 puts "BUF_X1 is_inverter: [get_property $buf_cell is_inverter]"
 puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
-# catch: is_register is not a supported get_property property for LibertyCell
-catch { puts "DFF_X1 is_register: [get_property $dff_cell is_register]" }
 
 ############################################################
 # Write liberty and re-read (exercises writer power paths)
@@ -98,8 +87,6 @@ read_liberty ../../test/sky130hd/sky130hd_tt.lib
 
 # Query sky130 cell leakage powers
 set sky_inv [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "sky130 inv leakage: [get_property $sky_inv cell_leakage_power]" }
 puts "sky130 inv area: [get_property $sky_inv area]"
 
 # Write sky130 liberty
@@ -113,8 +100,6 @@ sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
 read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
 set ihp_inv [get_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "IHP inv leakage: [get_property $ihp_inv cell_leakage_power]" }
 puts "IHP inv area: [get_property $ihp_inv area]"
 
 ############################################################
@@ -124,10 +109,7 @@ puts "IHP inv area: [get_property $ihp_inv area]"
 read_liberty ../../test/asap7_ccsn.lib.gz
 
 set outfile3 [make_result_file liberty_power_write_ccsn.lib]
-# catch: CCSN library name may not match after loading
-catch {
-  sta::write_liberty asap7_ccsn $outfile3
-}
+sta::write_liberty asap7sc7p5t_AO_LVT_FF_ccsn_211120 $outfile3
 
 ############################################################
 # Read ASAP7 SEQ for power on sequential cells
@@ -136,6 +118,4 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 set asap7_dff [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R]
-# catch: cell_leakage_power is not a supported get_property property
-catch { puts "ASAP7 DFF leakage: [get_property $asap7_dff cell_leakage_power]" }
 puts "ASAP7 DFF area: [get_property $asap7_dff area]"
diff --git a/liberty/test/liberty_scan_signal_types.ok b/liberty/test/liberty_scan_signal_types.ok
index deca1bcd..d1a4613d 100644
--- a/liberty/test/liberty_scan_signal_types.ok
+++ b/liberty/test/liberty_scan_signal_types.ok
@@ -1,4 +1,31 @@
 --- scan DFF cell queries ---
+sky130_fd_sc_hd__sdfxtp_1 area=26.275200
+  has test_cell: yes
+  IQ dir=internal scan_type=none func=
+  IQ_N dir=internal scan_type=none func=
+  CLK dir=input scan_type=none func=
+  D dir=input scan_type=none func=
+  Q dir=output scan_type=output func=IQ
+  SCD dir=input scan_type=input func=
+  SCE dir=input scan_type=enable func=
+sky130_fd_sc_hd__sdfxtp_2 area=27.526400
+  has test_cell: yes
+  IQ dir=internal scan_type=none func=
+  IQ_N dir=internal scan_type=none func=
+  CLK dir=input scan_type=none func=
+  D dir=input scan_type=none func=
+  Q dir=output scan_type=output func=IQ
+  SCD dir=input scan_type=input func=
+  SCE dir=input scan_type=enable func=
+sky130_fd_sc_hd__sdfxtp_4 area=30.028799
+  has test_cell: yes
+  IQ dir=internal scan_type=none func=
+  IQ_N dir=internal scan_type=none func=
+  CLK dir=input scan_type=none func=
+  D dir=input scan_type=none func=
+  Q dir=output scan_type=output func=IQ
+  SCD dir=input scan_type=input func=
+  SCE dir=input scan_type=enable func=
 sky130_fd_sc_hd__sdfxbp_1 area=30.028799
   has test_cell: yes
   IQ dir=internal scan_type=none
@@ -78,18 +105,82 @@ sky130_fd_sc_hd__sdfstp_4 area=37.535999
   SET_B dir=input scan_type=none
 --- scan DFF timing arcs ---
 sky130_fd_sc_hd__sdfxtp_1 arc_sets = 8
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> CLK role=width
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> D role=setup
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> D role=hold
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> Q role=Reg Clk to Q
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> SCD role=setup
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> SCD role=hold
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> SCE role=setup
+  sky130_fd_sc_hd__sdfxtp_1 CLK -> SCE role=hold
 sky130_fd_sc_hd__sdfrtp_1 arc_sets = 12
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> CLK role=width
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=setup
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> D role=hold
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> Q role=Reg Clk to Q
+  sky130_fd_sc_hd__sdfrtp_1 RESET_B -> Q role=Reg Set/Clr
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=recovery
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> RESET_B role=removal
+  sky130_fd_sc_hd__sdfrtp_1 RESET_B -> RESET_B role=width
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=setup
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> SCD role=hold
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=setup
+  sky130_fd_sc_hd__sdfrtp_1 CLK -> SCE role=hold
 sky130_fd_sc_hd__sdfstp_1 arc_sets = 12
+  sky130_fd_sc_hd__sdfstp_1 CLK -> CLK role=width
+  sky130_fd_sc_hd__sdfstp_1 CLK -> D role=setup
+  sky130_fd_sc_hd__sdfstp_1 CLK -> D role=hold
+  sky130_fd_sc_hd__sdfstp_1 CLK -> Q role=Reg Clk to Q
+  sky130_fd_sc_hd__sdfstp_1 SET_B -> Q role=Reg Set/Clr
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=setup
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SCD role=hold
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=setup
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SCE role=hold
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=recovery
+  sky130_fd_sc_hd__sdfstp_1 CLK -> SET_B role=removal
+  sky130_fd_sc_hd__sdfstp_1 SET_B -> SET_B role=width
 SDFF_X1 test_cell=no
 SDFF_X2 test_cell=no
 SDFFR_X1 test_cell=no
 SDFFS_X1 test_cell=no
 SDFFRS_X1 test_cell=no
 CLKGATETST_X1 area=3.990000 test_cell=no
+  CLKGATETST_X1 CK -> CK role=width
+  CLKGATETST_X1 CK -> E role=hold
+  CLKGATETST_X1 CK -> E role=setup
+  CLKGATETST_X1 CK -> SE role=hold
+  CLKGATETST_X1 CK -> SE role=setup
+  CLKGATETST_X1 CK -> GCK role=combinational
+  CLKGATETST_X1 CK -> GCK role=combinational
+  CLKGATETST_X1 CK -> GCK role=combinational
+  CLKGATETST_X1 CK -> GCK role=combinational
 ASAP7 ICGx1 arc_sets = 13
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> CLK role=width
+  ICGx1_ASAP7_75t_R CLK -> CLK role=width
+  ICGx1_ASAP7_75t_R CLK -> ENA role=hold
+  ICGx1_ASAP7_75t_R CLK -> ENA role=hold
+  ICGx1_ASAP7_75t_R CLK -> ENA role=setup
+  ICGx1_ASAP7_75t_R CLK -> ENA role=setup
+  ICGx1_ASAP7_75t_R CLK -> SE role=hold
+  ICGx1_ASAP7_75t_R CLK -> SE role=hold
+  ICGx1_ASAP7_75t_R CLK -> SE role=setup
+  ICGx1_ASAP7_75t_R CLK -> SE role=setup
 DFFHQNx1_ASAP7_75t_R arcs=5
+  DFFHQNx1_ASAP7_75t_R CLK -> QN role=Reg Clk to Q
+  DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
+  DFFHQNx1_ASAP7_75t_R CLK -> CLK role=width
+  DFFHQNx1_ASAP7_75t_R CLK -> D role=hold
+  DFFHQNx1_ASAP7_75t_R CLK -> D role=setup
 Warning: liberty_scan_signal_types.tcl line 1, cell 'DFFHQx1_ASAP7_75t_R' not found.
 DFFHQNx2_ASAP7_75t_R arcs=5
+  DFFHQNx2_ASAP7_75t_R CLK -> QN role=Reg Clk to Q
+  DFFHQNx2_ASAP7_75t_R CLK -> CLK role=width
+  DFFHQNx2_ASAP7_75t_R CLK -> CLK role=width
+  DFFHQNx2_ASAP7_75t_R CLK -> D role=hold
+  DFFHQNx2_ASAP7_75t_R CLK -> D role=setup
 Warning: liberty_scan_signal_types.tcl line 1, cell 'DFFHQx2_ASAP7_75t_R' not found.
 Warning: liberty_scan_signal_types.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
 Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
diff --git a/liberty/test/liberty_scan_signal_types.tcl b/liberty/test/liberty_scan_signal_types.tcl
index 2f7e5507..1f51a9fe 100644
--- a/liberty/test/liberty_scan_signal_types.tcl
+++ b/liberty/test/liberty_scan_signal_types.tcl
@@ -15,124 +15,111 @@ puts "--- scan DFF cell queries ---"
 # sdfxtp cells are scan DFFs
 foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_2
                    sky130_fd_sc_hd__sdfxtp_4} {
-  # catch: scan cell variant may not exist in this library version
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name area=$area leakage=$lp"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      # Check test_cell
-      set tc [$cell test_cell]
-      if {$tc != "NULL" && $tc ne ""} {
-        puts "  has test_cell: yes"
-      } else {
-        puts "  has test_cell: no"
-      }
-
-      # Iterate ports and check scan_signal_type
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set dir [sta::liberty_port_direction $port]
-        set is_pwr [$port is_pwr_gnd]
-        if {!$is_pwr} {
-          set sst [$port scan_signal_type]
-          set func [$port function]
-          puts "  [get_name $port] dir=$dir scan_type=$sst func=$func"
-        }
-      }
-      $port_iter finish
+    # Check test_cell
+    set tc [$cell test_cell]
+    if {$tc != "NULL" && $tc ne ""} {
+      puts "  has test_cell: yes"
+    } else {
+      puts "  has test_cell: no"
     }
+
+    # Iterate ports and check scan_signal_type
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set dir [sta::liberty_port_direction $port]
+      set is_pwr [$port is_pwr_gnd]
+      if {!$is_pwr} {
+        set sst [$port scan_signal_type]
+        set func [$port function]
+        puts "  [get_name $port] dir=$dir scan_type=$sst func=$func"
+      }
+    }
+    $port_iter finish
   }
 }
 
 # sdfxbp cells are scan DFFs with complementary outputs
 foreach cell_name {sky130_fd_sc_hd__sdfxbp_1 sky130_fd_sc_hd__sdfxbp_2} {
-  # catch: scan cell variant may not exist in this library version
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      puts "$cell_name area=$area"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      set tc [$cell test_cell]
-      if {$tc != "NULL" && $tc ne ""} {
-        puts "  has test_cell: yes"
-      } else {
-        puts "  has test_cell: no"
-      }
-
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set is_pwr [$port is_pwr_gnd]
-        if {!$is_pwr} {
-          set dir [sta::liberty_port_direction $port]
-          set sst [$port scan_signal_type]
-          puts "  [get_name $port] dir=$dir scan_type=$sst"
-        }
-      }
-      $port_iter finish
+    set tc [$cell test_cell]
+    if {$tc != "NULL" && $tc ne ""} {
+      puts "  has test_cell: yes"
+    } else {
+      puts "  has test_cell: no"
     }
+
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set is_pwr [$port is_pwr_gnd]
+      if {!$is_pwr} {
+        set dir [sta::liberty_port_direction $port]
+        set sst [$port scan_signal_type]
+        puts "  [get_name $port] dir=$dir scan_type=$sst"
+      }
+    }
+    $port_iter finish
   }
 }
 
 # sdfrtp cells are scan DFFs with async reset
 foreach cell_name {sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_2
                    sky130_fd_sc_hd__sdfrtp_4} {
-  # catch: scan cell variant may not exist in this library version
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      puts "$cell_name area=$area"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      set tc [$cell test_cell]
-      if {$tc != "NULL" && $tc ne ""} {
-        puts "  has test_cell: yes"
-      } else {
-        puts "  has test_cell: no"
-      }
-
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set is_pwr [$port is_pwr_gnd]
-        if {!$is_pwr} {
-          set dir [sta::liberty_port_direction $port]
-          set sst [$port scan_signal_type]
-          puts "  [get_name $port] dir=$dir scan_type=$sst"
-        }
-      }
-      $port_iter finish
+    set tc [$cell test_cell]
+    if {$tc != "NULL" && $tc ne ""} {
+      puts "  has test_cell: yes"
+    } else {
+      puts "  has test_cell: no"
     }
+
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set is_pwr [$port is_pwr_gnd]
+      if {!$is_pwr} {
+        set dir [sta::liberty_port_direction $port]
+        set sst [$port scan_signal_type]
+        puts "  [get_name $port] dir=$dir scan_type=$sst"
+      }
+    }
+    $port_iter finish
   }
 }
 
 # sdfstp cells are scan DFFs with async set
 foreach cell_name {sky130_fd_sc_hd__sdfstp_1 sky130_fd_sc_hd__sdfstp_2
                    sky130_fd_sc_hd__sdfstp_4} {
-  # catch: scan cell variant may not exist in this library version
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set area [get_property $cell area]
-      puts "$cell_name area=$area"
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set area [get_property $cell area]
+    puts "$cell_name area=$area"
 
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set is_pwr [$port is_pwr_gnd]
-        if {!$is_pwr} {
-          set dir [sta::liberty_port_direction $port]
-          set sst [$port scan_signal_type]
-          puts "  [get_name $port] dir=$dir scan_type=$sst"
-        }
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set is_pwr [$port is_pwr_gnd]
+      if {!$is_pwr} {
+        set dir [sta::liberty_port_direction $port]
+        set sst [$port scan_signal_type]
+        puts "  [get_name $port] dir=$dir scan_type=$sst"
       }
-      $port_iter finish
     }
+    $port_iter finish
   }
 }
 
@@ -143,17 +130,14 @@ puts "--- scan DFF timing arcs ---"
 
 foreach cell_name {sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfrtp_1
                    sky130_fd_sc_hd__sdfstp_1} {
-  # catch: cell may not exist; timing arc iteration may fail
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set arcs [$cell timing_arc_sets]
-      set arc_count [llength $arcs]
-      puts "$cell_name arc_sets = $arc_count"
-      foreach arc $arcs {
-        set role [$arc role]
-        puts "  [$arc full_name] role=[$role name]"
-      }
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set arcs [$cell timing_arc_sets]
+    set arc_count [llength $arcs]
+    puts "$cell_name arc_sets = $arc_count"
+    foreach arc $arcs {
+      set role [$arc role]
+      puts "  [$arc full_name] role=$role"
     }
   }
 }
@@ -165,40 +149,34 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
 
 # Nangate SDFF cells
 foreach cell_name {SDFF_X1 SDFF_X2 SDFFR_X1 SDFFS_X1 SDFFRS_X1} {
-  # catch: SDFF cell variant may not exist in NangateOpenCellLibrary
-  catch {
-    set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set tc [$cell test_cell]
-      puts "$cell_name test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
+  set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set tc [$cell test_cell]
+    puts "$cell_name test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
 
-      set port_iter [$cell liberty_port_iterator]
-      while {[$port_iter has_next]} {
-        set port [$port_iter next]
-        set dir [sta::liberty_port_direction $port]
-        set sst [$port scan_signal_type]
-        if {$sst != "none"} {
-          puts "  [get_name $port] dir=$dir scan_type=$sst"
-        }
+    set port_iter [$cell liberty_port_iterator]
+    while {[$port_iter has_next]} {
+      set port [$port_iter next]
+      set dir [sta::liberty_port_direction $port]
+      set sst [$port scan_signal_type]
+      if {$sst != "none"} {
+        puts "  [get_name $port] dir=$dir scan_type=$sst"
       }
-      $port_iter finish
     }
+    $port_iter finish
   }
 }
 
 # Nangate CLKGATETST cell (clock gate test)
-# catch: CLKGATETST_X1 may not have test_cell attribute
-catch {
-  set cell [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
-  if {$cell != "NULL" && $cell ne ""} {
-    set tc [$cell test_cell]
-    set area [get_property $cell area]
-    puts "CLKGATETST_X1 area=$area test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
+set cell [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
+if {$cell != "NULL" && $cell ne ""} {
+  set tc [$cell test_cell]
+  set area [get_property $cell area]
+  puts "CLKGATETST_X1 area=$area test_cell=[expr {$tc != "NULL" ? "yes" : "no"}]"
 
-    set arcs [$cell timing_arc_sets]
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[[$arc role] name]"
-    }
+  set arcs [$cell timing_arc_sets]
+  foreach arc $arcs {
+    puts "  [$arc full_name] role=[$arc role]"
   }
 }
 
@@ -208,32 +186,26 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 # ASAP7 ICG cell has statetable (exercises clock gate paths)
-# catch: ASAP7 ICG cell may not exist in loaded library
-catch {
-  set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    puts "ASAP7 ICGx1 arc_sets = [llength $arcs]"
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[[$arc role] name]"
-    }
+set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  puts "ASAP7 ICGx1 arc_sets = [llength $arcs]"
+  foreach arc $arcs {
+    puts "  [$arc full_name] role=[$arc role]"
   }
 }
 
 # ASAP7 DFFs with scan
 foreach cell_name {DFFHQNx1_ASAP7_75t_R DFFHQx1_ASAP7_75t_R
                    DFFHQNx2_ASAP7_75t_R DFFHQx2_ASAP7_75t_R} {
-  # catch: ASAP7 DFF cell name variant may not match
-  catch {
-    set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set arcs [$cell timing_arc_sets]
-      puts "$cell_name arcs=[llength $arcs]"
-      foreach arc $arcs {
-        set role [$arc role]
-        if {[$role name] != "combinational"} {
-          puts "  [$arc full_name] role=[$role name]"
-        }
+  set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set arcs [$cell timing_arc_sets]
+    puts "$cell_name arcs=[llength $arcs]"
+    foreach arc $arcs {
+      set role [$arc role]
+      if {$role != "combinational"} {
+        puts "  [$arc full_name] role=$role"
       }
     }
   }
diff --git a/liberty/test/liberty_seq_scan_bus.ok b/liberty/test/liberty_seq_scan_bus.ok
index 54fc8647..2d110c77 100644
--- a/liberty/test/liberty_seq_scan_bus.ok
+++ b/liberty/test/liberty_seq_scan_bus.ok
@@ -43,9 +43,81 @@ OAI21_X1/A cap=0.001671
 OAI21_X1/B1 cap=0.001662
 OAI21_X1/B2 cap=0.001572
 DFF_X1 arc_sets = 5
+  DFF_X1 CK -> D role=hold
+  DFF_X1 CK -> D role=setup
+  DFF_X1 CK -> CK role=width
+  DFF_X1 CK -> Q role=Reg Clk to Q
+  DFF_X1 CK -> QN role=Reg Clk to Q
 DFFR_X1 arc_sets = 16
+  DFFR_X1 CK -> D role=hold
+  DFFR_X1 CK -> D role=setup
+  DFFR_X1 CK -> RN role=recovery
+  DFFR_X1 CK -> RN role=removal
+  DFFR_X1 RN -> RN role=width
+  DFFR_X1 CK -> CK role=width
+  DFFR_X1 CK -> Q role=Reg Clk to Q
+  DFFR_X1 RN -> Q role=Reg Set/Clr
+  DFFR_X1 RN -> Q role=Reg Set/Clr
+  DFFR_X1 RN -> Q role=Reg Set/Clr
+  DFFR_X1 RN -> Q role=Reg Set/Clr
+  DFFR_X1 CK -> QN role=Reg Clk to Q
+  DFFR_X1 RN -> QN role=Reg Set/Clr
+  DFFR_X1 RN -> QN role=Reg Set/Clr
+  DFFR_X1 RN -> QN role=Reg Set/Clr
+  DFFR_X1 RN -> QN role=Reg Set/Clr
 DFFS_X1 arc_sets = 16
+  DFFS_X1 CK -> D role=hold
+  DFFS_X1 CK -> D role=setup
+  DFFS_X1 CK -> SN role=recovery
+  DFFS_X1 CK -> SN role=removal
+  DFFS_X1 SN -> SN role=width
+  DFFS_X1 CK -> CK role=width
+  DFFS_X1 CK -> Q role=Reg Clk to Q
+  DFFS_X1 SN -> Q role=Reg Set/Clr
+  DFFS_X1 SN -> Q role=Reg Set/Clr
+  DFFS_X1 SN -> Q role=Reg Set/Clr
+  DFFS_X1 SN -> Q role=Reg Set/Clr
+  DFFS_X1 CK -> QN role=Reg Clk to Q
+  DFFS_X1 SN -> QN role=Reg Set/Clr
+  DFFS_X1 SN -> QN role=Reg Set/Clr
+  DFFS_X1 SN -> QN role=Reg Set/Clr
+  DFFS_X1 SN -> QN role=Reg Set/Clr
 DFFRS_X1 arc_sets = 35
+  DFFRS_X1 CK -> D role=hold
+  DFFRS_X1 CK -> D role=setup
+  DFFRS_X1 CK -> RN role=recovery
+  DFFRS_X1 CK -> RN role=removal
+  DFFRS_X1 RN -> RN role=width
+  DFFRS_X1 CK -> SN role=recovery
+  DFFRS_X1 CK -> SN role=removal
+  DFFRS_X1 SN -> SN role=width
+  DFFRS_X1 CK -> CK role=width
+  DFFRS_X1 CK -> Q role=Reg Clk to Q
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 RN -> Q role=Reg Set/Clr
+  DFFRS_X1 SN -> Q role=Reg Set/Clr
+  DFFRS_X1 SN -> Q role=Reg Set/Clr
+  DFFRS_X1 SN -> Q role=Reg Set/Clr
+  DFFRS_X1 SN -> Q role=Reg Set/Clr
+  DFFRS_X1 CK -> QN role=Reg Clk to Q
+  DFFRS_X1 RN -> QN role=Reg Set/Clr
+  DFFRS_X1 RN -> QN role=Reg Set/Clr
+  DFFRS_X1 RN -> QN role=Reg Set/Clr
+  DFFRS_X1 RN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
+  DFFRS_X1 SN -> QN role=Reg Set/Clr
 fakeram/clk dir=input bus=0 bundle=0 has_members=0
 fakeram/rd_out dir=output bus=1 bundle=0 has_members=1
   member_count = 7
@@ -58,7 +130,26 @@ fakeram/wd_in dir=input bus=1 bundle=0 has_members=1
 fakeram/w_mask_in dir=input bus=1 bundle=0 has_members=1
   member_count = 7
 DLLx1 arc_sets = 6
+  DLLx1_ASAP7_75t_R CLK -> Q role=Latch En to Q
+  DLLx1_ASAP7_75t_R D -> Q role=Latch D to Q
+  DLLx1_ASAP7_75t_R CLK -> CLK role=width
+  DLLx1_ASAP7_75t_R CLK -> CLK role=width
+  DLLx1_ASAP7_75t_R CLK -> D role=hold
+  DLLx1_ASAP7_75t_R CLK -> D role=setup
 ICGx1 arc_sets = 13
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> GCLK role=combinational
+  ICGx1_ASAP7_75t_R CLK -> CLK role=width
+  ICGx1_ASAP7_75t_R CLK -> CLK role=width
+  ICGx1_ASAP7_75t_R CLK -> ENA role=hold
+  ICGx1_ASAP7_75t_R CLK -> ENA role=hold
+  ICGx1_ASAP7_75t_R CLK -> ENA role=setup
+  ICGx1_ASAP7_75t_R CLK -> ENA role=setup
+  ICGx1_ASAP7_75t_R CLK -> SE role=hold
+  ICGx1_ASAP7_75t_R CLK -> SE role=hold
+  ICGx1_ASAP7_75t_R CLK -> SE role=setup
+  ICGx1_ASAP7_75t_R CLK -> SE role=setup
 Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
 Endpoint: out1 (output port clocked by clk1)
 Path Group: clk1
diff --git a/liberty/test/liberty_seq_scan_bus.tcl b/liberty/test/liberty_seq_scan_bus.tcl
index 129d40be..b2088e72 100644
--- a/liberty/test/liberty_seq_scan_bus.tcl
+++ b/liberty/test/liberty_seq_scan_bus.tcl
@@ -41,9 +41,8 @@ puts "sdfxbp_1 area = $area2"
 ############################################################
 foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
                    sky130_fd_sc_hd__ebufn_4 sky130_fd_sc_hd__ebufn_8} {
-  # catch: sky130 tristate cell may not exist or tristate_enable may be unsupported
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
+  if {$cell ne ""} {
     set area [get_property $cell area]
     puts "$cell_name area = $area"
     # Query tristate enable function
@@ -81,22 +80,6 @@ foreach cell_name {sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfstp_1
   }
 }
 
-############################################################
-# Internal power queries on various cells
-############################################################
-foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
-                   sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nor2_1
-                   sky130_fd_sc_hd__dfxtp_1} {
-  # catch: cell_leakage_power is not a supported get_property property
-  catch {
-    set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set lp [get_property $cell cell_leakage_power]
-      puts "$cell_name leakage = $lp"
-    }
-  }
-}
-
 ############################################################
 # Port function and direction queries (exercises setFunction)
 ############################################################
@@ -145,19 +128,16 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
 # Timing arc set queries (exercises makeTimingArcMap paths)
 ############################################################
 foreach cell_name {DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1} {
-  # catch: cell may not exist in this library version
-  catch {
-    set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
-    if {$cell != "NULL" && $cell ne ""} {
-      set arcs [$cell timing_arc_sets]
-      set arc_count [llength $arcs]
-      puts "$cell_name arc_sets = $arc_count"
-      foreach arc $arcs {
-        set from_port [$arc from]
-        set to_port [$arc to]
-        set role [$arc role]
-        puts "  [$arc full_name] role=[$role name]"
-      }
+  set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
+  if {$cell != "NULL" && $cell ne ""} {
+    set arcs [$cell timing_arc_sets]
+    set arc_count [llength $arcs]
+    puts "$cell_name arc_sets = $arc_count"
+    foreach arc $arcs {
+      set from_port [$arc from]
+      set to_port [$arc to]
+      set role [$arc role]
+      puts "  [$arc full_name] role=$role"
     }
   }
 }
@@ -168,32 +148,29 @@ foreach cell_name {DFF_X1 DFFR_X1 DFFS_X1 DFFRS_X1} {
 read_liberty ../../test/nangate45/fakeram45_64x7.lib
 
 # Query bus ports
-# catch: bus port iteration format may differ across library versions
-catch {
-  set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
-  if {$cell != "NULL" && $cell ne ""} {
-    set port_iter [$cell liberty_port_iterator]
-    while {[$port_iter has_next]} {
-      set port [$port_iter next]
-      set dir [sta::liberty_port_direction $port]
-      set is_bus [$port is_bus]
-      set is_bundle [$port is_bundle]
-      set has_mem [$port has_members]
-      puts "fakeram/[get_name $port] dir=$dir bus=$is_bus bundle=$is_bundle has_members=$has_mem"
-      if {$is_bus || $has_mem} {
-        # Iterate members
-        set mem_iter [$port member_iterator]
-        set mem_count 0
-        while {[$mem_iter has_next]} {
-          set mem [$mem_iter next]
-          incr mem_count
-        }
-        $mem_iter finish
-        puts "  member_count = $mem_count"
+set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
+if {$cell != "NULL" && $cell ne ""} {
+  set port_iter [$cell liberty_port_iterator]
+  while {[$port_iter has_next]} {
+    set port [$port_iter next]
+    set dir [sta::liberty_port_direction $port]
+    set is_bus [$port is_bus]
+    set is_bundle [$port is_bundle]
+    set has_mem [$port has_members]
+    puts "fakeram/[get_name $port] dir=$dir bus=$is_bus bundle=$is_bundle has_members=$has_mem"
+    if {$is_bus || $has_mem} {
+      # Iterate members
+      set mem_iter [$port member_iterator]
+      set mem_count 0
+      while {[$mem_iter has_next]} {
+        set mem [$mem_iter next]
+        incr mem_count
       }
+      $mem_iter finish
+      puts "  member_count = $mem_count"
     }
-    $port_iter finish
   }
+  $port_iter finish
 }
 
 ############################################################
@@ -202,30 +179,24 @@ catch {
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
 # Query ASAP7 latch cells
-# catch: ASAP7 DLLx1 latch cell may not exist
-catch {
-  set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    set arc_count [llength $arcs]
-    puts "DLLx1 arc_sets = $arc_count"
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[[$arc role] name]"
-    }
+set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DLLx1_ASAP7_75t_R]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  set arc_count [llength $arcs]
+  puts "DLLx1 arc_sets = $arc_count"
+  foreach arc $arcs {
+    puts "  [$arc full_name] role=[$arc role]"
   }
 }
 
 # Query ICG (Integrated Clock Gate) cell with statetable
-# catch: ASAP7 ICGx1 clock gate cell may not exist
-catch {
-  set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
-  if {$cell != "NULL" && $cell ne ""} {
-    set arcs [$cell timing_arc_sets]
-    set arc_count [llength $arcs]
-    puts "ICGx1 arc_sets = $arc_count"
-    foreach arc $arcs {
-      puts "  [$arc full_name] role=[[$arc role] name]"
-    }
+set cell [get_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R]
+if {$cell != "NULL" && $cell ne ""} {
+  set arcs [$cell timing_arc_sets]
+  set arc_count [llength $arcs]
+  puts "ICGx1 arc_sets = $arc_count"
+  foreach arc $arcs {
+    puts "  [$arc full_name] role=[$arc role]"
   }
 }
 
diff --git a/liberty/test/liberty_writer_roundtrip.ok b/liberty/test/liberty_writer_roundtrip.ok
index 4f1d3bec..29716fc9 100644
--- a/liberty/test/liberty_writer_roundtrip.ok
+++ b/liberty/test/liberty_writer_roundtrip.ok
@@ -481,6 +481,11 @@ NOR2_X1: 2 arc sets
   fall->rise
   rise->fall
   fall->rise
+AND2_X1: 2 arc sets
+  rise->rise
+  fall->fall
+  rise->rise
+  fall->fall
 OR2_X1: 2 arc sets
   rise->rise
   fall->fall
diff --git a/liberty/test/liberty_writer_roundtrip.tcl b/liberty/test/liberty_writer_roundtrip.tcl
index b0e0126d..544272b0 100644
--- a/liberty/test/liberty_writer_roundtrip.tcl
+++ b/liberty/test/liberty_writer_roundtrip.tcl
@@ -15,8 +15,7 @@ set lib [lindex [get_libs NangateOpenCellLibrary] 0]
 set outfile1 [make_result_file liberty_writer_rt1.lib]
 sta::write_liberty $lib $outfile1
 
-# Read back the written liberty (may have warnings/errors - that's ok)
-# catch: roundtrip read-back of written liberty may produce parser warnings
+# catch: write_liberty produces liberty with errors; read_liberty throws on parse failures
 catch {
   read_liberty $outfile1
 } msg
@@ -30,32 +29,26 @@ if {$msg ne ""} {
 ############################################################
 read_liberty ../../test/sky130hd/sky130hd_tt.lib
 
-# catch: library name may not match exactly after loading
-catch {
-  set sky_lib [sta::find_liberty "sky130_fd_sc_hd__tt_025C_1v80"]
-  if {$sky_lib ne ""} {
-    set outfile3 [make_result_file liberty_writer_rt_sky.lib]
-    sta::write_liberty $sky_lib $outfile3
+set sky_lib [sta::find_liberty "sky130_fd_sc_hd__tt_025C_1v80"]
+if {$sky_lib ne "NULL" && $sky_lib ne ""} {
+  set outfile3 [make_result_file liberty_writer_rt_sky.lib]
+  sta::write_liberty $sky_lib $outfile3
 
-    # catch: roundtrip read-back of written liberty may produce parser warnings
-    catch {
-      read_liberty $outfile3
-    }
-  }
+  # read_liberty on writer output is expected to fail due to port errors;
+  # use catch with rc check to allow graceful continuation
+  set rc [catch {read_liberty $outfile3} read_msg]
 }
 
+
 ############################################################
 # Read IHP library (has different cell structures)
 ############################################################
 read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 
-# catch: IHP library name may not match exactly
-catch {
-  set ihp_lib [sta::find_liberty "sg13g2_stdcell"]
-  if {$ihp_lib ne ""} {
-    set outfile4 [make_result_file liberty_writer_rt_ihp.lib]
-    sta::write_liberty $ihp_lib $outfile4
-  }
+set ihp_lib [sta::find_liberty "sg13g2_stdcell_typ_1p20V_25C"]
+if {$ihp_lib ne "NULL" && $ihp_lib ne ""} {
+  set outfile4 [make_result_file liberty_writer_rt_ihp.lib]
+  sta::write_liberty $ihp_lib $outfile4
 }
 
 ############################################################
@@ -68,9 +61,9 @@ catch {
 foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
                    XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
                    FA_X1 HA_X1} {
-  # catch: some cells (e.g. FA_X1, HA_X1) may not exist in all library versions
-  catch {
-    set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
+  # Use lindex to handle potential duplicate libraries from re-read
+  set cell [lindex [get_lib_cell NangateOpenCellLibrary/$cell_name] 0]
+  if {$cell ne ""} {
     set arc_sets [$cell timing_arc_sets]
     puts "$cell_name: [llength $arc_sets] arc sets"
     foreach arc_set $arc_sets {
@@ -136,11 +129,8 @@ foreach cell_name {TLAT_X1} {
 ############################################################
 read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 
-# catch: ASAP7 library name may not match exactly
-catch {
-  set asap7_lib [sta::find_liberty "asap7sc7p5t_SEQ_RVT_FF_nldm_220123"]
-  if {$asap7_lib ne ""} {
-    set outfile5 [make_result_file liberty_writer_rt_asap7.lib]
-    sta::write_liberty $asap7_lib $outfile5
-  }
+set asap7_lib [sta::find_liberty "asap7sc7p5t_SEQ_RVT_FF_nldm_220123"]
+if {$asap7_lib ne "NULL" && $asap7_lib ne ""} {
+  set outfile5 [make_result_file liberty_writer_rt_asap7.lib]
+  sta::write_liberty $asap7_lib $outfile5
 }
diff --git a/sdc/test/sdc_clock_operations.tcl b/sdc/test/sdc_clock_operations.tcl
index d17ca6cd..4badd70b 100644
--- a/sdc/test/sdc_clock_operations.tcl
+++ b/sdc/test/sdc_clock_operations.tcl
@@ -55,11 +55,10 @@ create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [
 report_checks
 
 puts "--- generated clock invert ---"
-# catch: -invert with -divide_by 1 and -add may conflict with existing clock on this pin
-catch {
-  create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
-  report_checks
-}
+# -invert with -divide_by 1 and -add on a pin that already has a generated clock
+# Commented out: -add requires -master_clock when multiple clocks drive this pin
+# create_generated_clock -name gclk_inv -source [get_ports clk1] -divide_by 1 -invert [get_pins reg1/Q] -add
+# report_checks
 
 ############################################################
 # Propagated clock
diff --git a/sdc/test/sdc_delay_borrow_group.tcl b/sdc/test/sdc_delay_borrow_group.tcl
index e7f91b59..6fa795e4 100644
--- a/sdc/test/sdc_delay_borrow_group.tcl
+++ b/sdc/test/sdc_delay_borrow_group.tcl
@@ -159,10 +159,8 @@ set_min_delay -from [get_ports in3] -to [get_ports out2] 0.5
 ############################################################
 # Min fanout limit (covers setMinFanout through set_min_fanout if available)
 ############################################################
-# catch: set_min_fanout is not a valid SDC command in OpenSTA
-catch {
-  set_min_fanout 2 [current_design]
-}
+# set_min_fanout is not a valid SDC command in OpenSTA
+# set_min_fanout 2 [current_design]
 
 ############################################################
 # Write SDC
diff --git a/sdc/test/sdc_design_rules_limits.tcl b/sdc/test/sdc_design_rules_limits.tcl
index b34e600c..3ca49475 100644
--- a/sdc/test/sdc_design_rules_limits.tcl
+++ b/sdc/test/sdc_design_rules_limits.tcl
@@ -68,11 +68,9 @@ set_max_fanout 20 [current_design]
 set_max_fanout 10 [get_ports in1]
 set_max_fanout 15 [get_ports in2]
 
-# catch: set_max_fanout on a liberty cell object is not supported
-catch {
-  # Cell-level fanout limit
-  set_max_fanout 8 [get_lib_cells NangateOpenCellLibrary/INV_X1]
-}
+# Cell-level fanout limit
+# set_max_fanout on a liberty cell object is not supported in OpenSTA
+# set_max_fanout 8 [get_lib_cells NangateOpenCellLibrary/INV_X1]
 
 ############################################################
 # Max area
diff --git a/sdc/test/sdc_genclk_advanced.tcl b/sdc/test/sdc_genclk_advanced.tcl
index 8c5dca39..33980e97 100644
--- a/sdc/test/sdc_genclk_advanced.tcl
+++ b/sdc/test/sdc_genclk_advanced.tcl
@@ -47,19 +47,15 @@ create_generated_clock -name gclk_mul2 -source [get_ports clk1] -multiply_by 2 [
 ############################################################
 
 # Edge-based generated clock
-# catch: -edges with -add may conflict with existing generated clock on this pin
-catch {
-  create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg1/Q] -add
-}
+# Commented out: -add requires -master_clock when multiple clocks drive this pin
+# create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg1/Q] -add
 
 ############################################################
 # Generated clock - edge shift
 ############################################################
 
-# catch: -edge_shift with -edges and -add is an unsupported option combination
-catch {
-  create_generated_clock -name gclk_shift -source [get_ports clk2] -edges {1 3 5} -edge_shift {0.0 0.5 1.0} [get_pins reg3/Q] -add
-}
+# Commented out: -add requires -master_clock when multiple clocks drive this pin
+# create_generated_clock -name gclk_shift -source [get_ports clk2] -edges {1 3 5} -edge_shift {0.0 0.5 1.0} [get_pins reg3/Q] -add
 
 ############################################################
 # Report clock properties after generated clocks
diff --git a/sdc/test/sdc_port_delay_advanced.tcl b/sdc/test/sdc_port_delay_advanced.tcl
index 73718e0b..0b92f50a 100644
--- a/sdc/test/sdc_port_delay_advanced.tcl
+++ b/sdc/test/sdc_port_delay_advanced.tcl
@@ -134,10 +134,8 @@ set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
 
 set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
 
-# catch: -clock_fall is not a valid option for set_data_check
-catch {
-  set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6 -clock_fall
-}
+# -clock_fall is not a valid option for set_data_check
+# set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6 -clock_fall
 
 ############################################################
 # Case analysis and logic values (Constants)
diff --git a/sdc/test/sdc_variables.tcl b/sdc/test/sdc_variables.tcl
index 1f3d0c1f..72bad850 100644
--- a/sdc/test/sdc_variables.tcl
+++ b/sdc/test/sdc_variables.tcl
@@ -144,12 +144,11 @@ set val $::sta_propagate_gated_clock_enable
 # POCV enabled (may require SSTA compilation, use catch)
 ############################################################
 
-# catch: POCV variables may not exist if SSTA is not compiled in
-catch {
-  set ::sta_pocv_enabled 1
-  set ::sta_pocv_enabled 0
-  set val $::sta_pocv_enabled
-}
+# POCV variables may not exist if SSTA is not compiled in
+# Commented out: POCV support requires compilation with SSTA=1
+# set ::sta_pocv_enabled 1
+# set ::sta_pocv_enabled 0
+# set val $::sta_pocv_enabled
 
 ############################################################
 # Report default digits
diff --git a/search/test/search_limits_verbose.tcl b/search/test/search_limits_verbose.tcl
index 7564fb67..065fc82b 100644
--- a/search/test/search_limits_verbose.tcl
+++ b/search/test/search_limits_verbose.tcl
@@ -211,21 +211,9 @@ check_setup -verbose -loops
 # max_slew_check_slack_limit / max_cap_check_slack_limit / etc.
 ############################################################
 puts "--- slack/limit ratios ---"
-# catch: max_slew_check_slack_limit is not exposed as Tcl command
-catch {
-  set sr [max_slew_check_slack_limit]
-  puts "slew slack/limit: $sr"
-}
-# catch: max_capacitance_check_slack_limit is not exposed as Tcl command
-catch {
-  set cr [max_capacitance_check_slack_limit]
-  puts "cap slack/limit: $cr"
-}
-# catch: max_fanout_check_slack_limit is not exposed as Tcl command
-catch {
-  set fr [max_fanout_check_slack_limit]
-  puts "fanout slack/limit: $fr"
-}
+# max_slew_check_slack_limit is not exposed as Tcl command; removed
+# max_capacitance_check_slack_limit is not exposed as Tcl command; removed
+# max_fanout_check_slack_limit is not exposed as Tcl command; removed
 
 ############################################################
 # Endpoint violation counts
diff --git a/search/test/search_multiclock.tcl b/search/test/search_multiclock.tcl
index b0ff22dc..49e66c01 100644
--- a/search/test/search_multiclock.tcl
+++ b/search/test/search_multiclock.tcl
@@ -41,8 +41,6 @@ puts "--- group_path with -weight ---"
 group_path -name weighted_group -from [get_ports in1] -weight 2.0
 
 puts "--- group_path with -default ---"
-# catch: group_path -name and -default are mutually exclusive; -default also requires path args
-catch { group_path -name default_group -default }
 
 puts "--- report_checks with -group filter ---"
 report_checks -path_delay max -group_path_count 3
diff --git a/search/test/search_multicorner_analysis.tcl b/search/test/search_multicorner_analysis.tcl
index 8062753e..06cc9454 100644
--- a/search/test/search_multicorner_analysis.tcl
+++ b/search/test/search_multicorner_analysis.tcl
@@ -124,8 +124,3 @@ puts "--- set_max_area ---"
 set_max_area 1000
 
 puts "--- isClock / isPropagatedClock queries ---"
-# catch: sta::is_clock_pin is not exposed as Tcl command
-catch {
-  set clk_pin [get_pins ckbuf/Z]
-  puts "isClock ckbuf/Z: [sta::is_clock_pin $clk_pin]"
-}
diff --git a/search/test/search_network_edit_deep.tcl b/search/test/search_network_edit_deep.tcl
index c01d5a8e..161f63a6 100644
--- a/search/test/search_network_edit_deep.tcl
+++ b/search/test/search_network_edit_deep.tcl
@@ -50,8 +50,9 @@ puts "--- slow_drivers 5 ---"
 set slow5 [sta::slow_drivers 5]
 puts "slow_drivers(5): [llength $slow5]"
 foreach s $slow5 {
-  # catch: slow_drivers may return objects that don't support get_full_name
-  catch { puts "  [get_full_name $s]" }
+  if { $s != "NULL" } {
+    puts "  [get_full_name $s]"
+  }
 }
 
 ############################################################
diff --git a/search/test/search_path_enum_groups.tcl b/search/test/search_path_enum_groups.tcl
index bde0a8ab..5e9be614 100644
--- a/search/test/search_path_enum_groups.tcl
+++ b/search/test/search_path_enum_groups.tcl
@@ -79,11 +79,7 @@ puts "input_paths is group: [sta::is_path_group_name input_paths]"
 puts "nonexistent is group: [sta::is_path_group_name nonexistent_group]"
 
 puts "--- group_path -default ---"
-# catch: group_path -name and -default are mutually exclusive; -default also requires path args
-catch {
-  group_path -name default_group -default
-  report_checks -path_delay max
-}
+# group_path -name and -default are mutually exclusive; removed
 
 puts "--- report_path_ends ---"
 set pe_list [find_timing_paths -path_delay max -endpoint_path_count 5]
diff --git a/search/test/search_port_pin_properties.tcl b/search/test/search_port_pin_properties.tcl
index a173046a..1cafba9e 100644
--- a/search/test/search_port_pin_properties.tcl
+++ b/search/test/search_port_pin_properties.tcl
@@ -137,8 +137,6 @@ puts "DFF_X1 is_buffer: [get_property $dff_cell is_buffer]"
 set dff_lib [get_property $dff_cell library]
 puts "DFF_X1 library: [get_name $dff_lib]"
 puts "DFF_X1 area: [get_property $dff_cell area]"
-# catch: 'cell_leakage_power' is not a supported get_property property
-catch { puts "DFF_X1 leakage: [get_property $dff_cell cell_leakage_power]" }
 
 puts "--- LibertyPort properties ---"
 set lp_d [get_lib_pins NangateOpenCellLibrary/DFF_X1/D]
@@ -147,12 +145,10 @@ puts "DFF_X1/D full_name: [get_property $lp_d full_name]"
 puts "DFF_X1/D direction: [get_property $lp_d direction]"
 puts "DFF_X1/D capacitance: [get_property $lp_d capacitance]"
 puts "DFF_X1/D is_clock: [get_property $lp_d is_clock]"
-# catch: 'is_register_clock' property may not be valid for data pins
-catch { puts "DFF_X1/D is_register_clock: [get_property $lp_d is_register_clock]" }
+puts "DFF_X1/D is_register_clock: [get_property $lp_d is_register_clock]"
 set lp_ck [get_lib_pins NangateOpenCellLibrary/DFF_X1/CK]
 puts "DFF_X1/CK is_clock: [get_property $lp_ck is_clock]"
-# catch: 'is_register_clock' property may not be valid for clock pins
-catch { puts "DFF_X1/CK is_register_clock: [get_property $lp_ck is_register_clock]" }
+puts "DFF_X1/CK is_register_clock: [get_property $lp_ck is_register_clock]"
 
 puts "--- Library properties ---"
 set lib [get_libs NangateOpenCellLibrary]
diff --git a/search/test/search_power_activity.ok b/search/test/search_power_activity.ok
index 4491e2ee..a4a391b7 100644
--- a/search/test/search_power_activity.ok
+++ b/search/test/search_power_activity.ok
@@ -79,7 +79,6 @@ Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
 ----------------------------------------------------------------
 Total                  1.94e-06   3.76e-07   4.04e-07   2.72e-06 100.0%
                           71.3%      13.8%      14.9%
---- isClock queries ---
 --- report with timing derate after power ---
 Group                  Internal  Switching    Leakage      Total
                           Power      Power      Power      Power (Watts)
diff --git a/search/test/search_power_activity.tcl b/search/test/search_power_activity.tcl
index bd1e3c25..af521a36 100644
--- a/search/test/search_power_activity.tcl
+++ b/search/test/search_power_activity.tcl
@@ -27,21 +27,6 @@ puts "--- report_power -digits 6 ---"
 report_power -digits 6
 
 puts "--- Pin activity ---"
-# catch: sta::pin_activity is not exposed as Tcl command
-catch {
-  set act1 [sta::pin_activity [get_pins and1/ZN]]
-  puts "and1/ZN activity: $act1"
-}
-# catch: sta::pin_activity is not exposed as Tcl command
-catch {
-  set act2 [sta::pin_activity [get_pins reg1/Q]]
-  puts "reg1/Q activity: $act2"
-}
-# catch: sta::pin_activity is not exposed as Tcl command
-catch {
-  set act3 [sta::pin_activity [get_pins buf1/Z]]
-  puts "buf1/Z activity: $act3"
-}
 
 puts "--- set_power_activity on pins ---"
 set_power_activity -input_ports [get_ports in1] -activity 0.5 -duty 0.5
@@ -61,15 +46,6 @@ puts "--- report_power with clock propagation ---"
 set_propagated_clock [get_clocks clk]
 report_power
 
-puts "--- isClock queries ---"
-# catch: ckbuf instance may not exist in this design
-catch {
-  puts "ckbuf/A is_clock: [sta::is_clock_pin [get_pins ckbuf/A]]"
-  puts "ckbuf/Z is_clock: [sta::is_clock_pin [get_pins ckbuf/Z]]"
-  puts "reg1/CK is_clock: [sta::is_clock_pin [get_pins reg1/CK]]"
-  puts "and1/ZN is_clock: [sta::is_clock_pin [get_pins and1/ZN]]"
-}
-
 puts "--- report with timing derate after power ---"
 set_timing_derate -early 0.95
 set_timing_derate -late 1.05
diff --git a/search/test/search_property_extra.tcl b/search/test/search_property_extra.tcl
index 7b8feabe..bca1f159 100644
--- a/search/test/search_property_extra.tcl
+++ b/search/test/search_property_extra.tcl
@@ -46,13 +46,7 @@ set lport [get_lib_pins NangateOpenCellLibrary/AND2_X1/ZN]
 puts "lport name: [get_property $lport name]"
 puts "lport full_name: [get_property $lport full_name]"
 puts "lport direction: [get_property $lport direction]"
-# catch: 'function' is not a get_property property (use $port function method instead)
-catch { puts "lport function: [get_property $lport function]" }
 puts "lport capacitance: [get_property $lport capacitance]"
-# catch: 'max_capacitance' is not a supported get_property property
-catch { puts "lport max_capacitance: [get_property $lport max_capacitance]" }
-# catch: 'max_transition' is not a supported get_property property
-catch { puts "lport max_transition: [get_property $lport max_transition]" }
 puts "lport is_register_clock: [get_property $lport is_register_clock]"
 puts "lport is_clock: [get_property $lport is_clock]"
 
@@ -64,8 +58,6 @@ puts "and is_buffer: [get_property $and_cell is_buffer]"
 set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
 puts "dff is_buffer: [get_property $dff_cell is_buffer]"
 puts "dff area: [get_property $dff_cell area]"
-# catch: 'cell_leakage_power' is not a supported get_property property
-catch { puts "dff cell_leakage_power: [get_property $dff_cell cell_leakage_power]" }
 
 puts "--- LibertyLibrary properties ---"
 set lib [get_libs NangateOpenCellLibrary]
diff --git a/search/test/search_property_libport_deep.tcl b/search/test/search_property_libport_deep.tcl
index fa86fc69..8e8d133d 100644
--- a/search/test/search_property_libport_deep.tcl
+++ b/search/test/search_property_libport_deep.tcl
@@ -129,12 +129,8 @@ puts "reg1 is_memory: [get_property $reg_inst is_memory]"
 puts "--- LibertyCell area and leakage ---"
 set dff_cell [get_lib_cells NangateOpenCellLibrary/DFF_X1]
 puts "DFF_X1 area: [get_property $dff_cell area]"
-# catch: 'cell_leakage_power' is not a supported get_property property
-catch { puts "DFF_X1 cell_leakage_power: [get_property $dff_cell cell_leakage_power]" }
 set buf_cell [get_lib_cells NangateOpenCellLibrary/BUF_X1]
 puts "BUF_X1 area: [get_property $buf_cell area]"
-# catch: 'cell_leakage_power' is not a supported get_property property
-catch { puts "BUF_X1 cell_leakage_power: [get_property $buf_cell cell_leakage_power]" }
 set inv_cell [get_lib_cells NangateOpenCellLibrary/INV_X1]
 puts "INV_X1 area: [get_property $inv_cell area]"
 set and_cell [get_lib_cells NangateOpenCellLibrary/AND2_X1]
@@ -156,24 +152,10 @@ report_checks -path_delay max
 puts "--- find_timing_paths with group_path ---"
 set paths [find_timing_paths -path_delay max -group_path_count 20 -endpoint_path_count 10]
 puts "Found [llength $paths] paths with groups"
-foreach pe $paths {
-  # catch: PathEnd does not have a path_group method
-  catch {
-    set pg [$pe path_group]
-    puts "  [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
-  }
-}
 
 puts "--- find_timing_paths with min paths and groups ---"
 set paths_min [find_timing_paths -path_delay min -group_path_count 20 -endpoint_path_count 10]
 puts "Found [llength $paths_min] min paths with groups"
-foreach pe $paths_min {
-  # catch: PathEnd does not have a path_group method
-  catch {
-    set pg [$pe path_group]
-    puts "  [get_full_name [$pe pin]] group=[$pg name] slack=[$pe slack]"
-  }
-}
 
 ############################################################
 # path_group_names and is_path_group_name
diff --git a/search/test/search_pvt_analysis.ok b/search/test/search_pvt_analysis.ok
index df9869ba..e1a22db2 100644
--- a/search/test/search_pvt_analysis.ok
+++ b/search/test/search_pvt_analysis.ok
@@ -931,7 +931,6 @@ Path Type: max
            1.88   slack (MET)
 
 
---- set_min_pulse_width on pins ---
 --- report_pulse_width_checks -verbose ---
 Pin: reg3/CK
 Check: sequential_clock_pulse_width
diff --git a/search/test/search_pvt_analysis.tcl b/search/test/search_pvt_analysis.tcl
index eece9a8d..4e209e0b 100644
--- a/search/test/search_pvt_analysis.tcl
+++ b/search/test/search_pvt_analysis.tcl
@@ -139,16 +139,6 @@ puts "--- set_driving_cell ---"
 set_driving_cell -lib_cell BUF_X2 -pin Z [get_ports in1]
 report_checks -path_delay max
 
-############################################################
-# Min pulse width on pins/instances
-############################################################
-puts "--- set_min_pulse_width on pins ---"
-# catch: set_min_pulse_width does not accept port objects
-catch {
-  set_min_pulse_width 0.5 [get_ports clk1]
-  report_pulse_width_checks
-}
-
 puts "--- report_pulse_width_checks -verbose ---"
 report_pulse_width_checks -verbose
 
diff --git a/search/test/search_report_path_detail.ok b/search/test/search_report_path_detail.ok
index 28d910a4..34f2551b 100644
--- a/search/test/search_report_path_detail.ok
+++ b/search/test/search_report_path_detail.ok
@@ -207,7 +207,6 @@ Endpoints: 3
 Endpoint count: 3
 --- Path group names ---
 Path group names: clk out_group reg_group asynchronous {path delay} {gated clock} unconstrained
---- Endpoint slack ---
 --- find_requireds ---
 --- report internal debug ---
 Group    0 hash = 17966705655932391860 ( 134)
diff --git a/search/test/search_report_path_detail.tcl b/search/test/search_report_path_detail.tcl
index 518aa937..4246c133 100644
--- a/search/test/search_report_path_detail.tcl
+++ b/search/test/search_report_path_detail.tcl
@@ -139,14 +139,6 @@ puts "--- Path group names ---"
 set group_names [sta::path_group_names]
 puts "Path group names: $group_names"
 
-puts "--- Endpoint slack ---"
-set pin [get_pins reg1/D]
-# catch: sta::endpoint_slack may fail if path group "reg_to_reg" does not exist
-catch {
-  set eslack [sta::endpoint_slack $pin "reg_to_reg" max]
-  puts "Endpoint slack: $eslack"
-}
-
 puts "--- find_requireds ---"
 sta::find_requireds
 
diff --git a/search/test/search_sim_const_prop.ok b/search/test/search_sim_const_prop.ok
index 43439898..8ecdbc64 100644
--- a/search/test/search_sim_const_prop.ok
+++ b/search/test/search_sim_const_prop.ok
@@ -1055,8 +1055,6 @@ Path Type: max
            7.88   slack (MET)
 
 
---- set_min_pulse_width ---
---- report_pulse_width_checks after setting ---
                                      Required  Actual
 Pin                                    Width   Width   Slack
 ------------------------------------------------------------
diff --git a/search/test/search_sim_const_prop.tcl b/search/test/search_sim_const_prop.tcl
index 7e3e8105..1e543a35 100644
--- a/search/test/search_sim_const_prop.tcl
+++ b/search/test/search_sim_const_prop.tcl
@@ -189,13 +189,6 @@ report_checks -path_delay max
 ############################################################
 # Min pulse width
 ############################################################
-puts "--- set_min_pulse_width ---"
-# catch: set_min_pulse_width does not accept [all_inputs] as argument
-catch {
-  set_min_pulse_width 0.5 [all_inputs]
-}
-
-puts "--- report_pulse_width_checks after setting ---"
 report_pulse_width_checks
 
 ############################################################
diff --git a/search/test/search_sim_logic_clk_network.ok b/search/test/search_sim_logic_clk_network.ok
index 29a9d4c3..0c44ca85 100644
--- a/search/test/search_sim_logic_clk_network.ok
+++ b/search/test/search_sim_logic_clk_network.ok
@@ -233,11 +233,7 @@ Path Type: max
            7.90   slack (MET)
 
 
---- findLogicConstants ---
---- clearLogicConstants ---
 --- levelize ---
---- graphLoops ---
---- max_path_count_vertex ---
 --- generated clock ---
 Startpoint: reg1/Q (clock source 'gclk')
 Endpoint: out1 (output port clocked by clk)
diff --git a/search/test/search_sim_logic_clk_network.tcl b/search/test/search_sim_logic_clk_network.tcl
index 495b3770..5afcb8c0 100644
--- a/search/test/search_sim_logic_clk_network.tcl
+++ b/search/test/search_sim_logic_clk_network.tcl
@@ -100,38 +100,12 @@ report_checks -path_delay max
 ############################################################
 # findLogicConstants / clearLogicConstants
 ############################################################
-puts "--- findLogicConstants ---"
-# catch: sta::find_logic_constants is not exposed as Tcl command
-catch { sta::find_logic_constants }
-
-puts "--- clearLogicConstants ---"
-# catch: sta::clear_logic_constants is not exposed as Tcl command
-catch { sta::clear_logic_constants }
-
 ############################################################
 # Levelize and graph queries
 ############################################################
 puts "--- levelize ---"
 sta::levelize
 
-puts "--- graphLoops ---"
-# catch: sta::graph_loop_count is not exposed as Tcl command
-catch {
-  set loops [sta::graph_loop_count]
-  puts "Graph loops: $loops"
-}
-
-puts "--- max_path_count_vertex ---"
-# catch: sta::max_path_count_vertex is not exposed as Tcl command
-catch {
-  set maxv [sta::max_path_count_vertex]
-  if { $maxv != "NULL" } {
-    puts "max_path_count vertex: [get_full_name [$maxv pin]]"
-    puts "  path_count: [sta::vertex_path_count $maxv]"
-    puts "  level: [sta::vertex_level $maxv]"
-  }
-}
-
 ############################################################
 # Generated clock (exercises Genclks.cc)
 ############################################################
diff --git a/search/test/search_worst_slack_sta.tcl b/search/test/search_worst_slack_sta.tcl
index 47c4e4d6..64eb4f62 100644
--- a/search/test/search_worst_slack_sta.tcl
+++ b/search/test/search_worst_slack_sta.tcl
@@ -157,11 +157,6 @@ report_checks -path_delay max > /dev/null
 sta::set_report_path_no_split 0
 
 puts "--- graph loops ---"
-# catch: sta::graph_loop_count is not exposed as Tcl command
-catch {
-  set loops [sta::graph_loop_count]
-  puts "graph_loop_count: $loops"
-}
 
 puts "--- pocv ---"
 puts "pocv_enabled: [sta::pocv_enabled]"