From 1731dd0c38dafadd50f3fd3908b9e9ec17557fe3 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 3 Sep 2025 16:08:06 -0700 Subject: [PATCH 1/3] group_path -default doc resolves #292 Signed-off-by: James Cherry --- doc/OpenSTA.fodt | 3078 +++++++++++++++++++++++----------------------- doc/OpenSTA.pdf | Bin 1427456 -> 1429579 bytes 2 files changed, 1550 insertions(+), 1528 deletions(-) diff --git a/doc/OpenSTA.fodt b/doc/OpenSTA.fodt index b62d4b94..cd7ae9d9 100644 --- a/doc/OpenSTA.fodt +++ b/doc/OpenSTA.fodt @@ -1,10 +1,10 @@ - Parallax STA documentationJames Cherry4812025-03-17T12:59:52.4638705382010-07-31T21:07:002025-08-12T12:31:42.963746000P117DT14H34M45SLibreOffice/25.2.2.2$MacOSX_AARCH64 LibreOffice_project/7370d4be9e3cf6031a51beef54ff3bda878e3facPDF files: James CherryJames Cherry12.00000falsefalsefalsefalse + Parallax STA documentationJames Cherry4822025-03-17T12:59:52.4638705382010-07-31T21:07:002025-09-03T16:07:18.577431000P117DT14H37M47SLibreOffice/25.2.2.2$MacOSX_AARCH64 LibreOffice_project/7370d4be9e3cf6031a51beef54ff3bda878e3facPDF files: James CherryJames Cherry12.00000falsefalsefalsefalse - 999943 + 700804 0 30224 17736 @@ -13,12 +13,12 @@ view2 - 12256 - 1005261 + 19479 + 714065 0 - 999943 + 700804 30222 - 1017677 + 718538 0 1 false @@ -87,7 +87,7 @@ false true false - 25694037 + 25749756 0 false @@ -194,7 +194,7 @@ - + @@ -4368,779 +4368,786 @@ - + - - - + + - - + + - + + - - + + - - - + + - + - + - - + + + - + - - + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - + - + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - + - - + + + - + - - - + + - + + - + - - + - + - + - + + + + + + + + + - + - + - - - - - - - - - + - - + + + - + - - - + + - - + + - - + + + - + - - - + + - - + + + - + - - + + - + - - - + + - + - + - - + + + + + + + + + + - + - + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + - - - - - - - + + - + - + - - + + - - + + - + - + + - + + + + + + + + - - - - - - - - - + - - + + - + - + - + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - + - - + - - - + + + - + - + - + - - + + + - + - - + + - + - - - + + - + + + + + + + + + - + - + - + - - - - - - - - - + - + - + + + + + + + + + - + - + - + - + - - - - - - - + + + + + + + - + - + - - - - - - - - + - - + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - + - + - + - + - - - - - - - - - + - + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -5426,756 +5433,762 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + + @@ -6310,24 +6323,24 @@ Variables80 - Command Line Arguments + Command Line Arguments The command line arguments for sta are shown below. sta -help show help and exit -version show version and exit -no_init do not read ~/.sta -no_splash do not print the splash message -threads count|max use count threads -exit exit after reading cmd_file cmd_file source cmd_file When OpenSTA starts up, commands are first read from the user initialization file ~/.sta if it exists. If a TCL command file cmd_file is specified on the command line, commands are read from the file and executed before entering an interactive TCL command interpreter. If -exit is specified the application exits after reading cmd_file. Use the TCL exit command to exit the application. The –threads option specifies how many parallel threads to use. Use –threads max to use one thread per processor. - Example Command Scripts + Example Command Scripts To read a design into OpenSTA use the read_liberty command to read Liberty library files. Next, read hierarchical structural Verilog files with the read_verilog command. The link_design command links the Verilog to the Liberty timing cells. Any number of Liberty and Verilog files can be read before linking the design. Delays used for timing analysis are calculated using the Liberty timing models. If no parasitics are read only the pin capacitances of the timing models are used in delay calculation. Use the read_spef command to read parasitics from an extractor, or read_sdf to use delays calculated by an external delay calculator. Timing constraints can be entered as TCL commands or read using the read_sdc command. The units used by OpenSTA for all command arguments and reports are taken from the first Liberty file that is read. Use the set_cmd_units command to override the default units. - Timing Analysis using SDF + Timing Analysis using SDF A sample command file that reads a library and a Verilog netlist and reports timing checks is shown below. read_liberty example1_slow.libread_verilog example1.vlink_design topread_sdf example1.sdfcreate_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks This example can be found in examples/sdf_delays.tcl. - Timing Analysis with Multiple Process Corners + Timing Analysis with Multiple Process Corners An example command script using three process corners and +/-10% min/max derating is shown below. define_corners wc typ bcread_liberty -corner wc example1_slow.libread_liberty -corner typ example1_typ.libread_liberty -corner bc example1_fast.libread_verilog example1.vlink_design topset_timing_derate -early 0.9set_timing_derate -late 1.1create_clock -name clk -period 10 {clk1 clk2 clk3}set_input_delay -clock clk 0 {in1 in2}report_checks -path_delay min_maxreport_checks -corner typ This example can be found in examples/spef_parasitics.tcl. Other examples can be found in the examples directory. - Power Analysis + Power Analysis OpenSTA also supports static power analysis with the report_power command. Probabalistic switching activities are propagated from the input ports to determine switching activities for internal pins. read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefset_power_activity -input -activity 0.1set_power_activity -input_port reset -activity 0report_power In this example the activity for all inputs is set to 0.1, and then the activity for the reset signal is set to zero because it does not switch during steady state operation. @@ -6339,14 +6352,14 @@ read_liberty sky130hd_tt.libread_verilog gcd_sky130hd.vlink_design gcdread_sdc gcd_sky130hd.sdcread_spef gcd_sky130hd.spefread_vcd -scope gcd_tb/gcd1 gcd_sky130hd.vcd.gzreport_power This example can be found in examples/power_vcd.tcl. Note that in this simple example design simulation based activities does not significantly change the results. - TCL Interpreter + TCL Interpreter Keyword arguments to commands may be abbreviated. For example, report_checks -unique is equivalent to the following command. report_checks -unique_paths_to_endpoint The help command lists matching commands and their arguments. > help report*report_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange] [-width] [-period] [-max_skew] [-max_lines liness] [-list_annotated]group_path_count [-list_not_annotated] [-constant_arcs]report_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports] [-max_lines liness] [-list_annotated] [-list_not_annotated] [-constant_arcs]report_arrival pinreport_check_types [-violators] [-verbose] [-corner corner] [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal] [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew] [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits [-no_line_splits] [> filename] [>> filename]report_checks [-from from_list|-rise_from from_list|-fall_from from_list] [-through through_list|-rise_through through_list|-fall_through through_list] [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained] [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max] [-corner corner] [-group_path_count path_count] [-endpoint_path_count path_count] [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack] [-path_group group_name] [-format full|full_clock|full_clock_expanded|short|end|summary]... - Many reporting commands support redirection of the output to a file much like a Unix shell. + Many reporting commands support redirection of the output to a file much like a Unix shell. report_checks -to out1 > path.logreport_checks -to out2 >> path.log Debugging Timing Here are some guidelines for debugging your design if static timing does not report any paths, or does not report the expected paths. @@ -6372,13 +6385,13 @@ Next, check the arrival times at the D and CP pins of the register with report_arrivals. % report_arrivals r1/D (clk1 ^) r 1.00:1.00 f 1.00:1.00% report_arrivals r1/CP (clk1 ^) r 0.00:0.00 f INF:-INF (clk1 v) r INF:-INF f 5.00:5.00 If there are no arrivals on an input port of the design, use the set_input_delay command to specify the arrival times on the port. - Commands + Commands - all_clocks + all_clocks @@ -6391,7 +6404,7 @@ - all_inputs + all_inputs [-no_clocks] @@ -6412,7 +6425,7 @@ - all_outputs + all_outputs @@ -6425,7 +6438,7 @@ - all_registers + all_registers [-clock clock_names][-cells | -data_pins | -clock_pins | -async_pins | ‑output_pins][-level_sensitive][-edge_triggered] @@ -6502,7 +6515,7 @@ - check_setup + check_setup [-verbose][-unconstrained_endpoints][-multiple_clock][-no_clock][-no_input_delay][-loops][-generated_clocks][> filename][>> filename] @@ -6571,7 +6584,7 @@ - connect_pin + connect_pin netport|pin @@ -6671,7 +6684,7 @@ - create_generated_clock + create_generated_clock [-name clock_name]-source master_pin[-master_clock master_clock][-divide_by divisor][-multiply_by multiplier][-duty_cycle duty_cycle][-invert][-edges edge_list][-edge_shift shift_list][-add]pin_list @@ -6787,7 +6800,7 @@ - create_voltage_area + create_voltage_area [-name name][-coordinate coordinates][-guard_band_x guard_x][-guard_band_y guard_y]cells @@ -6800,7 +6813,7 @@ - current_design + current_design [design] @@ -6813,7 +6826,7 @@ - current_instance + current_instance [instance] @@ -6835,7 +6848,7 @@ - define_corners + define_corners corner1 [corner2]... @@ -6857,7 +6870,7 @@ - delete_clock + delete_clock [-all] clocks @@ -6878,7 +6891,7 @@ - delete_from_list + delete_from_list list objects @@ -6907,7 +6920,7 @@ - delete_generated_clock + delete_generated_clock [-all] clocks @@ -6928,7 +6941,7 @@ - delete_instance + delete_instance instance @@ -6950,7 +6963,7 @@ - delete_net + delete_net net @@ -6971,7 +6984,7 @@ - disconnect_pin + disconnect_pin netport | pin | -all @@ -7016,7 +7029,7 @@ - elapsed_run_time + elapsed_run_time @@ -7030,7 +7043,7 @@ - find_timing_paths + find_timing_paths [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups] @@ -7244,7 +7257,7 @@ - get_cells + get_cells [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7322,7 +7335,7 @@ - get_clocks + get_clocks [-regexp][-nocase][-filter expr][-quiet]patterns @@ -7376,7 +7389,7 @@ - get_fanin + get_fanin -to sink_list[-flat][-only_cells][-startpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7461,7 +7474,7 @@ - get_fanout + get_fanout -from source_list[-flat][-only_cells][-endpoints_only][-levels level_count][-pin_levels pin_count][-trace_arcs timing|enabled|all] @@ -7547,7 +7560,7 @@ - get_full_name + get_full_name object @@ -7638,7 +7651,7 @@ - get_lib_pins + get_lib_pins [-of_objects objects][-hsc separator][-filter expr][-regexp][-nocase][-quiet]patterns @@ -7707,7 +7720,7 @@ - get_libs + get_libs [-filter expr][-regexp][-nocase][-quiet]patterns @@ -7761,7 +7774,7 @@ - get_nets + get_nets [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7838,7 +7851,7 @@ - get_name + get_name object @@ -7859,7 +7872,7 @@ - get_pins + get_pins [-hierarchical][-hsc separator][-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7931,7 +7944,7 @@ - get_ports + get_ports [-filter expr][-regexp][-nocase][-quiet][-of_objects objects][patterns] @@ -7992,7 +8005,7 @@ - get_property + get_property [-object_type object_type]objectproperty @@ -8053,7 +8066,7 @@ - get_timing_edges + get_timing_edges [-from from_pins][-to to_pins][-of_objects objects][-filter expr][patterns] @@ -8098,10 +8111,10 @@ - group_path + group_path - -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list] + -name group_name[-weight weight][-critical_range range][-from from_list |-rise_from from_list |-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-default] @@ -8157,7 +8170,7 @@ -through through_list - Group paths through a list of instances, pins or nets. + Group paths through a list of instances, pins or nets. @@ -8165,7 +8178,7 @@ -rise_through through_list - Group rising paths through a list of instances, pins or nets. + Group rising paths through a list of instances, pins or nets. @@ -8173,7 +8186,7 @@ -fall_through through_list - Group falling paths through a list of instances, pins or nets. + Group falling paths through a list of instances, pins or nets. @@ -8181,7 +8194,7 @@ -to to_list - Group paths to a list of clocks, instances, ports or pins. + Group paths to a list of clocks, instances, ports or pins. @@ -8189,7 +8202,7 @@ -rise_to to_list - Group rising paths to a list of clocks, instances, ports or pins. + Group rising paths to a list of clocks, instances, ports or pins. @@ -8197,7 +8210,16 @@ -fall_to to_list - Group falling paths to a list of clocks, instances, ports or pins. + Group falling paths to a list of clocks, instances, port-s or pins. + + + + + + -default + + + Restore the paths in the path group -from/-to/-through/-to to their default path group. @@ -8205,95 +8227,95 @@ - - include + include - [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] + [-echo|-e][-verbose|-v]filename[> log_filename][>> log_filename] - -echo|-e + -echo|-e - Print each command before evaluating it. + Print each command before evaluating it. - -verbose|-v + -verbose|-v - Print each command before evaluating it as well as the result it returns. + Print each command before evaluating it as well as the result it returns. - filename + filename - The name of the file containing commands to read. + The name of the file containing commands to read. - > log_filename + > log_filename - Redirect command output to log_filename. + Redirect command output to log_filename. - >> log_filename + >> log_filename - Redirect command output and append log_filename. + Redirect command output and append log_filename. - Read STA/SDC/Tcl commands from filename. - The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. + Read STA/SDC/Tcl commands from filename. + The include command stops and reports any errors encountered while reading a file unless sta_continue_on_error is 1. - link_design + link_design - [-no_black_boxes][cell_name] + [-no_black_boxes][cell_name] - -no_black_boxes + -no_black_boxes - Do not make empty “black box” cells for instances that reference undefined cells. + Do not make empty “black box” cells for instances that reference undefined cells. - cell_name + cell_name - The top level module/cell name of the design hierarchy to link. + The top level module/cell name of the design hierarchy to link. - Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. + Link (elaborate, flatten) the the top level cell cell_name. The design must be linked after reading netlist and library files. The default value of cell_name is the current design. The linker creates empty "block box" cells for instances the reference undefined cells when the variable link_create_black_boxes is true. When link_create_black_boxes is false an error is reported and the link fails. The link_design command returns 1 if the link succeeds and 0 if it fails. + - make_instance + make_instance inst_pathlib_cell @@ -8316,13 +8338,13 @@ - The make_instance command makes an instance of library cell lib_cell. + The make_instance command makes an instance of library cell lib_cell. - make_net + make_net net_name_list @@ -8343,18 +8365,18 @@ - read_liberty + read_liberty - [-corner corner][-min][-max][-infer_latches]filename + [-corner corner][-min][-max][-infer_latches]filename - -corner corner + -corner corner - Use the library for process corner corner delay calculation. + Use the library for process corner corner delay calculation. @@ -8378,13 +8400,13 @@ filename - The liberty file name to read. + The liberty file name to read. The read_liberty command reads a Liberty format library file. The first library that is read sets the units used by SDC/TCL commands and reporting. The include_file attribute is supported. - Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: - cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} + Some Liberty libraries do not include latch groups for cells that are describe transparent latches. In that situation the -infer_latches command flag can be used to infer the latches. The timing arcs required for a latch to be inferred should look like the following: + cell (infered_latch) { pin(D) { direction : input ; timing () { related_pin : "E" ; timing_type : setup_falling ; } timing () { related_pin : "E" ; timing_type : hold_falling ; } } pin(E) { direction : input; } pin(Q) { direction : output ; timing () { related_pin : "D" ; } timing () { related_pin : "E" ; timing_type : rising_edge ; } }} In this example a positive level-sensitive latch is inferred. Files compressed with gzip are automatically uncompressed. @@ -8392,36 +8414,36 @@ - read_saif + read_saif - [-scope scope]filename + [-scope scope]filename - scope + scope - The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The SAIF scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - filename + filename - The name of the SAIF file to read. + The name of the SAIF file to read. - The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_saif command reads a SAIF (Switching Activity Interchange Format) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_sdc + read_sdc [-echo]filename @@ -8450,9 +8472,10 @@ + - read_sdf + read_sdf [-corner corner][-unescaped_dividers]filename @@ -8460,13 +8483,12 @@ - -corner corner + -corner corner Process corner delays to annotate. - -unescaped_dividers @@ -8484,7 +8506,7 @@ - Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple corners are defined -corner must be specified. + Read SDF delays from a file. The min and max values in the SDF tuples are used to annotate the delays for corner. The typical values in the SDF tuples are ignored. If multiple corners are defined -corner must be specified. Files compressed with gzip are automatically uncompressed. INCREMENT is supported as an alias for INCREMENTAL. The following SDF statements are not supported. @@ -8494,26 +8516,26 @@ - read_spef + read_spef - [-min][-max][-path path][-corner corner][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce]filename + [-min][-max][-path path][-corner corner][-keep_capacitive_coupling][-coupling_reduction_factor factor][-reduce]filename - -min + -min - Annotate parasitics for min delays. + Annotate parasitics for min delays. - -max + -max - Annotate parasitics for max delays. + Annotate parasitics for max delays. @@ -8521,20 +8543,21 @@ path - Hierarchical block instance path to annotate with parasitics. + Hierarchical block instance path to annotate with parasitics. - -corner corner + -corner corner - Annotate parasitics for one process corner. + Annotate parasitics for one process corner. + - ‑keep_capacitive_coupling + ‑keep_capacitive_coupling Keep coupling capacitors in parasitic networks rather than converting them to grounded capacitors. @@ -8542,21 +8565,20 @@ - ‑coupling_reduction_factorfactor + ‑coupling_reduction_factorfactor - Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. + Factor to multiply coupling capacitance by when reducing parasitic networks. The default value is 1.0. - -reduce + -reduce - Reduce detailed parasitics and do not save the detailed parastic network. + Reduce detailed parasitics and do not save the detailed parastic network. - filename @@ -8566,58 +8588,57 @@ - The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. + The read_spef command reads a file of net parasitics in SPEF format. Use the ‑report_parasitic_annotation command to check for nets that are not annotated. Files compressed with gzip are automatically uncompressed. - Separate parasitics can be annotated for corners and min and max paths using the -corner, –min and -max arguments. To use the same parastiics for every corner and for min/max delay calculation read the SPEF without -corner, -min, and -max options. - read_spef spef1 - To use separate parastics for min/max delay, use the -min, and -max options for each SPEF file. - read_spef -min spef1read_spef -max spef2 - To use separate parastics for each corner, use the -corner option for each SPEF file. - read_spef -corner ss spef1read_spef -corner tt spef2read_spef -corner ff spef3 - To use separate parastics for each corner and separate min/max delay calculation, use the -corner option along with the -min, and -max options. - read_spef -corner ss -min spef1read_spef -corner ss -max spef2read_spef -corner ff -min spef3read_spef -corner ff -max spef4 - With the -reduce option, the current delay calculator reduces the parastic network to the appropriate type and deletes the parasitic network. This substantially reduces the memory required to store the parasitics. + Separate parasitics can be annotated for corners and min and max paths using the -corner, –min and -max arguments. To use the same parastiics for every corner and for min/max delay calculation read the SPEF without -corner, -min, and -max options. + read_spef spef1 + To use separate parastics for min/max delay, use the -min, and -max options for each SPEF file. + read_spef -min spef1read_spef -max spef2 + To use separate parastics for each corner, use the -corner option for each SPEF file. + read_spef -corner ss spef1read_spef -corner tt spef2read_spef -corner ff spef3 + To use separate parastics for each corner and separate min/max delay calculation, use the -corner option along with the -min, and -max options. + read_spef -corner ss -min spef1read_spef -corner ss -max spef2read_spef -corner ff -min spef3read_spef -corner ff -max spef4 + With the -reduce option, the current delay calculator reduces the parastic network to the appropriate type and deletes the parasitic network. This substantially reduces the memory required to store the parasitics. Coupling capacitors are multiplied by the –coupling_reduction_factor when a parasitic network is reduced. The following SPEF constructs are ignored. - *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues - If the SPEF file contains triplet values the first value is used. - Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. + *DESIGN_FLOW (all values are ignored)*S slews*D driving cell*I pin capacitances (library cell capacitances are used instead)*Q r_net load poles*K r_net load residues + If the SPEF file contains triplet values the first value is used. + Parasitic networks (DSPEF) can be annotated on hierarchical blocks using the -path argument to specify the instance path to the block. Parasitic networks in the higher level netlist are stitched together at the hierarchical pins of the blocks. - - read_vcd + read_vcd - [-scope scope]filename + [-scope scope]filename - scope + scope - The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. + The VCD scope of the current design to extract simulation data. Typically the test bench name and design under test instance name. Scope levels are separated with ‘/’. - filename + filename - The name of the VCD file to read. + The name of the VCD file to read. - The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. + The read_vcd command reads a VCD (Value Change Dump) file from a Verilog simulation and extracts pin activities and duty cycles for use in power estimation. Files compressed with gzip are supported. Annotated activities are propagated to the fanout of the annotated pins. - read_verilog + read_verilog filename @@ -8632,8 +8653,8 @@ - The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. - Verilog 2001 module port declaratations are supported. An example is shown below. + The read_verilog command reads a gate level verilog netlist. After all verilog netlist and Liberty libraries are read the design must be linked with the link_design command. + Verilog 2001 module port declaratations are supported. An example is shown below. module top (input in1, in2, clk1, clk2, clk3, output out); Files compressed with gzip are automatically uncompressed. @@ -8641,7 +8662,7 @@ - replace_cell + replace_cell instance_listreplacement_cell @@ -8664,45 +8685,46 @@ - The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + The replace_cell command changes the cell of an instance. The replacement cell must have the same port list (number, name, and order) as the instance's existing cell for the replacement to be successful. + - replace_activity_annotation + replace_activity_annotation - [-report_unannotated][-report_annotated] + [-report_unannotated][-report_annotated] - -report_unannotated + -report_unannotated - Report unannotated pins. + Report unannotated pins. - -report_unannotated + -report_unannotated - Report annotated pins. + Report annotated pins. - Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. + Report a summary of pins that are annotated by read_vcd, read_saif or set_power_activity. Sequential internal pins and hierarchical pins are ignored. - report_annotated_check + report_annotated_check - [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] + [-setup][-hold][-recovery][-removal][-nochange][-width][-period][-max_skew][-max_line lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -8771,28 +8793,29 @@ - -max_line lines + -max_line lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. + -constant_arcs @@ -8802,17 +8825,16 @@ - The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_check command reports a summary of SDF timing check annotation. The -report_annotated and –report_annotated options can be used to list arcs that are annotated or not annotated. - - report_annotated_delay + report_annotated_delay - [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] + [-cell][-net][-from_in_ports][-to_out_ports][-max_lines lines][-report_annotated][-report_unannotated][-constant_arcs] @@ -8833,7 +8855,7 @@ - -from_in_ports + -from_in_ports Report annotated delays from input ports. @@ -8841,7 +8863,7 @@ - -to_out_ports + -to_out_ports Report annotated delays to output ports. @@ -8849,26 +8871,26 @@ - -max_lines lines + -max_lines lines - Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. + Maximum number of lines listed by the –report_annotated and ‑report_unannotated options. - -report_annotated + -report_annotated - Report annotated timing arcs. + Report annotated timing arcs. - -report_unannotated + -report_unannotated - Report unannotated timing arcs. + Report unannotated timing arcs. @@ -8880,310 +8902,310 @@ - The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. + The report_annotated_delay command reports a summary of SDF delay annotation. Without the ‑from_in_ports and –to_out_ports options arcs to and from top level ports are not reported. The ‑report_annotated and –report_unannotated options can be used to list arcs that are annotated or not annotated. - report_checks + report_checks - [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] + [-from from_list |-rise_from from_list |-fall_from from_list][-through through_list |-rise_through through_list |-fall_through through_list][-to to_list |-rise_to to_list |-fall_to to_list][-unconstrained][-path_delay min|min_rise|min_fall |max|max_rise|max_fall |min_max][-group_path_count path_count][-endpoint_path_count endpoint_path_count][-unique_paths_to_endpoint][-corner corner][-slack_max max_slack][-slack_min min_slack][-sort_by_slack][-path_group groups][-format end|full|short|summary |full_clock|full_clock_expanded |json][-fields fields][-digits digits][-no_line_split][> filename][>> filename] - -from from_list + -from from_list - Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from a list of clocks, instances, ports, register clock pins, or latch data pins. - -rise_from from_list + -rise_from from_list - Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the rising edge of clocks, instances, ports, register clock pins, or latch data pins. - -fall_from from_list + -fall_from from_list - Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. + Report paths from the falling edge of clocks, instances, ports, register clock pins, or latch data pins. - -through through_list + -through through_list - Report paths through a list of instances, pins or nets. + Report paths through a list of instances, pins or nets. - -rise_through through_list + -rise_through through_list - Report rising paths through a list of instances, pins or nets. + Report rising paths through a list of instances, pins or nets. - -fall_through through_list + -fall_through through_list - Report falling paths through a list of instances, pins or nets. + Report falling paths through a list of instances, pins or nets. - -to to_list + -to to_list - Report paths to a list of clocks, instances, ports or pins. + Report paths to a list of clocks, instances, ports or pins. - -rise_to to_list + -rise_to to_list - Report rising paths to a list of clocks, instances, ports or pins. + Report rising paths to a list of clocks, instances, ports or pins. - -fall_to to_list + -fall_to to_list - Report falling paths to a list of clocks, instances, ports or pins. + Report falling paths to a list of clocks, instances, ports or pins. - -unconstrained + -unconstrained - Report unconstrained paths also. The unconstrained path group is not reported without this option. + Report unconstrained paths also. The unconstrained path group is not reported without this option. - -path_delay min + -path_delay min - Report min path (hold) checks. + Report min path (hold) checks. - -path_delay min_rise + -path_delay min_rise - Report min path (hold) checks for rising endpoints. + Report min path (hold) checks for rising endpoints. - -path_delay min_fall + -path_delay min_fall - Report min path (hold) checks for falling endpoints. + Report min path (hold) checks for falling endpoints. - -path_delay max + -path_delay max - Report max path (setup) checks. + Report max path (setup) checks. - -path_delay max_rise + -path_delay max_rise - Report max path (setup) checks for rising endpoints. + Report max path (setup) checks for rising endpoints. - -path_delay max_fall + -path_delay max_fall - Report max path (setup) checks for falling endpoints. + Report max path (setup) checks for falling endpoints. - -path_delay min_max + -path_delay min_max - Report max and max path (setup and hold) checks. + Report max and max path (setup and hold) checks. - -group_path_count path_count + -group_path_count path_count - The number of paths to report in each path group. The default is 1. + The number of paths to report in each path group. The default is 1. - -endpoint_path_count endpoint_path_count + -endpoint_path_count endpoint_path_count - The number of paths to report for each endpoint. The default is 1. + The number of paths to report for each endpoint. The default is 1. - ‑unique_paths_to_endpoint + ‑unique_paths_to_endpoint - When multiple paths to an endpoint are specified with ‑endpoint_path_count many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pis is reported. + When multiple paths to an endpoint are specified with ‑endpoint_path_count many of the paths may differ only in the rise/fall edges of the pins in the paths. With this option only the worst path through the set of pis is reported. - -corner corner + -corner corner - Report paths for one process corner. The default is to report paths for all process corners. + Report paths for one process corner. The default is to report paths for all process corners. - -slack_max max_slack + -slack_max max_slack - Only report paths with less slack than max_slack. + Only report paths with less slack than max_slack. - -slack_min min_slack + -slack_min min_slack - Only report paths with more slack than min_slack. + Only report paths with more slack than min_slack. - -sort_by_slack + -sort_by_slack - Sort paths by slack rather than slack grouped by path group. + Sort paths by slack rather than slack grouped by path group. - -path_group groups + -path_group groups - List of path groups to report. The default is to report all path groups. + List of path groups to report. The default is to report all path groups. - -format end + -format end - Report path ends in one line with delay, required time and slack. + Report path ends in one line with delay, required time and slack. - -format full + -format full - Report path start and end points and the path. This is the default path type. + Report path start and end points and the path. This is the default path type. - -format full_clock + -format full_clock - Report path start and end points, the path, and the source and and target clock paths. + Report path start and end points, the path, and the source and and target clock paths. - -format full_clock_expanded + -format full_clock_expanded - Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. + Report path start and end points, the path, and the source and and target clock paths. If the clock is generated and propagated, the path from the clock source pin is also reported. - -format short + -format short - Report only path start and end points. + Report only path start and end points. - -format summary + -format summary - Report only path ends with delay. + Report only path ends with delay. - -format json + -format json - Report in json format. -fields is ignored. + Report in json format. -fields is ignored. - -fields fields + -fields fields - List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr + List of capacitance|slew|input_pins|hierarchical_pins|nets|fanout|src_attr - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - -no_line_splits + -no_line_splits - Do not split long lines into multiple lines. + Do not split long lines into multiple lines. - The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. - See set_false_path for a description of allowed from_list, through_list and to_list objects. + The report_checks command reports paths in the design. Paths are reported in groups by capture clock, unclocked path delays, gated clocks and unconstrained. + See set_false_path for a description of allowed from_list, through_list and to_list objects. - report_check_types + report_check_types [-violators][-verbose][-format slack_only|end][-max_delay][-min_delay][-recovery][-removal][-clock_gating_setup][-clock_gating_hold][-max_slew][-min_slew][-min_pulse_width][-min_period][-digits digits][-no_split_lines][> filename][>> filename] @@ -9192,7 +9214,7 @@ - -violators + -violators Report all violated timing and design rule constraints. @@ -9200,7 +9222,7 @@ - -verbose + -verbose Use a verbose output format. @@ -9208,18 +9230,18 @@ - -format slack_only + -format slack_only - Report the minimum slack for each timing check. + Report the minimum slack for each timing check. - -format end + -format end - Report the endpoint for each check. + Report the endpoint for each check. @@ -9312,10 +9334,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9323,7 +9345,7 @@ -no_split_lines - Do not split long lines into multiple lines. + Do not split long lines into multiple lines. @@ -9333,45 +9355,45 @@ - report_clock_latency + report_clock_latency - [-clock clocks][-include_internal_latency][-digits digits] + [-clock clocks][-include_internal_latency][-digits digits] - -clock clocks + -clock clocks - The clocks to report. + The clocks to report. - -include_internal_latency + -include_internal_latency - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. - -digits digits + -digits digits - The number of digits to report for delays. + The number of digits to report for delays. - Report the clock network latency. + Report the clock network latency. - report_clock_min_period + report_clock_min_period [-clocks clocks][-include_port_paths] @@ -9379,7 +9401,7 @@ - -clocks clocks + -clocks clocks The clocks to report. @@ -9394,13 +9416,13 @@ - Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. + Report the minimum period and maximum frequency for clocks. If the -clocks argument is not specified all clocks are reported. The minimum period is determined by examining the smallest slack paths between registers the rising edges of the clock or between falling edges of the clock. Paths between different clocks, different clock edges of the same clock, level sensitive latches, or paths constrained by set_multicycle_path, set_max_path are not considered. - report_clock_properties + report_clock_properties [clock_names] @@ -9421,10 +9443,10 @@ - report_clock_skew + report_clock_skew - [-setup|-hold][-clock clocks][-include_internal_latency][-digits digits] + [-setup|-hold][-clock clocks][-include_internal_latency][-digits digits] @@ -9445,7 +9467,7 @@ - -clock clocks + -clock clocks The clocks to report. @@ -9453,29 +9475,29 @@ - -include_internal_latency + -include_internal_latency - Include internal clock latency from liberty min/max_clock_tree_path timing groups. + Include internal clock latency from liberty min/max_clock_tree_path timing groups. - -digits digits + -digits digits The number of digits to report for delays. - Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. + Report the maximum difference in clock arrival between every source and target register that has a path between the source and target registers. - report_dcalc + report_dcalc [-from from_pin][-to to_pin][-corner corner][-min][-max][-digits digits][> filename][>> filename] @@ -9483,50 +9505,50 @@ - -from from_pin + -from from_pin - Report delay calculations for timing arcs from instance input pin from_pin. + Report delay calculations for timing arcs from instance input pin from_pin. - -to to_pin + -to to_pin - Report delay calculations for timing arcs to instance output pin to_pin. + Report delay calculations for timing arcs to instance output pin to_pin. - -corner corner + -corner corner - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report paths for process corner. The -corner keyword is required if more than one process corner is defined. - -min + -min - Report delay calculation for min delays. + Report delay calculation for min delays. - -max + -max - Report delay calculation for max delays. + Report delay calculation for max delays. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default is sta_report_default_digits. + The number of digits after the decimal point to report. The default is sta_report_default_digits. @@ -9536,7 +9558,7 @@ - report_disabled_edges + report_disabled_edges @@ -9544,42 +9566,42 @@ The report_disabled_edges command reports disabled timing arcs along with the reason they are disabled. Each disabled timing arc is reported as the instance name along with the from and to ports of the arc. The disable reason is shown next. Arcs that are disabled with set_disable_timing are reported with constraint as the reason. Arcs that are disabled by constants are reported with constant as the reason along with the constant instance pin and value. Arcs that are disabled to break combinational feedback loops are reported with loop as the reason. - > report_disabled_edgesu1 A B constant B=0 + > report_disabled_edgesu1 A B constant B=0 - report_edges + report_edges - [-from from_pin][-to to_pin] + [-from from_pin][-to to_pin] - -from from_pin + -from from_pin - Report edges/timing arcs from pin from_pin. + Report edges/timing arcs from pin from_pin. - -to to_pin + -to to_pin - Report edges/timing arcs to pin to_pin. + Report edges/timing arcs to pin to_pin. - Report the edges/timing arcs and their delays in the timing graph from/to/between pins. + Report the edges/timing arcs and their delays in the timing graph from/to/between pins. - report_instance + report_instance instance_path[> filename][>> filename] @@ -9600,7 +9622,7 @@ - report_lib_cell + report_lib_cell cell_name[> filename][>> filename] @@ -9621,7 +9643,7 @@ - report_net + report_net [-digits digits]net_path[> filename][>> filename] @@ -9629,10 +9651,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9644,74 +9666,74 @@ - Report the connections and capacitance of a net. + Report the connections and capacitance of a net. - report_parasitic_annotation + report_parasitic_annotation - [-report_unannotated][> filename][>> filename] + [-report_unannotated][> filename][>> filename] - -report_unannotated + -report_unannotated - Report unannotated and partially annotated nets. + Report unannotated and partially annotated nets. - Report SPEF parasitic annotation completeness. + Report SPEF parasitic annotation completeness. - report_power + report_power - [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] + [-instances instances][-highest_power_instances count][-digits digits][> filename][>> filename] - -instances instances + -instances instances - Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. + Report the power for each instance of instances. If the instance is hierarchical the total power for the instances inside the hierarchical instance is reported. - -highest_power_instances count + -highest_power_instances count - Report the power for the count highest power instances. + Report the power for the count highest power instances. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. - The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. + The report_power command uses static power analysis based on propagated or annotated pin activities in the circuit using Liberty power models. The internal, switching, leakage and total power are reported. Design power is reported separately for combinational, sequential, macro and pad groups. Power values are reported in watts. + The read_vcd or read_saif commands can be used to read activities from a file based on simulation. If no simulation activities are available, the set_power_activity command should be used to set the activity of input ports or pins in the design. The default input activity and duty for inputs are 0.1 and 0.5 respectively. The activities are propagated from annotated input ports or pins through gates and used in the power calculations. Group Internal Switching Leakage Total Power Power Power Power----------------------------------------------------------------Sequential 3.29e-06 3.41e-08 2.37e-07 3.56e-06 92.4%Combinational 1.86e-07 3.31e-08 7.51e-08 2.94e-07 7.6%Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%---------------------------------------------------------------Total 3.48e-06 6.72e-08 3.12e-07 3.86e-06 100.0% 90.2% 1.7% 8.1% - report_pulse_width_checks + report_pulse_width_checks [-verbose][-digits digits][-no_line_splits][pins][> filename][>> filename] @@ -9719,7 +9741,7 @@ - -verbose + -verbose Use a verbose output format. @@ -9727,10 +9749,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9751,86 +9773,86 @@ - The report_pulse_width_checks command reports min pulse width checks for pins in the clock network. If pins is not specified all clock network pins are reported. + The report_pulse_width_checks command reports min pulse width checks for pins in the clock network. If pins is not specified all clock network pins are reported. - report_slews + report_slews - [-corner corner]pin + [-corner corner]pin - -corner corner + -corner corner - Report paths for process corner. The -corner keyword is required if more than one process corner is defined. + Report paths for process corner. The -corner keyword is required if more than one process corner is defined. - pin + pin - + - Report the slews at pin + Report the slews at pin - report_tns + report_tns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the total max/setup slack. + Report the total max/setup slack. - -min + -min - Report the total min/hold slack. + Report the total min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the total negative slack. + Report the total negative slack. - report_units + report_units - Report the units used for command arguments and reporting. + Report the units used for command arguments and reporting. report_units time 1ns capacitance 1pF resistance 1kohm voltage 1v current 1A power 1pW distance 1um @@ -9838,44 +9860,44 @@ - report_wns + report_wns - [-min][-max][-digits digits] + [-min][-max][-digits digits] - -max + -max - Report the worst max/setup slack. + Report the worst max/setup slack. - -min + -min - Report the worst min/hold slack. + Report the worst min/hold slack. - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. - Report the worst negative slack. If the worst slack is positive, zero is reported. + Report the worst negative slack. If the worst slack is positive, zero is reported. - report_worst_slack + report_worst_slack [-min][-max][-digits digits] @@ -9899,10 +9921,10 @@ - -digits digits + -digits digits - The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. + The number of digits after the decimal point to report. The default value is the variable sta_report_default_digits. @@ -9912,7 +9934,7 @@ - set_assigned_check + set_assigned_check -setup|-hold|-recovery|-removal[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins][-clock rise|fall][-cond sdf_cond][-worst]margin @@ -9923,7 +9945,7 @@ -setup - Annotate setup timing checks. + Annotate setup timing checks. @@ -9931,7 +9953,7 @@ -hold - Annotate hold timing checks. + Annotate hold timing checks. @@ -9940,7 +9962,7 @@ -recovery - Annotate recovery timing checks. + Annotate recovery timing checks. @@ -9948,7 +9970,7 @@ -removal - Annotate removal timing checks. + Annotate removal timing checks. @@ -9969,10 +9991,10 @@ - -corner corner + -corner corner - The name of a process corner. The -corner keyword is required if more than one process corner is defined. + The name of a process corner. The -corner keyword is required if more than one process corner is defined. @@ -9993,7 +10015,7 @@ - -from from_pins + -from from_pins A list of pins for the clock. @@ -10001,7 +10023,7 @@ - -to to_pins + -to to_pins A list of pins for the data. @@ -10009,10 +10031,10 @@ - -clock rise|fall + -clock rise|fall - The timing check clock pin transition. + The timing check clock pin transition. @@ -10020,7 +10042,7 @@ margin - The timing check margin. + The timing check margin. @@ -10030,7 +10052,7 @@ - set_assigned_delay + set_assigned_delay -cell|-net[-rise][-fall][-corner corner][-min][-max][-from from_pins][-to to_pins]delay @@ -10071,10 +10093,10 @@ - -corner corner + -corner corner - The name of a process corner. The -corner keyword is required if more than one process corner is defined. + The name of a process corner. The -corner keyword is required if more than one process corner is defined. @@ -10095,7 +10117,7 @@ - -from from_pins + -from from_pins A list of pins. @@ -10103,7 +10125,7 @@ - -to to_pins + -to to_pins A list of pins. @@ -10125,7 +10147,7 @@ - set_assigned_transition + set_assigned_transition [-rise][-fall][-corner corner][-min][-max]slewpin_list @@ -10149,10 +10171,10 @@ - -corner corner + -corner corner - Annotate delays for process corner. + Annotate delays for process corner. @@ -10195,7 +10217,7 @@ - set_case_analysis + set_case_analysis 0|1|zero|one|rise|rising|fall|fallingport_or_pin_list @@ -10211,13 +10233,13 @@ The set_case_analysis command sets the signal on a port or pin to a constant logic value. No paths are propagated from constant pins. Constant values set with the set_case_analysis command are propagated through downstream gates. - Conditional timing arcs with mode groups are controlled by logic values on the instance pins. + Conditional timing arcs with mode groups are controlled by logic values on the instance pins. - set_clock_gating_check + set_clock_gating_check [-setup setup_time][-hold hold_time][-rise][-fall][-high][-low][objects] @@ -10225,7 +10247,7 @@ - -setup setup_time + -setup setup_time Clock enable setup margin. @@ -10233,7 +10255,7 @@ - -hold hold_time + -hold hold_time Clock enable hold margin. @@ -10290,7 +10312,7 @@ - set_clock_groups + set_clock_groups [-name name][-logically_exclusive][-physically_exclusive][-asynchronous][-allow_paths]-group clocks @@ -10298,7 +10320,7 @@ - -name name + -name name The clock group name. @@ -10351,7 +10373,7 @@ - set_clock_latency + set_clock_latency [-source][-clock clock][-rise][-fall][-min][-max]delayobjects @@ -10359,7 +10381,7 @@ - -source + -source The latency is at the clock source. @@ -10367,7 +10389,7 @@ - -clock clock + -clock clock If multiple clocks are defined at a pin this use this option to specify the latency for a specific clock. @@ -10429,7 +10451,7 @@ - set_clock_transition + set_clock_transition [-rise][-fall][-min][-max]transitionclocks @@ -10440,7 +10462,7 @@ -rise - Set the transition time for the rising edge of the clock. + Set the transition time for the rising edge of the clock. @@ -10448,7 +10470,7 @@ -fall - Set the transition time for the falling edge of the clock. + Set the transition time for the falling edge of the clock. @@ -10456,7 +10478,7 @@ -min - Set the min transition time. + Set the min transition time. @@ -10464,7 +10486,7 @@ -max - Set the min transition time. + Set the min transition time. @@ -10491,7 +10513,7 @@ - set_clock_uncertainty + set_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold]uncertainty[objects] @@ -10499,18 +10521,18 @@ - -from from_clock + -from from_clock - Inter-clock uncertainty source clock. + Inter-clock uncertainty source clock. - -to to_clock + -to to_clock - Inter-clock uncertainty target clock. + Inter-clock uncertainty target clock. @@ -10518,7 +10540,7 @@ -rise - Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. + Inter-clock target clock rise edge, alternative to ‑rise_to.Inter-clock target clock rise edge, alternative to ‑rise_to. @@ -10526,7 +10548,7 @@ -fall - Inter-clock target clock rise edge, alternative to ‑fall_to. + Inter-clock target clock rise edge, alternative to ‑fall_to. @@ -10534,7 +10556,7 @@ -setup - uncertainty is for setup checks. + uncertainty is for setup checks. @@ -10542,12 +10564,12 @@ -hold - uncertainty is for hold checks. + uncertainty is for hold checks. - uncertainty + uncertainty Clock uncertainty. @@ -10562,82 +10584,82 @@ - The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. - set_clock_uncertainty .1 [get_clock clk1] - Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . - set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 - The following commands are equivalent. - set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 + The set_clock_uncertainty command specifies the uncertainty or jitter in a clock. The uncertainty for a clock can be specified on its source pin or port, or the clock itself. + set_clock_uncertainty .1 [get_clock clk1] + Inter-clock uncertainty between the source and target clocks of timing checks is specified with the ‑from|‑rise_from|-fall_from and ‑to|‑rise_to|-fall_to arguments . + set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] .1 + The following commands are equivalent. + set_clock_uncertainty -from [get_clock clk1] -rise_to [get_clocks clk2] .1set_clock_uncertainty -from [get_clock clk1] -to [get_clocks clk2] -rise .1 - set_cmd_units + set_cmd_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - -distance distance_unit + -distance distance_unit - The distance scale factor followed by 'm'. + The distance scale factor followed by 'm'. - The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. + The set_cmd_units command is used to change the units used by the STA command interpreter when parsing commands and reporting results. The default units are the units specified in the first Liberty library file that is read. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. @@ -10648,15 +10670,15 @@ - set_data_check + set_data_check - [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin + [-from|-rise_from|-fall_from from_pin][-to|-rise_to|-fall_to to_pin][-setup][-hold][-clock clock]margin - -from from_pin + -from from_pin A pin used as the timing check reference. @@ -10664,7 +10686,7 @@ - -to to_pin + -to to_pin A pin that the setup/hold check is applied to. @@ -10688,7 +10710,7 @@ - -clock clock + -clock clock The setup/hold check clock. @@ -10709,7 +10731,7 @@ - set_disable_inferred_clock_gating + set_disable_inferred_clock_gating objects @@ -10724,13 +10746,13 @@ - The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. + The set_disable_inferred_clock_gating command disables clock gating checks on a clock gating instance, clock gating pin, or clock gating enable pin. - set_disable_timing + set_disable_timing [-from from_port][-to to_port]objects @@ -10738,18 +10760,18 @@ - -from from_port + -from from_port - + - -to to_port + -to to_port - + @@ -10757,7 +10779,7 @@ objects - A list of instances, ports, pins, cells, cell/port, or library/cell/port. + A list of instances, ports, pins, cells, cell/port, or library/cell/port. @@ -10775,10 +10797,10 @@ - set_drive + set_drive - [-rise][-fall][-max][-min]resistanceports + [-rise][-fall][-max][-min]resistanceports @@ -10786,7 +10808,7 @@ -rise - Set the drive rise resistance. + Set the drive rise resistance. @@ -10794,7 +10816,7 @@ -fall - Set the drive fall resistance. + Set the drive fall resistance. @@ -10802,7 +10824,7 @@ -max - Set the maximum resistance. + Set the maximum resistance. @@ -10810,7 +10832,7 @@ -min - Set the minimum resistance. + Set the minimum resistance. @@ -10823,7 +10845,7 @@ - ports + ports A list of ports. @@ -10837,26 +10859,26 @@ - set_driving_cell + set_driving_cell - [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports + [-lib_cell cell_name][-library library][-rise][-fall][-min][-max][-pin pin][-from_pin from_pin][-input_transition_rise trans_rise][-input_transition_fall trans_fall]ports - -lib_cell cell_name + -lib_cell cell_name - The driving cell. + The driving cell. - -library library + -library library - The driving cell library. + The driving cell library. @@ -10864,7 +10886,7 @@ -rise - Set the driving cell for a rising edge. + Set the driving cell for a rising edge. @@ -10872,7 +10894,7 @@ -fall - Set the driving cell for a falling edge. + Set the driving cell for a falling edge. @@ -10880,7 +10902,7 @@ -max - Set the driving cell for max delays. + Set the driving cell for max delays. @@ -10888,12 +10910,12 @@ -min - Set the driving cell for min delays. + Set the driving cell for min delays. - -pin pin + -pin pin The output port of the driving cell. @@ -10901,15 +10923,15 @@ - -from_pin from_pin + -from_pin from_pin - Use timing arcs from from_pin to the output pin. + Use timing arcs from from_pin to the output pin. - -input_transition_rise trans_rise + -input_transition_rise trans_rise The transition time for a rising input at from_pin. @@ -10917,7 +10939,7 @@ - -input_transition_fall trans_fall + -input_transition_fall trans_fall The transition time for a falling input at from_pin. @@ -10925,7 +10947,7 @@ - ports + ports A list of ports. @@ -10939,7 +10961,7 @@ - set_false_path + set_false_path [-setup][-hold][-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path] @@ -10950,7 +10972,7 @@ -setup - Apply to setup checks. + Apply to setup checks. @@ -10958,7 +10980,7 @@ -hold - Apply to hold checks. + Apply to hold checks. @@ -10966,7 +10988,7 @@ -rise - Apply to rising path edges. + Apply to rising path edges. @@ -10974,7 +10996,7 @@ -fall - Apply to falling path edges. + Apply to falling path edges. @@ -10987,7 +11009,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -10995,7 +11017,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11003,7 +11025,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11020,7 +11042,7 @@ - set_fanout_load + set_fanout_load fanoutport_list @@ -11033,7 +11055,7 @@ - set_hierarchy_separator + set_hierarchy_separator separator @@ -11054,7 +11076,7 @@ - set_ideal_latency + set_ideal_latency [-rise] [-fall] [-min] [-max] delay objects @@ -11067,7 +11089,7 @@ - set_ideal_network + set_ideal_network [-no_propagation] objects @@ -11080,7 +11102,7 @@ - set_ideal_transition + set_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects @@ -11093,7 +11115,7 @@ - set_input_delay + set_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -11104,7 +11126,7 @@ -rise - Set the arrival time for the rising edge of the input. + Set the arrival time for the rising edge of the input. @@ -11112,7 +11134,7 @@ -fall - Set the arrival time for the falling edge of the input. + Set the arrival time for the falling edge of the input. @@ -11121,7 +11143,7 @@ -max - Set the maximum arrival time. + Set the maximum arrival time. @@ -11129,12 +11151,12 @@ -min - Set the minimum arrival time. + Set the minimum arrival time. - -clock clock + -clock clock The arrival time is from clock. @@ -11150,7 +11172,7 @@ - -reference_pin ref_pin + -reference_pin ref_pin The arrival time is with respect to the clock that arrives at ref_pin. @@ -11161,7 +11183,7 @@ -source_latency_included - D no add the clock source latency (insertion delay) to the delay value. + D no add the clock source latency (insertion delay) to the delay value. @@ -11169,7 +11191,7 @@ -network_latency_included - Do not add the clock latency to the delay value when the clock is ideal. + Do not add the clock latency to the delay value when the clock is ideal. @@ -11197,20 +11219,20 @@ - The set_input_delay command is used to specify the arrival time of an input signal. - The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. - set_input_delay -clock clk1 1.0 [get_ports in1] - Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. - set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] - The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. + The set_input_delay command is used to specify the arrival time of an input signal. + The following command sets the min, max, rise and fall times on the in1 input port 1.0 time units after the rising edge of clk1. + set_input_delay -clock clk1 1.0 [get_ports in1] + Use multiple commands with the -add_delay option to specify separate arrival times for min, max, rise and fall times or multiple clocks. For example, the following specifies separate arrival times with respect to clocks clk1 and clk2. + set_input_delay -clock clk1 1.0 [get_ports in1]set_input_delay -add_delay -clock clk2 2.0 [get_ports in1] + The –reference_pin option is used to specify an arrival time with respect to the arrival on a pin in the clock network. For propagated clocks, the input arrival time is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, input arrival time is relative to the reference pin clock source latency. With the -clock_fall flag the arrival time is relative to the falling transition at the reference pin. If no clocks arrive at the reference pin the set_input_delay command is ignored. If no -clock is specified the arrival time is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + Paths from inputs that do not have an arrival time defined by set_input_delay are not reported. Set the sta_input_port_default_clock variable to 1 to report paths from inputs without a set_input_delay. - set_input_transition + set_input_transition [-rise][-fall][-max][-min]transitionport_list @@ -11221,7 +11243,7 @@ -rise - Set the rising edge transition. + Set the rising edge transition. @@ -11229,7 +11251,7 @@ -fall - Set the falling edge transition. + Set the falling edge transition. @@ -11237,7 +11259,7 @@ -max - Set the minimum transition time. + Set the minimum transition time. @@ -11245,7 +11267,7 @@ -min - Set the maximum transition time. + Set the maximum transition time. @@ -11271,7 +11293,7 @@ - set_level_shifter_strategy + set_level_shifter_strategy [-rule rule_type] @@ -11284,7 +11306,7 @@ - set_level_shifter_threshold + set_level_shifter_threshold [-voltage voltage] @@ -11297,7 +11319,7 @@ - set_load + set_load [-rise][-fall][-max][-min][-subtract_pin_load][-pin_load][-wire_load]capacitanceobjects @@ -11308,7 +11330,7 @@ -rise - Set the external port rising capacitance (ports only). + Set the external port rising capacitance (ports only). @@ -11316,7 +11338,7 @@ -fall - Set the external port falling capacitance (ports only). + Set the external port falling capacitance (ports only). @@ -11325,7 +11347,7 @@ -max - Set the max capacitance. + Set the max capacitance. @@ -11333,7 +11355,7 @@ -min - Set the min capacitance. + Set the min capacitance. @@ -11341,7 +11363,7 @@ -subtract_pin_load - Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. + Subtract the capacitance of all instance pins connected to the net from capacitance (nets only). If the resulting capacitance is negative, zero is used. Pin capacitances are ignored by delay calculation when this option is used. @@ -11377,16 +11399,16 @@ - The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: - set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance - External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. - When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. + The set_load command annotates wire capacitance on a net or external capacitance on a port. There are four different uses for the set_load commanc: + set_load -wire_load port external port wire capacitanceset_load -pin_load port external port pin capacitanceset_load port same as -pin_loadset_load net net wire capacitance + External port capacitance can be annotated separately with the -pin_load and ‑wire_load options. Without the -pin_load and -wire_load options pin capacitance is annotated. + When annotating net wire capacitance with the -subtract_pin_load option the capacitance of all instance pins connected to the net is subtracted from capacitance. Setting the capacitance on a net overrides SPEF parasitics for delay calculation. - set_logic_dc + set_logic_dc port_list @@ -11407,7 +11429,7 @@ - set_logic_one + set_logic_one port_list @@ -11422,14 +11444,14 @@ - Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. + Set a port or pin to a constant logic one value. No paths are propagated from constant pins. Constant values set with the set_logic_one command are not propagated through downstream gates. - set_logic_zero + set_logic_zero port_list @@ -11444,13 +11466,13 @@ - Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. + Set a port or pin to a constant logic zero value. No paths are propagated from constant pins. Constant values set with the set_logic_zero command are not propagated through downstream gates. - set_max_area + set_max_area area @@ -11471,7 +11493,7 @@ - set_max_capacitance + set_max_capacitance capacitanceobjects @@ -11500,10 +11522,10 @@ - set_max_delay + set_max_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11511,7 +11533,7 @@ -rise - Set max delay for rising paths. + Set max delay for rising paths. @@ -11519,13 +11541,13 @@ -fall - Set max delay for falling paths. + Set max delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11533,7 +11555,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11541,7 +11563,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11557,10 +11579,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -11587,7 +11609,7 @@ - set_max_dynamic_power + set_max_dynamic_power power [unit] @@ -11600,7 +11622,7 @@ - set_max_fanout + set_max_fanout fanoutobjects @@ -11629,7 +11651,7 @@ - set_max_leakage_power + set_max_leakage_power power [unit] @@ -11642,7 +11664,7 @@ - set_max_time_borrow + set_max_time_borrow delayobjects @@ -11666,13 +11688,13 @@ - The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. + The set_max_time_borrow command specifies the maximum amount of time that latches can borrow. Time borrowing is the time that a data input to a transparent latch arrives after the latch opens. - set_max_transition + set_max_transition [-data_path][-clock_path][-rise][-fall]transitionobjects @@ -11680,34 +11702,34 @@ - -data_path + -data_path - Set the max slew for data paths. + Set the max slew for data paths. - -clock_path + -clock_path - Set the max slew for clock paths. + Set the max slew for clock paths. - -rise + -rise - Set the max slew for rising paths. + Set the max slew for rising paths. - -fall + -fall - Set the max slew for falling paths. + Set the max slew for falling paths. @@ -11715,7 +11737,7 @@ transition - The maximum slew/transition time. + The maximum slew/transition time. @@ -11727,7 +11749,7 @@ - The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. + The set_max_transition command is specifies the maximum transition time (slew) design rule checked by the report_check_types –max_transition command. If specified for a design, the default maximum transition is set for the design. If specified for a clock, the maximum transition is applied to all pins in the clock domain. The –clock_path option restricts the maximum transition to clocks in clock paths. The -data_path option restricts the maximum transition to clocks data paths. The –clock_path, -data_path, -rise and –fall options only apply to clock objects. @@ -11735,7 +11757,7 @@ - set_min_capacitance + set_min_capacitance capacitanceobjects @@ -11746,7 +11768,7 @@ capacitance - Minimum capacitance. + Minimum capacitance. @@ -11765,10 +11787,10 @@ - set_min_delay + set_min_delay - [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay + [-rise][-fall][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-ignore_clock_latency][-probe][-reset_path]delay @@ -11776,7 +11798,7 @@ -rise - Set min delay for rising paths. + Set min delay for rising paths. @@ -11784,12 +11806,12 @@ -fall - Set min delay for falling paths. + Set min delay for falling paths. - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11797,7 +11819,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11805,7 +11827,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11821,10 +11843,10 @@ - -probe + -probe - Do not break paths at internal pins (non startpoints). + Do not break paths at internal pins (non startpoints). @@ -11840,7 +11862,7 @@ delay - The minimum delay. + The minimum delay. @@ -11852,7 +11874,7 @@ - set_min_pulse_width + set_min_pulse_width [-high][-low]min_widthobjects @@ -11897,7 +11919,7 @@ - set_multicycle_path + set_multicycle_path [-setup][-hold][-rise][-fall][-start][-end][-from from_list][-rise_from from_list][-fall_from from_list][-through through_list][-rise_through through_list][-fall_through through_list][-to to_list][-rise_to to_list][-fall_to to_list][-reset_path]path_multiplier @@ -11908,7 +11930,7 @@ -setup - Set cycle count for setup checks. + Set cycle count for setup checks. @@ -11916,7 +11938,7 @@ -hold - Set cycle count for hold checks. + Set cycle count for hold checks. @@ -11924,7 +11946,7 @@ -rise - Set cycle count for rising path edges. + Set cycle count for rising path edges. @@ -11932,7 +11954,7 @@ -fall - Set cycle count for falling path edges. + Set cycle count for falling path edges. @@ -11954,7 +11976,7 @@ - -from from_list + -from from_list A list of clocks, instances, ports or pins. @@ -11962,7 +11984,7 @@ - -through through_list + -through through_list A list of instances, pins or nets. @@ -11970,7 +11992,7 @@ - -to to_list + -to to_list A list of clocks, instances, ports or pins. @@ -11999,15 +12021,15 @@ - set_operating_conditions + set_operating_conditions - [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] + [-analysis_type single|bc_wc|on_chip_variation][-library lib][condition][-min min_condition][-max max_condition][-min_library min_lib][-max_library max_lib] - -analysis_type single + -analysis_type single Use one operating condition for min and max paths. @@ -12015,7 +12037,7 @@ - -analysis_type bc_wc + -analysis_type bc_wc Best case, worst case analysis. Setup checks use max_condition for clock and data paths. Hold checks use the min_condition for clock and data paths. @@ -12023,7 +12045,7 @@ - ‑analysis_type on_chip_variation + ‑analysis_type on_chip_variation The min and max operating conditions represent variations on the chip that can occur simultaneously. Setup checks use max_condition for data paths and min_condition for clock paths. Hold checks use min_condition for data paths and max_condition for clock paths. This is the default analysis type. @@ -12031,7 +12053,7 @@ - -library lib + -library lib The name of the library that contains condition. @@ -12047,7 +12069,7 @@ - -min min_condition + -min min_condition The operating condition to use for min paths and hold checks. @@ -12055,7 +12077,7 @@ - -max max_condition + -max max_condition The operating condition to use for max paths and setup checks. @@ -12063,7 +12085,7 @@ - -min_library min_lib + -min_library min_lib The name of the library that contains min_condition. @@ -12071,7 +12093,7 @@ - -max_library max_lib + -max_library max_lib The name of the library that contains max_condition. @@ -12084,7 +12106,7 @@ - set_output_delay + set_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall][-reference_pin ref_pin][-source_latency_included][-network_latency_included][-add_delay]delayport_pin_list @@ -12095,7 +12117,7 @@ -rise - Set the output delay for the rising edge of the input. + Set the output delay for the rising edge of the input. @@ -12103,7 +12125,7 @@ -fall - Set the output delay for the falling edge of the input. + Set the output delay for the falling edge of the input. @@ -12111,7 +12133,7 @@ -max - Set the maximum output delay. + Set the maximum output delay. @@ -12119,15 +12141,15 @@ -min - Set the minimum output delay. + Set the minimum output delay. - -clock clock + -clock clock - The external check is to clock. The default clock edge is rising. + The external check is to clock. The default clock edge is rising. @@ -12135,15 +12157,15 @@ -clock_fall - The external check is to the falling edge of clock. + The external check is to the falling edge of clock. - -reference_pin ref_pin + -reference_pin ref_pin - The external check is clocked by the clock that arrives at ref_pin. + The external check is clocked by the clock that arrives at ref_pin. @@ -12151,7 +12173,7 @@ -add_delay - Add this output delay to any existing output delays. + Add this output delay to any existing output delays. @@ -12159,7 +12181,7 @@ delay - The external delay to the check clocked by clock. + The external delay to the check clocked by clock. @@ -12171,17 +12193,17 @@ - The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. - The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. + The set_output_delay command is used to specify the external delay to a setup/hold check on an output port or internal pin that is clocked by clock. Unless the -add_delay option is specified any existing output delays are replaced. + The –reference_pin option is used to specify a timing check with respect to the arrival on a pin in the clock network. For propagated clocks, the timing check is relative to the clock arrival time at the reference pin (the clock source latency and network latency from the clock source to the reference pin). For ideal clocks, the timing check is relative to the reference pin clock source latency. With the -clock_fall flag the timing check is relative to the falling edge of the reference pin. If no clocks arrive at the reference pin the set_output_delay command is ignored. If no -clock is specified the timing check is with respect to all clocks that arrive at the reference pin. The -source_latency_included and -network_latency_included options cannot be used with -reference_pin. - set_port_fanout_number + set_port_fanout_number - [-min][-max]fanoutports + [-min][-max]fanoutports @@ -12189,7 +12211,7 @@ -min - Set the min fanout. + Set the min fanout. @@ -12197,7 +12219,7 @@ -max - Set the max fanout. + Set the max fanout. @@ -12217,21 +12239,21 @@ - Set the external fanout for ports. + Set the external fanout for ports. - set_power_activity + set_power_activity - [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] + [-global][-input][-input_ports ports][-pins pins][-activity activity | -density density][-duty duty][-clock clock] - -global + -global Set the activity/duty for all non-clock pins. @@ -12247,7 +12269,7 @@ - -input_ports input_ports + -input_ports input_ports Set the input port activity/duty. @@ -12255,7 +12277,7 @@ - -pins pins + -pins pins Set the pin activity/duty. @@ -12263,46 +12285,46 @@ - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - -density density + -density density - Transitions per library time unit. + Transitions per library time unit. - -duty duty + -duty duty - The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. + The duty, or probability the signal is high (0 <= duty <= 1.0). Defaults to 0.5. - -clock clock + -clock clock - The clock to use for the period with -activity. This option is ignored if -density is used. + The clock to use for the period with -activity. This option is ignored if -density is used. - The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. - The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: - set_power_activity -input -activity 0.1 -duty 0.5 + The set_power_activity command is used to set the activity and duty used for power analysis globally or for input ports or pins in the design. + The default input activity for inputs is 0.1 transitions per minimum clock period if a clock is defined or 0.0 if there are no clocks defined. The default input duty is 0.5. This is equivalent to the following command: + set_power_activity -input -activity 0.1 -duty 0.5 - set_propagated_clock + set_propagated_clock objects @@ -12323,11 +12345,11 @@ - set_pvt + set_pvt - [-min][-max][-process process][-voltage voltage] - [-temperature temperature]instances + [-min][-max][-process process][-voltage voltage] + [-temperature temperature]instances @@ -12335,7 +12357,7 @@ -min - Set the PVT values for max delays. + Set the PVT values for max delays. @@ -12343,12 +12365,12 @@ -max - Set the PVT values for min delays. + Set the PVT values for min delays. - -process process + -process process A process value (float). @@ -12356,7 +12378,7 @@ - -voltage voltage + -voltage voltage A voltage value (float). @@ -12364,7 +12386,7 @@ - -temperature temperature + -temperature temperature A temperature value (float). @@ -12386,7 +12408,7 @@ - set_sense + set_sense [-type clock|data][-positive][-negative][-pulse pulse_type][-stop_propagation][-clock clocks]pins @@ -12394,18 +12416,18 @@ - -type clock + -type clock - Set the sense for clock paths. + Set the sense for clock paths. - -type data + -type data - Set the sense for data paths (not supported). + Set the sense for data paths (not supported). @@ -12413,7 +12435,7 @@ -positive - The clock sense is positive unate. + The clock sense is positive unate. @@ -12421,15 +12443,15 @@ -negative - The clock sense is negative unate. + The clock sense is negative unate. - -pulse pulse_type + -pulse pulse_type - rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. + rise_triggered_high_pulserise_triggered_low_pulsefall_triggered_high_pulsefall_triggered_low_pulseNot supported. @@ -12464,7 +12486,7 @@ - set_timing_derate + set_timing_derate [-rise][-fall][-early][-late][-clock][-data][-net_delay][-cell_delay][-cell_check]derate[objects] @@ -12472,18 +12494,18 @@ - -rise + -rise - Set the derating for rising delays. + Set the derating for rising delays. - -fall + -fall - Set the derating for falling delays. + Set the derating for falling delays. @@ -12547,7 +12569,7 @@ derate - The derating factor to apply to delays. + The derating factor to apply to delays. @@ -12566,10 +12588,10 @@ - set_resistance + set_resistance - [-max][-min]resistancenets + [-max][-min]resistancenets @@ -12599,7 +12621,7 @@ - nets + nets A list of nets. @@ -12612,72 +12634,72 @@ - set_units + set_units - [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] + [-capacitance cap_unit][-resistance res_unit][-time time_unit][-voltage voltage_unit][-current current_unit][-power power_unit][-distance distance_unit] - -capacitance cap_unit + -capacitance cap_unit - The capacitance scale factor followed by 'f'. + The capacitance scale factor followed by 'f'. - -resistance res_unit + -resistance res_unit - The resistance scale factor followed by 'ohm'. + The resistance scale factor followed by 'ohm'. - -time time_unit + -time time_unit - The time scale factor followed by 's'. + The time scale factor followed by 's'. - -voltage voltage_unit + -voltage voltage_unit - The voltage scale factor followed by 'v'. + The voltage scale factor followed by 'v'. - -current current_unit + -current current_unit - The current scale factor followed by 'A'. + The current scale factor followed by 'A'. - -power power_unit + -power power_unit - The power scale factor followed by 'w'. + The power scale factor followed by 'w'. - The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. + The set_units command is used to check the units used by the STA command interpreter when parsing commands and reporting results. If the current units differ from the set_unit value a warning is printed. Use the set_cmd_units command to change the command units. Units are specified as a scale factor followed by a unit name. The scale factors are as follows. - M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 + M 1E+6k 1E+3m 1E-3u 1E-6n 1E-9p 1E-12f 1E-15 An example of the set_units command is shown below. - set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm + set_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm - set_wire_load_min_block_size + set_wire_load_min_block_size size @@ -12690,7 +12712,7 @@ - set_wire_load_mode + set_wire_load_mode top|enclosed|segmented @@ -12727,7 +12749,7 @@ - set_wire_load_model + set_wire_load_model -name model_name[-library library][-max][-min][objects] @@ -12735,7 +12757,7 @@ - -name model_name + -name model_name The name of a wire load model. @@ -12743,7 +12765,7 @@ - -library library + -library library Library to look for model_name. @@ -12780,7 +12802,7 @@ - set_wire_load_selection_group + set_wire_load_selection_group [-library library][-max][-min]group_name[objects] @@ -12834,28 +12856,28 @@ - suppress_msg + suppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to suppress. + A list of error/warning message IDs to suppress. - The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The suppress_msg command suppresses specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - unset_case_analysis + unset_case_analysis port_or_pin_list @@ -12876,7 +12898,7 @@ - unset_clock_latency + unset_clock_latency [-source]objects @@ -12905,7 +12927,7 @@ - unset_clock_transition + unset_clock_transition clocks @@ -12927,7 +12949,7 @@ - unset_clock_uncertainty + unset_clock_uncertainty [-from|-rise_from|-fall_from from_clock][-to|-rise_to|-fall_to to_clock][-rise][-fall][-setup][-hold][objects] @@ -12935,7 +12957,7 @@ - -from from_clock + -from from_clock @@ -12943,7 +12965,7 @@ - -to to_clock + -to to_clock @@ -12983,7 +13005,7 @@ - uncertainty + uncertainty Clock uncertainty. @@ -13004,15 +13026,15 @@ - unset_data_check + unset_data_check - [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] + [-from|-rise_from|-fall_from from_object][-to|-rise_to|-fall_to to_object][-setup][-hold][-clock clock] - -from from_object + -from from_object A pin used as the timing check reference. @@ -13020,7 +13042,7 @@ - -to to_object + -to to_object A pin that the setup/hold check is applied to. @@ -13044,7 +13066,7 @@ - clock + clock The setup/hold check clock. @@ -13057,7 +13079,7 @@ - unset_disable_inferred_clock_gating + unset_disable_inferred_clock_gating objects @@ -13072,13 +13094,13 @@ - The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. + The unset_disable_inferred_clock_gating command removes a previous set_disable_inferred_clock_gating command. - unset_disable_timing + unset_disable_timing [-from from_port][-to to_port]objects @@ -13089,7 +13111,7 @@ from_port - + @@ -13097,7 +13119,7 @@ to_port - + @@ -13115,7 +13137,7 @@ - unset_input_delay + unset_input_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13126,7 +13148,7 @@ -rise - Unset the arrival time for the rising edge of the input. + Unset the arrival time for the rising edge of the input. @@ -13134,7 +13156,7 @@ -fall - Unset the arrival time for the falling edge of the input. + Unset the arrival time for the falling edge of the input. @@ -13142,7 +13164,7 @@ -max - Unset the minimum arrival time. + Unset the minimum arrival time. @@ -13150,7 +13172,7 @@ -min - Unset the maximum arrival time. + Unset the maximum arrival time. @@ -13158,7 +13180,7 @@ clock - Unset the arrival time from clock. + Unset the arrival time from clock. @@ -13166,7 +13188,7 @@ -clock_fall - Unset the arrival time from the falling edge of clock + Unset the arrival time from the falling edge of clock @@ -13185,7 +13207,7 @@ - unset_output_delay + unset_output_delay [-rise][-fall][-max][-min][-clock clock][-clock_fall]port_pin_list @@ -13254,10 +13276,10 @@ - unset_path_exceptions + unset_path_exceptions - [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] + [-setup][-hold][-rise][-fall][-from|-rise_from|-fall_from from][-through|-rise_through|-fall_through through][-to|-rise_to|-fall_to to] @@ -13265,7 +13287,7 @@ -setup - Unset path exceptions for setup checks. + Unset path exceptions for setup checks. @@ -13273,7 +13295,7 @@ -hold - Unset path exceptions for hold checks. + Unset path exceptions for hold checks. @@ -13281,7 +13303,7 @@ -rise - Unset path exceptions for rising path edges. + Unset path exceptions for rising path edges. @@ -13290,12 +13312,12 @@ -fall - Unset path exceptions for falling path edges. + Unset path exceptions for falling path edges. - -from from + -from from A list of clocks, instances, ports or pins. @@ -13303,7 +13325,7 @@ - -through through + -through through A list of instances, pins or nets. @@ -13311,7 +13333,7 @@ - -to to + -to to A list of clocks, instances, ports or pins. @@ -13319,66 +13341,66 @@ The unset_path_exceptions command removes any matching set_false_path, set_multicycle_path, set_max_delay, and set_min_delay exceptions. - + - unset_power_activity + unset_power_activity - [-global][-input][-input_ports ports][-pins pins] + [-global][-input][-input_ports ports][-pins pins] - -global + -global - Set the activity/duty for all non-clock pins. + Set the activity/duty for all non-clock pins. - -input + -input - Set the default input port activity/duty. + Set the default input port activity/duty. - -input_ports input_ports + -input_ports input_ports - Set the input port activity/duty. + Set the input port activity/duty. - -pins pins + -pins pins - Set the pin activity/duty. + Set the pin activity/duty. - -activity activity + -activity activity - The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. + The activity, or number of transitions per clock cycle. If clock is not specified the clock with the minimum period is used. If no clocks are defined an error is reported. - The unset_power_activity_command is used to undo the effects of the set_power_activity command. + The unset_power_activity_command is used to undo the effects of the set_power_activity command. - unset_propagated_clock + unset_propagated_clock objects @@ -13399,42 +13421,42 @@ - unset_timing_derate + unset_timing_derate - Remove all derating factors set with the set_timing_derate command. + Remove all derating factors set with the set_timing_derate command. - unsuppress_msg + unsuppress_msg - msg_ids + msg_ids - msg_ids + msg_ids - A list of error/warning message IDs to unsuppress. + A list of error/warning message IDs to unsuppress. - The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. + The unsuppress_msg command removes suppressions for the specified error/warning messages by ID. The list of message IDs can be found in doc/messages.txt. - user_run_time + user_run_time @@ -13447,7 +13469,7 @@ - with_output_to_variable + with_output_to_variable var { commands } @@ -13470,21 +13492,21 @@ - The with_output_to_variable command redirects the output of TCL commands to a variable. + The with_output_to_variable command redirects the output of TCL commands to a variable. - write_path_spice + write_path_spice - -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] + -path_args path_args-spice_directory spice_directory-lib_subckt_file lib_subckts_file-model_file model_file-power power-ground ground[-simulator hspice|ngspice|xyce] - path_args + path_args -from|-through|-to arguments as in report_checks. @@ -13492,15 +13514,15 @@ - spice_directory + spice_directory - Directory for spice to write output files. + Directory for spice to write output files. - lib_subckts_file + lib_subckts_file Cell transistor level subckts. @@ -13508,7 +13530,7 @@ - model_file + model_file Transistor model definitions .included by spice_file. @@ -13516,7 +13538,7 @@ - power + power Voltage supply name in voltage_map of the default liberty library. @@ -13524,7 +13546,7 @@ - ground + ground Ground supply name in voltage_map of the default liberty library. @@ -13532,25 +13554,25 @@ - -simulator + -simulator - Simulator that will read the spice netlist. + Simulator that will read the spice netlist. The write_path_spice command writes a spice netlist for timing paths. Use path_args to specify -from/-through/-to as arguments to the find_timing_paths command. For each path, a spice netlist and the subckts referenced by the path are written in spice_directory. The spice netlist is written in path_<id>.sp and subckt file is path_<id>.subckt. The spice netlists used by the path are written to subckt_file, which spice_file .includes. The device models used by the spice subckt netlists in model_file are also .included in spice_file. Power and ground names are specified with the -power and -ground arguments. The spice netlist includes a piecewise linear voltage source at the input and .measure statement for each gate delay and pin slew. - Example command: - write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS - When the simulator is hspice, .measure statements will be added to the spice netlist. - When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. + Example command: + write_path_spice -path_args {-from "in0" -to "out1" -unconstrained} \ -spice_directory $result_dir \ -lib_subckt_file "write_spice1.subckt" \ -model_file "write_spice1.models" \ -power VDD -ground VSS + When the simulator is hspice, .measure statements will be added to the spice netlist. + When the simulator is Xyce, the .print statement selects the CSV format and writes the waveform data to a file name path_<id>.csv so the results can be used by gnuplot. - write_sdc + write_sdc [-digits digits][-gzip][-no_timestamp]filename @@ -13569,7 +13591,7 @@ -gzip - Compress the SDC with gzip. + Compress the SDC with gzip. @@ -13595,7 +13617,7 @@ - write_sdf + write_sdf [-corner corner][-divider /|.][-include_typ][-digits digits][-gzip][-no_timestamp][-no_version]filename @@ -13606,7 +13628,7 @@ corner - Write delays for corner. + Write delays for corner. @@ -13628,7 +13650,7 @@ - -digits digits + -digits digits The number of digits after the decimal point to report. The default is 4. @@ -13639,7 +13661,7 @@ -gzip - Compress the SDF using gzip. + Compress the SDF using gzip. @@ -13663,79 +13685,79 @@ filename - The SDF filename to write. + The SDF filename to write. - Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. + Write the delay calculation delays for the design in SDF format to filename. If -corner is not specified the min/max delays are across all corners. With -corner the min/max delays for corner are written. The SDF TIMESCALE is same as the time_unit in the first liberty file read. - write_timing_model + write_timing_model - [-library_name lib_name][-cell_name cell_name] - [-corner corner]filename + [-library_name lib_name][-cell_name cell_name] + [-corner corner]filename - -library_name lib_name + -library_name lib_name - The name to use for the liberty library. Defaults to cell_name. + The name to use for the liberty library. Defaults to cell_name. - -cell_name cell_name + -cell_name cell_name - The name to use for the liberty cell. Defaults to the top level module name. + The name to use for the liberty cell. Defaults to the top level module name. - -corner corner + -corner corner - The process corner to use for extracting the model. + The process corner to use for extracting the model. - filename + filename - Filename for the liberty timing model. + Filename for the liberty timing model. - The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. - The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. - set_input_delayset_output_delayset_loadset_timing_derate - Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. + The write_timing_model command constructs a liberty timing model for the current design and writes it to filename. cell_name defaults to the cell name of the top level block in the design. + The SDC used to extract the block should include the clock definitions. If the block contains a clock network set_propagated_clock should be used so the clock delays are included in the timing model. The following SDC commands are ignored when building the timing model. + set_input_delayset_output_delayset_loadset_timing_derate + Using set_input_transition with the slew from the block context will be used will improve the match between the timing model and the block netlist. Paths defined on clocks that are defined on internal pins are ignored because the model has no way to include the clock definition. The resulting timing model can be used in a hierarchical timing flow as a replacement for the block to speed up timing analysis. This hierarchical timing methodology does not handle timing exceptions that originate or terminate inside the block. The timing model includes: - combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths - Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. + combinational paths between inputs and outputssetup and hold timing constraints on inputsclock to output timing paths + Resistance of long wires on inputs and outputs of the block cannot be modeled in Liberty. To reduce inaccuracies from wire resistance in technologies with resistive wires place buffers on inputs and ouputs. The extracted timing model setup/hold checks are scalar (no input slew dependence). Delay timing arcs are load dependent but do not include input slew dependency. - write_verilog + write_verilog - [-sort] - [-include_pwr_gnd][-remove_cells lib_cells]filename + [-sort] + [-include_pwr_gnd][-remove_cells lib_cells]filename - -sort + -sort Sort the instances in the netlist. @@ -13743,7 +13765,7 @@ - -include_pwr_gnd + -include_pwr_gnd Include power and ground pins on instances. @@ -13751,24 +13773,24 @@ - -remove_cells lib_cells + -remove_cells lib_cells - Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. + Liberty cells to remove from the Verilog netlist. Use get_lib_cells, a list of cells names, or a cell name with wildcards. - filename + filename - Filename for the liberty library. + Filename for the liberty library. - The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. - Filter Expressions - The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. + The write_verilog command writes a Verilog netlist to filename. Use -sort to sort the instances so the results are reproducible across operating systems. Use -remove_cells to remove instances of lib_cells from the netlist. + Filter Expressions + The get_cells, get_pins, get_ports and get_timing_edges functions support filtering the returned objects by property values. Supported filter expressions are shown below. @@ -13777,7 +13799,7 @@ property - Return objects with property value equal to 1. + Return objects with property value equal to 1. @@ -13785,62 +13807,62 @@ property==value - Return objects with property value equal to value. + Return objects with property value equal to value. - property=~pattern + property=~pattern - Return objects with property value that matches pattern. + Return objects with property value that matches pattern. - property!=value + property!=value - Return objects with property value not equal to value. + Return objects with property value not equal to value. - property!~value + property!~value - Return objects with property value that does not match pattern. + Return objects with property value that does not match pattern. - expr1&&expr2 + expr1&&expr2 - Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 and expr2. expr1 and expr2 are one of the first three property value forms shown above. - expr1||expr2 + expr1||expr2 - Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. + Return objects with expr1 or expr2. expr1 and expr2 are one of the first three property value forms shown above. - Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. - Variables + Where property is a property supported by the get_property command. Note that if there are spaces in the expression it must be enclosed in quotes so that it is a single argument. + Variables - hierarchy_separator + hierarchy_separator - Any character. + Any character. @@ -13850,7 +13872,7 @@ - sta_bidirect_net_paths_enabled + sta_bidirect_net_paths_enabled 0|1 @@ -13863,33 +13885,33 @@ - sta_continue_on_error + sta_continue_on_error 0|1 - The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. + The include and read_sdc commands stop and report any errors encountered while reading a file unless sta_continue_on_error is 1. The default value is 0. - sta_crpr_mode + sta_crpr_mode same_pin|same_transition - When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. + When the data and clock paths of a timing check overlap (see sta_crpr_enabled), pessimism is removed independent of whether of the path rise/fall transitions. When sta_crpr_mode is same_transition, the pessimism is only removed if the path rise/fall transitions are the same. The default value is same_pin. - sta_cond_default_arcs_enabled + sta_cond_default_arcs_enabled 0|1 @@ -13902,7 +13924,7 @@ - sta_crpr_enabled + sta_crpr_enabled 0|1 @@ -13915,7 +13937,7 @@ - sta_dynamic_loop_breaking + sta_dynamic_loop_breaking 0|1 @@ -13928,20 +13950,20 @@ - sta_gated_clock_checks_enabled + sta_gated_clock_checks_enabled 0|1 - When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. + When sta_gated_clock_checks_enabled is 1, clock gating setup and hold timing checks are checked. The default value is 1. - sta_input_port_default_clock + sta_input_port_default_clock 0|1 @@ -13954,7 +13976,7 @@ - sta_internal_bidirect_instance_paths_enabled + sta_internal_bidirect_instance_paths_enabled 0|1 @@ -13967,7 +13989,7 @@ - sta_pocv_enabled + sta_pocv_enabled 0|1 @@ -13980,14 +14002,14 @@ - sta_propagate_all_clocks + sta_propagate_all_clocks 0|1 - All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as + All clocks defined after sta_propagate_all_clocks is set to 1 are propagated. If it is set before any clocks are defined it has the same effect as set_propagated_clock [all_clocks] After all clocks have been defined. The default value is 0. @@ -13995,34 +14017,34 @@ - sta_propagate_gated_clock_enable + sta_propagate_gated_clock_enable 0|1 - When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. + When set to 1, paths of gated clock enables are propagated through the clock gating instances. If the gated clock controls sequential elements setting sta_propagate_gated_clock_enable to 0 prevents spurious paths from the clock enable. The default value is 1. - sta_recovery_removal_checks_enabled + sta_recovery_removal_checks_enabled 0|1 - When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. + When sta_recovery_removal_checks_enabled is 0, recovery and removal timing checks are disabled. The default value is 1. - sta_report_default_digits + sta_report_default_digits integer @@ -14035,7 +14057,7 @@ - sta_preset_clear_arcs_enabled + sta_preset_clear_arcs_enabled 0|1 @@ -14068,184 +14090,184 @@ - Alphabetical Index + Alphabetical Index - all_clocks6 - all_inputs6 - all_outputs6 - all_registers6 - check_setup7 - Command Line Arguments1 - Commands6 - connect_pin7 - create_generated_clock9 - create_voltage_area10 - current_design10 - current_instance10 - define_corners11 - delete_clock11 - delete_from_list11 - delete_generated_clock11 - delete_instance11 - delete_net12 - disconnect_pin12 - elapsed_run_time12 - Example Command Scripts1 - Filter Expressions80 - find_timing_paths13 - get_cells14 - get_clocks15 - get_fanin16 - get_fanout16 - get_full_name17 - get_lib_pins18 - get_libs18 - get_name20 - get_nets19 - get_pins20 - get_ports21 - get_property21 - get_timing_edges24 - group_path25 - hierarchy_separator80 - include26 - link_design26 - make_instance26 - make_net27 - Power Analysis2 - read_liberty27 - read_saif28 - read_sdc28 - read_sdf28 - read_spef29 - read_vcd31 - read_verilog31 - redirection4 - replace_activity_annotation31 - replace_cell31 - report_annotated_check32 - report_annotated_delay33 - report_check_types36 - report_checks34 - report_clock_latency37 - report_clock_min_period38 - report_clock_properties38 - report_clock_skew38 - report_dcalc39 - report_disabled_edges39 - report_edges39 - report_instance40 - report_lib_cell40 - report_net40 - report_parasitic_annotation40 - report_power41 - report_pulse_width_checks41 - report_slews42 - report_tns42 - report_units42 - report_wns43 - report_worst_slack43 - set_assigned_check43 - set_assigned_delay44 - set_assigned_transition45 - set_case_analysis46 - set_clock_gating_check46 - set_clock_groups47 - set_clock_latency47 - set_clock_transition48 - set_clock_uncertainty49 - set_cmd_units50 - set_data_check51 - set_disable_inferred_clock_gating51 - set_disable_timing51 - set_drive52 - set_driving_cell53 - set_false_path54 - set_fanout_load55 - set_hierarchy_separator55 - set_ideal_latency55 - set_ideal_network55 - set_ideal_transition55 - set_input_delay55 - set_input_transition57 - set_level_shifter_strategy57 - set_level_shifter_threshold57 - set_load57 - set_logic_dc58 - set_logic_one58 - set_logic_zero59 - set_max_area59 - set_max_capacitance59 - set_max_delay59 - set_max_dynamic_power60 - set_max_fanout60 - set_max_leakage_power60 - set_max_time_borrow60 - set_max_transition61 - set_min_capacitance61 - set_min_delay62 - set_min_pulse_width62 - set_multicycle_path63 - set_operating_conditions64 - set_output_delay65 - set_port_fanout_number66 - set_power_activity66 - set_propagated_clock67 - set_pvt67 - set_resistance69 - set_sense68 - set_timing_derate69 - set_units70 - set_wire_load_min_block_size71 - set_wire_load_mode71 - set_wire_load_model71 - set_wire_load_selection_group71 - SPEF30 - sta_bidirect_net_paths_enabled80 - sta_cond_default_arcs_enabled81 - sta_continue_on_error80 - sta_crpr_enabled81 - sta_crpr_mode81 - sta_dynamic_loop_breaking81 - sta_gated_clock_checks_enabled81 - sta_input_port_default_clock81 - sta_internal_bidirect_instance_paths_enabled81 - sta_pocv_enabled82 - sta_preset_clear_arcs_enabled82 - sta_propagate_all_clocks82 - sta_propagate_gated_clock_enable82 - sta_recovery_removal_checks_enabled82 - sta_report_default_digits82 - suppress_msg72 - TCL Interpreter3 - Timing Analysis using SDF2 - Timing Analysis with Multiple Process Corners2 - unset_case_analysis72 - unset_clock_latency72 - unset_clock_transition72 - unset_clock_uncertainty73 - unset_data_check73 - unset_disable_inferred_clock_gating74 - unset_disable_timing74 - unset_input_delay74 - unset_output_delay75 - unset_path_exceptions75 - unset_propagated_clock76 - unset_timing_derate76 - unsuppress_msg76 - user_run_time76 - Variables80 - verilog netlist31 - with_output_to_variable76 - write_path_spice77 - write_sdc77 - write_sdf78 - write_timing_model78 - write_verilog79 + all_clocks6 + all_inputs6 + all_outputs6 + all_registers6 + check_setup7 + Command Line Arguments1 + Commands6 + connect_pin7 + create_generated_clock9 + create_voltage_area10 + current_design10 + current_instance10 + define_corners11 + delete_clock11 + delete_from_list11 + delete_generated_clock11 + delete_instance11 + delete_net12 + disconnect_pin12 + elapsed_run_time12 + Example Command Scripts1 + Filter Expressions80 + find_timing_paths13 + get_cells14 + get_clocks15 + get_fanin16 + get_fanout16 + get_full_name17 + get_lib_pins18 + get_libs18 + get_name20 + get_nets19 + get_pins20 + get_ports21 + get_property21 + get_timing_edges24 + group_path25 + hierarchy_separator80 + include26 + link_design26 + make_instance26 + make_net27 + Power Analysis2 + read_liberty27 + read_saif28 + read_sdc28 + read_sdf28 + read_spef29 + read_vcd31 + read_verilog31 + redirection4 + replace_activity_annotation31 + replace_cell31 + report_annotated_check32 + report_annotated_delay33 + report_check_types36 + report_checks34 + report_clock_latency37 + report_clock_min_period38 + report_clock_properties38 + report_clock_skew38 + report_dcalc39 + report_disabled_edges39 + report_edges39 + report_instance40 + report_lib_cell40 + report_net40 + report_parasitic_annotation40 + report_power41 + report_pulse_width_checks41 + report_slews42 + report_tns42 + report_units42 + report_wns43 + report_worst_slack43 + set_assigned_check43 + set_assigned_delay44 + set_assigned_transition45 + set_case_analysis46 + set_clock_gating_check46 + set_clock_groups47 + set_clock_latency47 + set_clock_transition48 + set_clock_uncertainty49 + set_cmd_units50 + set_data_check51 + set_disable_inferred_clock_gating51 + set_disable_timing51 + set_drive52 + set_driving_cell53 + set_false_path54 + set_fanout_load55 + set_hierarchy_separator55 + set_ideal_latency55 + set_ideal_network55 + set_ideal_transition55 + set_input_delay55 + set_input_transition57 + set_level_shifter_strategy57 + set_level_shifter_threshold57 + set_load57 + set_logic_dc58 + set_logic_one58 + set_logic_zero59 + set_max_area59 + set_max_capacitance59 + set_max_delay59 + set_max_dynamic_power60 + set_max_fanout60 + set_max_leakage_power60 + set_max_time_borrow60 + set_max_transition61 + set_min_capacitance61 + set_min_delay62 + set_min_pulse_width62 + set_multicycle_path63 + set_operating_conditions64 + set_output_delay65 + set_port_fanout_number66 + set_power_activity66 + set_propagated_clock67 + set_pvt67 + set_resistance69 + set_sense68 + set_timing_derate69 + set_units70 + set_wire_load_min_block_size71 + set_wire_load_mode71 + set_wire_load_model71 + set_wire_load_selection_group71 + SPEF30 + sta_bidirect_net_paths_enabled80 + sta_cond_default_arcs_enabled81 + sta_continue_on_error80 + sta_crpr_enabled81 + sta_crpr_mode81 + sta_dynamic_loop_breaking81 + sta_gated_clock_checks_enabled81 + sta_input_port_default_clock81 + sta_internal_bidirect_instance_paths_enabled81 + sta_pocv_enabled82 + sta_preset_clear_arcs_enabled82 + sta_propagate_all_clocks82 + sta_propagate_gated_clock_enable82 + sta_recovery_removal_checks_enabled82 + sta_report_default_digits82 + suppress_msg72 + TCL Interpreter3 + Timing Analysis using SDF2 + Timing Analysis with Multiple Process Corners2 + unset_case_analysis72 + unset_clock_latency72 + unset_clock_transition72 + unset_clock_uncertainty73 + unset_data_check73 + unset_disable_inferred_clock_gating74 + unset_disable_timing74 + unset_input_delay74 + unset_output_delay75 + unset_path_exceptions75 + unset_propagated_clock76 + unset_timing_derate76 + unsuppress_msg76 + user_run_time76 + Variables80 + verilog netlist31 + with_output_to_variable76 + write_path_spice77 + write_sdc77 + write_sdf78 + write_timing_model78 + write_verilog79 - - Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. + + Version 2.6.0, Sep 23, 2024Copyright (c) 2024, Parallax Software, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. 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zAZ?))FPzZN`^lP^?uwT=4t<6D*tQktNs!-@bhSywDWn8Ub@ znkT`A7PK1yV?PU97;v70f@@8J386_So6(V=&}x#jqUi^$(O zbEghK=Z?oq=T3VAojbvvvP4hV$!VZpt496Nxudgn1c+}j9s65W)7YXWvdv=bGTQOa z`bvrc6_o=vhX}c`!1UM%FkINZ7?g0qhO)bFzZm#o4DDZ8ctGizz#N*)Tbk#$eh+4< zm%w=&0S~3tM4e&5;!iY8k$GrNT{VEMK8KN+qR+Jn&OjpBJu!z+`ZVK|1`SM+1uDHz zJ%-;)DG$KM=TH4U$k3Z!gtfYR!-CJE4730>&0b)&&cImwFh9IJk5OC#ng=ofa<=ov zX&a()oCQ`stiWirT9c$?aol(&#xpWq{zw*lx)4Ww46OWG8P~=1fpx2Zz-Zr4zehHC zU1}O@J|>Xb6Q_#Qux{_g$0_)zNqDqmjuW#vU}ZlBhPl0byGs^;!~*)9uodgF!q$>7 zR}%v(T`%LhZ6UDqmLI?UR#wO(%vEpzQzX;07X$2k^Peb@5+dmrTpDE9Y6n*ropPR@ z+4HPg4tn) zJvz*BE>jC>W8mrHV$4<22jh6Xona&ooiWQXeHL&h~ z6xdp8H1Gp}-D@!e@%D@alu3|p^8%4PSLAd|p&7a1gXE_UzsLLmPOmI{=F@Nd@ZWgz z(=WX8$_KvthkyFbmuL`w|AFuN z^ybHZ^e6x3kG=GPr>_$2y?y=3YmYvB^WhIafAW!Ngs+p4|Jtj!ucMW|@SzXA@ROf; d Date: Thu, 4 Sep 2025 01:45:33 +0200 Subject: [PATCH 2/3] search: fix truncating path ends list if sorting by slack (#291) --- search/PathGroup.cc | 2 - test/regression_vars.tcl | 1 + test/report_checks_sorted.ok | 87 +++++++++++++++++++++++++++++++++++ test/report_checks_sorted.tcl | 12 +++++ test/report_checks_sorted.v | 15 ++++++ 5 files changed, 115 insertions(+), 2 deletions(-) create mode 100644 test/report_checks_sorted.ok create mode 100644 test/report_checks_sorted.tcl create mode 100644 test/report_checks_sorted.v diff --git a/search/PathGroup.cc b/search/PathGroup.cc index 2a0f7961..7b24f642 100644 --- a/search/PathGroup.cc +++ b/search/PathGroup.cc @@ -546,8 +546,6 @@ PathGroups::makePathEnds(ExceptionTo *to, pushGroupPathEnds(path_ends); if (sort_by_slack) { sort(path_ends, PathEndLess(this)); - if (static_cast(path_ends.size()) > group_path_count_) - path_ends.resize(group_path_count_); } if (unconstrained_paths diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 9dcfd8f4..02bdadcd 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -156,6 +156,7 @@ record_sta_tests { report_json2 suppress_msg verilog_attribute + report_checks_sorted } define_test_group fast [group_tests all] diff --git a/test/report_checks_sorted.ok b/test/report_checks_sorted.ok new file mode 100644 index 00000000..7b983801 --- /dev/null +++ b/test/report_checks_sorted.ok @@ -0,0 +1,87 @@ +Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) +Endpoint: r4 (rising edge-triggered flip-flop clocked by clk) +Path Group: long +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + 64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R) + 17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R) + 17.88 100.42 ^ u3/Y (BUFx2_ASAP7_75t_R) + 16.66 117.08 ^ u4/Y (BUFx2_ASAP7_75t_R) + 0.00 117.08 ^ r4/D (DFFHQx4_ASAP7_75t_R) + 117.08 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r4/CLK (DFFHQx4_ASAP7_75t_R) + -12.61 487.39 library setup time + 487.39 data required time +--------------------------------------------------------- + 487.39 data required time + -117.08 data arrival time +--------------------------------------------------------- + 370.32 slack (MET) + + +Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) +Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) +Path Group: custom +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + 64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R) + 17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R) + 17.88 100.42 ^ u3/Y (BUFx2_ASAP7_75t_R) + 0.00 100.42 ^ r3/D (DFFHQx4_ASAP7_75t_R) + 100.42 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R) + -12.98 487.02 library setup time + 487.02 data required time +--------------------------------------------------------- + 487.02 data required time + -100.42 data arrival time +--------------------------------------------------------- + 386.60 slack (MET) + + +Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) +Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R) + 64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R) + 17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R) + 0.00 82.53 ^ r2/D (DFFHQx4_ASAP7_75t_R) + 82.53 data arrival time + + 500.00 500.00 clock clk (rise edge) + 0.00 500.00 clock network delay (ideal) + 0.00 500.00 clock reconvergence pessimism + 500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R) + -12.98 487.02 library setup time + 487.02 data required time +--------------------------------------------------------- + 487.02 data required time + -82.53 data arrival time +--------------------------------------------------------- + 404.48 slack (MET) + + diff --git a/test/report_checks_sorted.tcl b/test/report_checks_sorted.tcl new file mode 100644 index 00000000..8a1e595b --- /dev/null +++ b/test/report_checks_sorted.tcl @@ -0,0 +1,12 @@ +# report_checks with sorted path ends +read_liberty asap7_small.lib.gz +read_verilog report_checks_sorted.v +link_design top + +create_clock -name clk -period 500 {clk} +set_input_delay -clock clk 0 {in} + +group_path -name custom -to {r3} +group_path -name long -to {r4} + +report_checks -group_path_count 1 -sort_by_slack diff --git a/test/report_checks_sorted.v b/test/report_checks_sorted.v new file mode 100644 index 00000000..20f59112 --- /dev/null +++ b/test/report_checks_sorted.v @@ -0,0 +1,15 @@ +module top (input in, input clk, output out); + + wire w1, w2, w3, w4; + + DFFHQx4_ASAP7_75t_R r1 (.D(in), .CLK(clk), .Q(w1)); + + BUFx2_ASAP7_75t_R u2 (.A(w1), .Y(w2)); + BUFx2_ASAP7_75t_R u3 (.A(w2), .Y(w3)); + BUFx2_ASAP7_75t_R u4 (.A(w3), .Y(w4)); + + DFFHQx4_ASAP7_75t_R r2 (.D(w2), .CLK(clk), .Q(out)); + DFFHQx4_ASAP7_75t_R r3 (.D(w3), .CLK(clk), .Q(out)); + DFFHQx4_ASAP7_75t_R r4 (.D(w4), .CLK(clk), .Q(out)); + +endmodule From 774c3c68f11fa4df4bcc6b523058fe317bb9c983 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Thu, 4 Sep 2025 18:36:18 -0700 Subject: [PATCH 3/3] setVertexArrivals use tag_group_lock Signed-off-by: James Cherry --- include/sta/Search.hh | 1 - search/Search.cc | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/sta/Search.hh b/include/sta/Search.hh index 40ddc542..308542cc 100644 --- a/include/sta/Search.hh +++ b/include/sta/Search.hh @@ -647,7 +647,6 @@ protected: // Capacity of tag_groups_. TagGroupIndex tag_group_capacity_; std::mutex tag_group_lock_; - std::mutex tag_group_ref_count_lock_; // Latches data outputs to queue on the next search pass. VertexSet *pending_latch_outputs_; std::mutex pending_latch_outputs_lock_; diff --git a/search/Search.cc b/search/Search.cc index 2023daca..ab2a8901 100644 --- a/search/Search.cc +++ b/search/Search.cc @@ -2783,7 +2783,7 @@ Search::setVertexArrivals(Vertex *vertex, } } if (tag_group != prev_tag_group) { - LockGuard lock(tag_group_ref_count_lock_); + LockGuard lock(tag_group_lock_); tag_group->incrRefCount(); if (prev_tag_group) { prev_tag_group->decrRefCount();