From 424cb1dff1ec264b662c91f60a1fba9d13243eed Mon Sep 17 00:00:00 2001 From: Drew Lewis Date: Wed, 10 Jun 2026 12:12:19 -0400 Subject: [PATCH 1/2] Add native gzip compression support to write_verilog (#448) --- test/regression_vars.tcl | 1 + test/verilog_write_gzip.ok | 33 +++++++++++++++++++++++++++++++++ test/verilog_write_gzip.tcl | 8 ++++++++ verilog/VerilogWriter.cc | 12 +++++++----- 4 files changed, 49 insertions(+), 5 deletions(-) create mode 100644 test/verilog_write_gzip.ok create mode 100644 test/verilog_write_gzip.tcl diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index ce037eff..bf7e9faa 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -169,6 +169,7 @@ record_public_tests { verilog_well_supplies verilog_specify verilog_write_escape + verilog_write_gzip verilog_unconnected_hpin } diff --git a/test/verilog_write_gzip.ok b/test/verilog_write_gzip.ok new file mode 100644 index 00000000..bb976236 --- /dev/null +++ b/test/verilog_write_gzip.ok @@ -0,0 +1,33 @@ +module top (in1, + in2, + clk1, + clk2, + clk3, + out); + input in1; + input in2; + input clk1; + input clk2; + input clk3; + output out; + + wire r1q; + wire r2q; + wire u1z; + wire u2z; + + DFFHQx4_ASAP7_75t_R r1 (.Q(r1q), + .CLK(clk1), + .D(in1)); + DFFHQx4_ASAP7_75t_R r2 (.Q(r2q), + .CLK(clk2), + .D(in2)); + DFFHQx4_ASAP7_75t_R r3 (.Q(out), + .CLK(clk3), + .D(u2z)); + BUFx2_ASAP7_75t_R u1 (.Y(u1z), + .A(r2q)); + AND2x2_ASAP7_75t_R u2 (.Y(u2z), + .A(r1q), + .B(u1z)); +endmodule diff --git a/test/verilog_write_gzip.tcl b/test/verilog_write_gzip.tcl new file mode 100644 index 00000000..a2b442ef --- /dev/null +++ b/test/verilog_write_gzip.tcl @@ -0,0 +1,8 @@ +# Check that write_verilog supports gzip compression natively if .gz extension is provided. +source helpers.tcl +read_liberty asap7_small.lib.gz +read_verilog reg1_asap7.v +link_design top +set verilog_file [make_result_file "verilog_write_gzip.v.gz"] +write_verilog $verilog_file +report_file $verilog_file diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index c5d3fe7a..9f299122 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -33,6 +33,7 @@ #include "Error.hh" #include "Format.hh" #include "Liberty.hh" +#include "Zlib.hh" #include "Network.hh" #include "NetworkCmp.hh" #include "ParseBus.hh" @@ -47,7 +48,7 @@ public: VerilogWriter(const char *filename, bool include_pwr_gnd, CellSeq *remove_cells, - FILE *stream, + gzFile stream, Network *network); void writeModules(); @@ -82,7 +83,7 @@ protected: const char *filename_; bool include_pwr_gnd_; CellSet remove_cells_; - FILE *stream_; + gzFile stream_; Network *network_; int unconnected_net_index_{1}; }; @@ -94,12 +95,13 @@ writeVerilog(const char *filename, Network *network) { if (network->topInstance()) { - FILE *stream = fopen(filename, "w"); + bool gzip = std::string_view(filename).ends_with(".gz"); + gzFile stream = gzopen(filename, gzip ? "wb" : "wT"); if (stream) { VerilogWriter writer(filename, include_pwr_gnd, remove_cells, stream, network); writer.writeModules(); - fclose(stream); + gzclose(stream); } else throw FileNotWritable(filename); @@ -109,7 +111,7 @@ writeVerilog(const char *filename, VerilogWriter::VerilogWriter(const char *filename, bool include_pwr_gnd, CellSeq *remove_cells, - FILE *stream, + gzFile stream, Network *network) : filename_(filename), include_pwr_gnd_(include_pwr_gnd), From 4249ab7b98246180db361b340b43ccfe2053054a Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 10 Jun 2026 10:38:15 -0700 Subject: [PATCH 2/2] set sta_pocv_mode update delays/slews Signed-off-by: James Cherry --- graph/Graph.cc | 21 +++++---------------- include/sta/Graph.hh | 4 +--- search/Sta.cc | 8 +++++--- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/graph/Graph.cc b/graph/Graph.cc index 74996842..f19927ff 100644 --- a/graph/Graph.cc +++ b/graph/Graph.cc @@ -384,13 +384,6 @@ Graph::makeWireEdge(const Pin *from_pin, } } -void -Graph::makeSceneAfter() -{ - ap_count_ = dcalcAnalysisPtCount(); - initSlews(); -} - //////////////////////////////////////////////////////////////// Vertex * @@ -782,17 +775,13 @@ Graph::removeDelayAnnotated(Edge *edge) //////////////////////////////////////////////////////////////// -// This only gets called if the analysis type changes from single -// to bc_wc/ocv or visa versa. void -Graph::setDelayCount(DcalcAPIndex ap_count) +Graph::delayCountChanged() { - if (ap_count != ap_count_) { - // Discard any existing delays. - removePeriodCheckAnnotations(); - ap_count_ = ap_count; - initSlews(); - } + ap_count_ = dcalcAnalysisPtCount(); + // Discard any existing delays. + removePeriodCheckAnnotations(); + initSlews(); } void diff --git a/include/sta/Graph.hh b/include/sta/Graph.hh index a3553048..572d95a7 100644 --- a/include/sta/Graph.hh +++ b/include/sta/Graph.hh @@ -63,8 +63,7 @@ public: void makeGraph(); ~Graph() override; - // Number of arc delays and slews from sdf or delay calculation. - void setDelayCount(DcalcAPIndex ap_count); + void delayCountChanged(); size_t slewCount(); // Vertex functions. @@ -178,7 +177,6 @@ public: // Remove all delay and slew annotations. void removeDelaySlewAnnotations(); VertexSet ®ClkVertices() { return reg_clk_vertices_; } - void makeSceneAfter(); static constexpr int vertex_level_bits = 24; static constexpr int vertex_level_max = (1<deletePathGroups(); if (graph_) - graph_->setDelayCount(dcalcAnalysisPtCount()); + graph_->delayCountChanged(); } } @@ -2311,6 +2311,8 @@ Sta::setPocvMode(PocvMode mode) } updateComponentsState(); delaysInvalid(); + if (graph_) + graph_->delayCountChanged(); } } @@ -2554,7 +2556,7 @@ Sta::makeScenes(const StringSeq &scene_names) cmd_scene_ = scenes_[0]; updateComponentsState(); if (graph_) - graph_->makeSceneAfter(); + graph_->delayCountChanged(); } void @@ -2583,7 +2585,7 @@ Sta::makeScene(const std::string &name, Scene *scene = makeScene(name, mode, parasitics_min, parasitics_max); updateComponentsState(); if (graph_) - graph_->makeSceneAfter(); + graph_->delayCountChanged(); updateSceneLiberty(scene, liberty_min_files, liberty_max_files); cmd_scene_ = scene; }