diff --git a/test/test_write_verilog_escape.ok b/test/test_write_verilog_escape.ok
index 7c2442cb..4906a851 100644
--- a/test/test_write_verilog_escape.ok
+++ b/test/test_write_verilog_escape.ok
@@ -13,5 +13,6 @@ module hier_block (childclk,
  output [1:0] \Y[2:1] ;
 
 
+ BUFx2_ASAP7_75t_R \abuf_$100  (.A(childclk));
  BUFx2_ASAP7_75t_R \ff0/name  (.A(childclk));
 endmodule
diff --git a/test/test_write_verilog_escape.v b/test/test_write_verilog_escape.v
index 6340d9b8..e3abd466 100644
--- a/test/test_write_verilog_escape.v
+++ b/test/test_write_verilog_escape.v
@@ -9,6 +9,7 @@ module \hier_block (childclk, \Y[2:1] );
    input childclk; 
    output [1:0] \Y[2:1] ;
    wire [1:0] \Y[2:1] ;
+   BUFx2_ASAP7_75t_R \abuf_$100  (.A(childclk));
    BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
 endmodule // hier_block1