From 0d73b5b65a185329ea77478d4670d8a103b0b710 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Fri, 2 Oct 2020 08:38:14 -0700 Subject: [PATCH 1/2] GraphDelayCalc::findDelays(vertex) --- dcalc/GraphDelayCalc1.cc | 6 ++++++ dcalc/GraphDelayCalc1.hh | 1 + include/sta/GraphDelayCalc.hh | 2 ++ 3 files changed, 9 insertions(+) diff --git a/dcalc/GraphDelayCalc1.cc b/dcalc/GraphDelayCalc1.cc index 872b1a10..95f13931 100644 --- a/dcalc/GraphDelayCalc1.cc +++ b/dcalc/GraphDelayCalc1.cc @@ -828,6 +828,12 @@ GraphDelayCalc1::findInputArcDelay(LibertyCell *drvr_cell, } } +void +GraphDelayCalc1::findDelays(Vertex *drvr_vertex) +{ + findVertexDelay(drvr_vertex, arc_delay_calc_, true); +} + void GraphDelayCalc1::findVertexDelay(Vertex *vertex, ArcDelayCalc *arc_delay_calc, diff --git a/dcalc/GraphDelayCalc1.hh b/dcalc/GraphDelayCalc1.hh index ab25442a..b4b8bf79 100644 --- a/dcalc/GraphDelayCalc1.hh +++ b/dcalc/GraphDelayCalc1.hh @@ -43,6 +43,7 @@ public: virtual void deleteVertexBefore(Vertex *vertex); virtual void clear(); virtual void findDelays(Level level); + virtual void findDelays(Vertex *drvr_vertex); virtual string *reportDelayCalc(Edge *edge, TimingArc *arc, const Corner *corner, diff --git a/include/sta/GraphDelayCalc.hh b/include/sta/GraphDelayCalc.hh index d36ad3a5..235fc8de 100644 --- a/include/sta/GraphDelayCalc.hh +++ b/include/sta/GraphDelayCalc.hh @@ -47,6 +47,8 @@ public: virtual void copyState(const StaState *sta); // Find arc delays and vertex slews thru level. virtual void findDelays(Level /* level */) {}; + // Find and annotate drvr_vertex gate and load delays/slews. + virtual void findDelays(Vertex * /* drvr_vertex */) {}; // Invalidate all delays/slews. virtual void delaysInvalid() {}; // Invalidate vertex and downstream delays/slews. From fc279f0b3450e6fdd9a8b3c04ded79a130799fdd Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 19 Oct 2020 20:55:54 -0700 Subject: [PATCH 2/2] write_verilog -include_pwr_gnd --- include/sta/VerilogWriter.hh | 1 + verilog/Verilog.i | 3 ++- verilog/Verilog.tcl | 9 ++++++--- verilog/VerilogWriter.cc | 19 ++++++++++++++----- 4 files changed, 23 insertions(+), 9 deletions(-) diff --git a/include/sta/VerilogWriter.hh b/include/sta/VerilogWriter.hh index 163e5f38..c73c9ef9 100644 --- a/include/sta/VerilogWriter.hh +++ b/include/sta/VerilogWriter.hh @@ -28,6 +28,7 @@ class LibertyCell; void writeVerilog(const char *filename, bool sort, + bool include_pwr_gnd, vector *remove_cells, Network *network); diff --git a/verilog/Verilog.i b/verilog/Verilog.i index 2d740479..40802cec 100644 --- a/verilog/Verilog.i +++ b/verilog/Verilog.i @@ -52,13 +52,14 @@ delete_verilog_reader() void write_verilog_cmd(const char *filename, bool sort, + bool include_pwr_gnd, vector *remove_cells) { // This does NOT want the SDC (cmd) network because it wants // to see the sta internal names. Sta *sta = Sta::sta(); Network *network = sta->network(); - writeVerilog(filename, sort, remove_cells, network); + writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network); } %} // inline diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl index 59c5f0a8..7bbd2072 100644 --- a/verilog/Verilog.tcl +++ b/verilog/Verilog.tcl @@ -19,19 +19,22 @@ namespace eval sta { # Defined by SWIG interface Verilog.i. define_cmd_args "read_verilog" {filename} -define_cmd_args "write_verilog" {[-sort] [-remove_cells cells] filename} +define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\ + [-remove_cells cells] filename} proc write_verilog { args } { - parse_key_args "write_verilog" args keys {-remove_cells} flags {-sort} + parse_key_args "write_verilog" args keys {-remove_cells} \ + flags {-sort -include_pwr_gnd} set remove_cells {} if { [info exists keys(-remove_cells)] } { set remove_cells [sta::parse_libcell_arg $keys(-remove_cells)] } set sort [info exists flags(-sort)] + set include_pwr_gnd [info exists flags(-include_pwr_gnd)] check_argc_eq1 "write_verilog" $args set filename $args - write_verilog_cmd $filename $sort $remove_cells + write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells } # sta namespace end diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index 36ed2093..6af6d279 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -32,6 +32,7 @@ class VerilogWriter public: VerilogWriter(const char *filename, bool sort, + bool include_pwr_gnd_pins, vector *remove_cells, FILE *stream, Network *network); @@ -55,6 +56,7 @@ protected: const char *filename_; bool sort_; + bool include_pwr_gnd_; CellSet remove_cells_; FILE *stream_; Network *network_; @@ -67,13 +69,15 @@ protected: void writeVerilog(const char *filename, bool sort, + bool include_pwr_gnd_pins, vector *remove_cells, Network *network) { if (network->topInstance()) { FILE *stream = fopen(filename, "w"); if (stream) { - VerilogWriter writer(filename, sort, remove_cells, stream, network); + VerilogWriter writer(filename, sort, include_pwr_gnd_pins, + remove_cells, stream, network); writer.writeModule(network->topInstance()); fclose(stream); } @@ -84,11 +88,13 @@ writeVerilog(const char *filename, VerilogWriter::VerilogWriter(const char *filename, bool sort, + bool include_pwr_gnd_pins, vector *remove_cells, FILE *stream, Network *network) : filename_(filename), sort_(sort), + include_pwr_gnd_(include_pwr_gnd_pins), stream_(stream), network_(network), unconnected_net_index_(1) @@ -224,10 +230,13 @@ VerilogWriter::writeChild(Instance *child) CellPortIterator *port_iter = network_->portIterator(child_cell); while (port_iter->hasNext()) { Port *port = port_iter->next(); - if (network_->hasMembers(port)) - writeInstBusPin(child, port, first_port); - else - writeInstPin(child, port, first_port); + if (include_pwr_gnd_ + || !network_->direction(port)->isPowerGround()) { + if (network_->hasMembers(port)) + writeInstBusPin(child, port, first_port); + else + writeInstPin(child, port, first_port); + } } delete port_iter; fprintf(stream_, ");\n");