diff --git a/parasitics/Parasitics.tcl b/parasitics/Parasitics.tcl index 1a6b8160..8a9b52a1 100644 --- a/parasitics/Parasitics.tcl +++ b/parasitics/Parasitics.tcl @@ -66,7 +66,7 @@ proc_redirect read_spef { set delete_after_reduce [info exists flags(-delete_after_reduce)] set quiet [info exists flags(-quiet)] set save [info exists flags(-save)] - set filename $args + set filename [file nativename [lindex $args 0]] return [read_spef_cmd $filename $instance $min_max $increment \ $pin_cap_included $keep_coupling_caps $coupling_reduction_factor \ $reduce_to $delete_after_reduce $quiet] diff --git a/sdf/Sdf.tcl b/sdf/Sdf.tcl index 865005a1..19415606 100644 --- a/sdf/Sdf.tcl +++ b/sdf/Sdf.tcl @@ -30,7 +30,7 @@ proc_redirect read_sdf { keys {-path -corner -analysis_type -type -min_type -max_type -cond_use} \ flags {-unescaped_dividers -incremental_only} check_argc_eq1 "read_sdf" $args - set filename $args + set filename [file nativename [lindex $args 0]] set path "" if [info exists keys(-path)] { set path $keys(-path) @@ -202,7 +202,7 @@ proc_redirect write_sdf { flags {-gzip -no_timestamp -no_version} check_argc_eq1 "write_sdf" $args set corner [parse_corner keys] - set filename $args + set filename [file nativename [lindex $args 0]] set divider "/" if [info exists keys(-divider)] { set divider $keys(-divider) diff --git a/tcl/Cmds.tcl b/tcl/Cmds.tcl index 957f5f8b..ca9819c7 100644 --- a/tcl/Cmds.tcl +++ b/tcl/Cmds.tcl @@ -1973,7 +1973,7 @@ proc write_path_spice { args } { flags {} if { [info exists keys(-spice_directory)] } { - set spice_dir [file_expand_tilde $keys(-spice_directory)] + set spice_dir [file nativename $keys(-spice_directory)] if { ![file exists $spice_dir] } { sta_error 496 "Directory $spice_dir not found." } @@ -1988,7 +1988,7 @@ proc write_path_spice { args } { } if { [info exists keys(-lib_subckt_file)] } { - set lib_subckt_file [file_expand_tilde $keys(-lib_subckt_file)] + set lib_subckt_file [file nativename $keys(-lib_subckt_file)] if { ![file readable $lib_subckt_file] } { sta_error 500 "-lib_subckt_file $lib_subckt_file is not readable." } @@ -1997,7 +1997,7 @@ proc write_path_spice { args } { } if { [info exists keys(-model_file)] } { - set model_file [file_expand_tilde $keys(-model_file)] + set model_file [file nativename $keys(-model_file)] if { ![file readable $model_file] } { sta_error 502 "-model_file $model_file is not readable." } @@ -2038,15 +2038,5 @@ proc write_path_spice { args } { } } -proc file_expand_tilde { filename } { - global env - - if { [string range $filename 0 1] == "~/" } { - return [file join $env(HOME) [string range $filename 2 end]] - } else { - return $filename - } -} - # sta namespace end. } diff --git a/tcl/Liberty.tcl b/tcl/Liberty.tcl index ee320f45..f18d3404 100644 --- a/tcl/Liberty.tcl +++ b/tcl/Liberty.tcl @@ -26,7 +26,7 @@ proc_redirect read_liberty { flags {-min -max -no_latch_infer} check_argc_eq1 "read_liberty" $args - set filename [file nativename $args] + set filename [file nativename [lindex $args 0]] set corner [parse_corner keys] set min_max [parse_min_max_all_flags flags] set infer_latches [expr ![info exists flags(-no_latch_infer)]] diff --git a/tcl/Sdc.tcl b/tcl/Sdc.tcl index 6dfe7a5b..ce3caadc 100644 --- a/tcl/Sdc.tcl +++ b/tcl/Sdc.tcl @@ -33,7 +33,7 @@ proc_redirect read_sdc { check_argc_eq1 "read_sdc" $args set echo [info exists flags(-echo)] - set filename [lindex $args 0] + set filename [file nativename [lindex $args 0]] source_ $filename $echo 0 } @@ -52,7 +52,7 @@ proc_redirect source { } set echo [info exists flags(-echo)] set verbose [info exists flags(-verbose)] - set filename [lindex $args 0] + set filename [file nativename [lindex $args 0]] source_ $filename $echo $verbose } diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl index 7bbd2072..63763b37 100644 --- a/verilog/Verilog.tcl +++ b/verilog/Verilog.tcl @@ -33,7 +33,7 @@ proc write_verilog { args } { set sort [info exists flags(-sort)] set include_pwr_gnd [info exists flags(-include_pwr_gnd)] check_argc_eq1 "write_verilog" $args - set filename $args + set filename [file nativename [lindex $args 0]] write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells }