[get_cells]
r1
r2
r3
u1
u2
[get_clocks]
clk
vclk
[get_lib_cells]
asap7_small/AND2x2_ASAP7_75t_R
asap7_small/BUFx2_ASAP7_75t_R
asap7_small/DFFHQx4_ASAP7_75t_R
[get_lib_pins]
A
A
B
CLK
D
IQ
IQN
Q
Y
Y
[get_libs]
asap7_small
[get_nets]
clk1
clk2
clk3
in1
in2
out
r1q
r2q
u1z
u2z
[get_pins]
r1/CLK
r1/D
r1/IQ
r1/IQN
r1/Q
r2/CLK
r2/D
r2/IQ
r2/IQN
r2/Q
r3/CLK
r3/D
r3/IQ
r3/IQN
r3/Q
u1/A
u1/Y
u2/A
u2/B
u2/Y
[get_ports]
clk1
clk2
clk3
in1
in2
out
