mirror of https://github.com/VLSIDA/OpenRAM.git
242 lines
15 KiB
Plaintext
242 lines
15 KiB
Plaintext
[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /home/jesse/output/
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[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/example_config_scn4m_subm.py
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[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
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[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
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[globals/init_paths]: Creating temp directory: /home/jesse/output/
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[verify/<module>]: Initializing verify...
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[verify/<module>]: Finding DRC/LVS/PEX tools.
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[globals/get_tool]: Using DRC: /usr/local/bin/magic
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[globals/get_tool]: Using LVS: /usr/local/bin/netgen
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[globals/get_tool]: Using PEX: /usr/local/bin/magic
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[globals/setup_bitcell]: Using bitcell: bitcell
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[characterizer/<module>]: Initializing characterizer...
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[characterizer/<module>]: Finding spice simulator.
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[globals/get_tool]: Could not find hspice, trying next spice tool.
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[globals/get_tool]: Using spice: /usr/local/bin/ngspice
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|==============================================================================|
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|========= OpenRAM v1.1.2 =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= Computer Science and Engineering Department =========|
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|========= University of California Santa Cruz =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /home/jesse/output/ =========|
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|========= See LICENSE for license info =========|
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|==============================================================================|
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** Start: 04/23/2020 00:06:42
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Technology: scn4m_subm
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Total size: 32 bits
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Word size: 2
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Words: 16
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Banks: 1
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Write size: None
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RW ports: 1
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R-only ports: 0
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W-only ports: 0
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DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
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Performing simulation-based characterization with ngspice
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[sram_config/recompute_sizes]: Recomputing with words per row: 1
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[sram_config/recompute_sizes]: Rows: 16 Cols: 2
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[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
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Words per row: 1
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Output files are:
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.sp
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.v
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lib
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.py
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.html
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.log
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lef
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/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.gds
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[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
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[dff_array/__init__]: Creating data_dff rows=1 cols=2
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[precharge_array/__init__]: Creating precharge_array_0
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[sense_amp_array/__init__]: Creating sense_amp_array_0
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[write_driver_array/__init__]: Creating write_driver_array_0
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[wordline_driver/__init__]: Creating wordline_driver_0
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[pdriver/__init__]: creating pdriver pdriver_0
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[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 16 x 2
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[bitcell_array/__init__]: Creating bitcell_array_0 16 x 2
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[dummy_array/__init__]: Creating dummy_array_0 1 x 2
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[dummy_array/__init__]: Creating dummy_array_1 19 x 1
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[control_logic/__init__]: Creating control_logic_rw
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[dff_buf/__init__]: Creating dff_buf
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[dff_buf_array/__init__]: Creating dff_buf_array_0
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[dff_buf/__init__]: Creating dff_buf_0
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[pand2/__init__]: Creating pnand2 pand2_0
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[pdriver/__init__]: creating pdriver pdriver_1
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[pbuf/__init__]: creating pbuf_0 with size of 2
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[pdriver/__init__]: creating pdriver pdriver_2
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[pdriver/__init__]: creating pdriver pdriver_3
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[pand3/__init__]: Creating pand3 pand3_0
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[pand3/__init__]: Creating pand3 pand3_1
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[pdriver/__init__]: creating pdriver pdriver_4
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[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
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** Submodules: 0.4 seconds
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** Placement: 0.0 seconds
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[router_tech/__init__]: Track width: 2.400
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[router_tech/__init__]: Track space: 1.200
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[router_tech/__init__]: Track wire width: 1.200
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[supply_grid_router/route]: Running supply router on vdd and gnd...
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[supply_grid_router/create_routing_grid]: Size: 227.0 x 371.80000000000007
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**** Retrieving pins: 0.0 seconds
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**** Analyzing pins: 0.7 seconds
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[router/find_blockages]: Finding blockages.
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**** Finding blockages: 0.1 seconds
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[router/convert_blockages]: Converting blockages.
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**** Converting blockages: 0.0 seconds
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[router/convert_pins]: Converting pins for vdd.
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[router/convert_pins]: Converting pins for gnd.
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**** Converting pins: 0.5 seconds
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[router/separate_adjacent_pin]: Comparing vdd and gnd adjacency
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[router/separate_adjacent_pin]: Removed 0 adjacent grids.
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**** Separating adjacent pins: 0.1 seconds
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[router/enclose_pins]: Enclosing pins for vdd
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[router/enclose_pins]: Enclosing pins for gnd
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**** Enclosing pins: 0.2 seconds
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*** Finding pins and blockages: 1.4 seconds
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[supply_grid_router/route_supply_rails]: Routing supply rail gnd.
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[supply_grid_router/route_supply_rails]: Routing supply rail vdd.
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*** Routing supply rails: 1.1 seconds
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[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for vdd
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[supply_grid_router/route_simple_overlaps]: Routed 96 simple overlap pins
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[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for gnd
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[supply_grid_router/route_simple_overlaps]: Routed 172 simple overlap pins
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*** Simple overlap routing: 0.0 seconds
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[supply_grid_router/route_pins_to_rails]: Maze routing vdd with 11 pin components to connect.
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[7, 72, 0]], [v3d[7, 72, 1]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[7, 54, 0]], [v3d[7, 54, 1]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[14, 63, 0]], [v3d[14, 64, 0]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[14, 55, 0]], [v3d[14, 56, 0]]]
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[router/run_router]: Found path: cost=1
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[router/run_router]: [[v3d[14, 80, 0]], [v3d[13, 80, 0]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[14, 71, 0]], [v3d[14, 70, 0]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[41, 123, 0]], [v3d[41, 123, 1]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[45, 123, 0]], [v3d[45, 123, 1]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[47, 123, 0]], [v3d[47, 123, 1]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[51, 123, 0]], [v3d[51, 123, 1]]]
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[router/run_router]: Found path: cost=2
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[router/run_router]: [[v3d[53, 123, 0]], [v3d[53, 123, 1]]]
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[supply_grid_router/route_pins_to_rails]: Maze routing gnd with 5 pin components to connect.
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[-6, 124, 0]], [v3d[-6, 123, 0]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[6, 58, 0]], [v3d[6, 57, 0]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[14, 68, 0]], [v3d[14, 69, 0]]]
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[router/run_router]: Found path: cost=4
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[router/run_router]: [[v3d[14, 58, 0]], [v3d[14, 57, 0]]]
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[router/run_router]: Found path: cost=1
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[router/run_router]: [[v3d[14, 85, 0]], [v3d[13, 85, 0]]]
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*** Maze routing supplies: 2.9 seconds
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** Routing: 7.6 seconds
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[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm 0
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[verify.magic/run_lvs]: sram_2_16_scn4m_subm LVS matches
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** Verification: 6.6 seconds
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** SRAM creation: 14.7 seconds
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LEF: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lef
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** LEF: 0.6 seconds
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GDS: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.gds
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** GDS: 0.2 seconds
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SP: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.sp
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** Spice writing: 0.0 seconds
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** Extraction: 5.6 seconds
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LIB: Characterizing...
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[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 78.5936 ]
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[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05 0.4 ]
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[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
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[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
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[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 10.0ns on Port 0
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[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns
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[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 5.0ns (ub: 10.0 lb: 0.0)
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[characterizer.delay/check_bit_measures]: Wrong value detected on probe bit during read/write cycle. Check writes and control logic for bugs.
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measure=v_qbar_a1111_b1_WRITE_ZERO, op=WRITE_ZERO, bit_storage=INVERTING, V(bit)=0.6127083
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[characterizer.delay/check_read_debug_measures]: Debug measurement failed. Value 4.987059V was read on read 0 cycle.
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[characterizer.delay/check_bitline_meas]: min_dicharge=False, min_diff=False
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[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 7.5ns (ub: 10.0 lb: 5.0)
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[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 8.75ns (ub: 10.0 lb: 7.5)
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[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 9.375ns (ub: 10.0 lb: 8.75)
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[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 9.0625ns (ub: 9.375 lb: 8.75)
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[characterizer.delay/analyze]: Min Period Found: 9.0625ns
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[characterizer.delay/run_power_simulation]: Performing leakage power simulations.
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[characterizer.delay/run_power_simulation]: Leakage power of full array is 0.4069451 mW
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[characterizer.delay/run_power_simulation]: Leakage power of trimmed array is 0.4069451 mW
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=2.45605
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=9.8242
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=78.5936
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=2.45605
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=9.8242
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=78.5936
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=2.45605
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=9.8242
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[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=78.5936
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[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2001953
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.1879883
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2368164
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.24902339999999998
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.2148437
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.08056640999999999
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[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2001953
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.1879883
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2368164
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.24902339999999998
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.2148437
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.08056640999999999
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[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2001953
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.1879883
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.1757812
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.11718749999999999
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.09277344
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[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
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[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.2368164
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[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.24902339999999998
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[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.2148437
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[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.08056640999999999
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** Characterization: 1028.4 seconds
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Config: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.py
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** Config: 0.0 seconds
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Datasheet: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.html
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** Datasheet: 0.0 seconds
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Verilog: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.v
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** Verilog: 0.0 seconds
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[globals/cleanup_paths]: Preserving temp directory: /home/jesse/output/
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[verify.magic/print_drc_stats]: DRC runs: 1
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[verify.magic/print_lvs_stats]: LVS runs: 1
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[verify.magic/print_pex_stats]: PEX runs: 1
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** End: 1049.5 seconds
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