mirror of https://github.com/VLSIDA/OpenRAM.git
279 lines
8.3 KiB
XML
279 lines
8.3 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<klayout-macro>
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<description/>
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<version/>
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<category>lvs</category>
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<prolog/>
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<epilog/>
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<doc/>
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<autorun>false</autorun>
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<autorun-early>false</autorun-early>
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<shortcut/>
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<show-in-menu>true</show-in-menu>
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<group-name>lvs_scripts</group-name>
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<menu-path>tools_menu.lvs.end</menu-path>
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<interpreter>dsl</interpreter>
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<dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
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<text>#
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tstart = Time.now
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# Extraction for SKY130
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#
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############################
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# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=my_report.lyrdb -rd schematic=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r lvs_sky130.lvs
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if $input
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source($input)
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end
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if $report
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report_lvs($report)
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else
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report_lvs("lvs_report.lvsdb")
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end
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if $schematic
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#reference netlist
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schematic($schematic)
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else
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schematic(RBA::CellView::active.filename.sub(/\.(oas|gds|oas.gz|gds.gz)$/, ".sp"))
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end
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# true: use net names instead of numbers
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# false: use numbers for nets
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spice_with_net_names = true
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# true: put in comments with details
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# false: no comments
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spice_with_comments = true
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if $target_netlist
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target_netlist($target_netlist)
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else
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target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments), "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
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end
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# klayout setup
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########################
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# Hierarchical mode
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deep
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# Use 4 CPU cores
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threads(4)
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# Print details
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verbose(true)
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# layers definitions
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########################
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# LVS section
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########################
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info("LVS section")
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# layers definitions
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########################
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BOUND = polygons(235, 4)
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DNWELL = polygons(64, 18)
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PWRES = polygons(64, 13)
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NWELL = polygons(64, 20)
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NWELLTXT = input(64, 5)
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NWELLPIN = polygons(64, 16)
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SUBTXT = input(122, 5)
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SUBPIN = input(64, 59)
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DIFF = polygons(65, 20)
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TAP = polygons(65, 44)
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PSDM = polygons(94, 20)
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NSDM = polygons(93, 44)
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LVTN = polygons(125, 44)
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HVTR = polygons(18, 20)
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HVTP = polygons(78, 44)
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SONOS = polygons(80, 20)
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COREID = polygons(81, 2)
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STDCELL = polygons(81, 4)
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NPNID = polygons(82, 20)
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PNPID = polygons(82, 44)
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RPM = polygons(86, 20)
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URPM = polygons(79, 20)
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LDNTM = polygons(11, 44)
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HVNTM = polygons(125, 20)
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POLY = polygons(66, 20)
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POLYTXT = input(66, 5)
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POLYPIN = polygons(66, 16)
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HVI = polygons(75, 20)
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LICON = polygons(66, 44)
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NPC = polygons(95, 20)
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DIFFRES = polygons(65, 13)
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POLYRES = polygons(66, 13)
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POLYSHO = polygons(66, 15)
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DIODE = polygons(81, 23)
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LI = polygons(67, 20)
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LITXT = input(67, 5)
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LIPIN = polygons(67, 16)
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LIRES = polygons(67, 13)
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MCON = polygons(67, 44)
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MET1 = polygons(68, 20)
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MET1TXT = input(68, 5)
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MET1PIN = polygons(68, 16)
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MET1RES = polygons(68, 13)
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VIA1 = polygons(68, 44)
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MET2 = polygons(69, 20)
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MET2TXT = input(69, 5)
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MET2PIN = polygons(69, 16)
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MET2RES = polygons(69, 13)
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VIA2 = polygons(69, 44)
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MET3 = polygons(70, 20)
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MET3TXT = input(70, 5)
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MET3PIN = polygons(70, 16)
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MET3RES = polygons(70, 13)
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VIA3 = polygons(70, 44)
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MET4 = polygons(71, 20)
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MET4TXT = input(71, 5)
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MET4PIN = polygons(71, 16)
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MET4RES = polygons(71, 13)
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VIA4 = polygons(71, 44)
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MET5 = polygons(72, 20)
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MET5TXT = input(72, 5)
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MET5PIN = polygons(72, 16)
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MET5RES = polygons(72, 13)
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RDL = polygons(74, 20)
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RDLTXT = input(74, 5)
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RDLPIN = polygons(74, 16)
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GLASS = polygons(76, 20)
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CAPM = polygons(89, 44)
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CAPM2 = polygons(97, 44)
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LOWTAPD = polygons(81, 14)
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FILLOBSM1 = polygons(62, 24)
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FILLOBSM2 = polygons(105, 52)
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FILLOBSM3 = polygons(107, 24)
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FILLOBSM4 = polygons(112, 4)
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NCM = polygons(92, 44)
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# Bulk layer for terminal provisioning
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SUB = polygons(236, 0)
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# SUB = polygon_layer
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# Computed layers
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PDIFF = DIFF & NWELL & PSDM
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NTAP = TAP & NWELL & NSDM
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PGATE = PDIFF & POLY
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PSD = PDIFF - PGATE
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CORE_PGATE = PGATE & COREID
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STD_PGATE = PGATE - HVTP - NCM - HVI - COREID
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HVT_PGATE = PGATE & HVTP - NCM - HVI
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HV5_PGATE = PGATE - HVTP - NCM & HVI
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NDIFF = DIFF - NWELL & NSDM
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PTAP = TAP - NWELL & PSDM
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NGATE = NDIFF & POLY
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NSD = NDIFF - NGATE
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CORE_NGATE = NGATE & COREID
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STD_NGATE = NGATE - NCM - LVTN - HVI
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LVT_NGATE = NGATE - NCM & LVTN - HVI
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HV5_NGATE = NGATE - NCM - LVTN & HVI
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HV5NA_NGATE = NGATE - NCM & LVTN & HVI
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# drawing to physical
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device_scaling(1000000)
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# PMOS transistor device extraction
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extract_devices(mos4("sky130_fd_pr__special_pfet_latch"), { "SD" => PSD, "G" => CORE_PGATE, "tS" => PSD, "tD" => PSD, "tG" => POLY, "W" => NWELL })
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extract_devices(mos4("sky130_fd_pr__pfet_01v8"), { "SD" => PSD, "G" => STD_PGATE, "tS" => PSD, "tD" => PSD, "tG" => POLY, "W" => NWELL })
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extract_devices(mos4("sky130_fd_pr__pfet_01v8_hvt"), { "SD" => PSD, "G" => HVT_PGATE, "tS" => PSD, "tD" => PSD, "tG" => POLY, "W" => NWELL })
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extract_devices(mos4("sky130_fd_pr__pfet_g5v0d10v5"), { "SD" => PSD, "G" => HV5_PGATE, "tS" => PSD, "tD" => PSD, "tG" => POLY, "W" => NWELL })
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# NMOS transistor device extraction
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extract_devices(mos4("sky130_fd_pr__special_nfet_latch"), { "SD" => NSD, "G" => CORE_NGATE, "tS" => NSD, "tD" => NSD, "tG" => POLY, "W" => SUB })
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extract_devices(mos4("sky130_fd_pr__nfet_01v8"), { "SD" => NSD, "G" => STD_NGATE, "tS" => NSD, "tD" => NSD, "tG" => POLY, "W" => SUB })
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extract_devices(mos4("sky130_fd_pr__nfet_01v8_lvt"), { "SD" => NSD, "G" => LVT_NGATE, "tS" => NSD, "tD" => NSD, "tG" => POLY, "W" => SUB })
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extract_devices(mos4("sky130_fd_pr__nfet_g5v0d10v5"), { "SD" => NSD, "G" => HV5_NGATE, "tS" => NSD, "tD" => NSD, "tG" => POLY, "W" => SUB })
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extract_devices(mos4("sky130_fd_pr__nfet_01v8_nvt"), { "SD" => NSD, "G" => HV5NA_NGATE, "tS" => NSD, "tD" => NSD, "tG" => POLY, "W" => SUB })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(SUB, PTAP)
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connect(NWELL, NTAP)
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connect(LICON, PTAP)
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connect(LICON, NTAP)
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connect(PSD, LICON)
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connect(NSD, LICON)
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connect(POLY, LICON)
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connect(LICON, LI)
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connect(LI, MCON)
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connect(MCON, MET1)
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connect(MET1,VIA1)
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connect(VIA1, MET2)
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connect(MET2, VIA2)
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connect(VIA2, MET3)
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connect(MET3, VIA3)
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connect(VIA3, MET4)
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connect(MET4, VIA4)
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connect(VIA4, MET5)
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# Attaching labels
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connect(SUB, SUBTXT)
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connect(SUB, SUBPIN)
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connect(NWELL, NWELLTXT)
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connect(POLY, POLYTXT)
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connect(LI, LITXT)
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connect(MET1, MET1TXT)
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connect(MET2, MET2TXT)
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connect(MET3, MET3TXT)
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connect(MET4, MET4TXT)
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connect(MET5, MET5TXT)
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# Global
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connect_global(SUB, "gnd")
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if $connect_supplies
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connect_implicit("*", "vdd")
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connect_implicit("*", "gnd")
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end
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#connect_global(pwell, "PWELL")
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#connect_global(nwell, "NWELL")
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#connect_global(bulk, "BULK")
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# Actually performs the extraction
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netlist # ... not really required
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# Flatten cells which are present in one netlist only
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align
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# SIMPLIFICATION of the netlist
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#netlist.make_top_level_pins
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#netlist.combine_devices
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#netlist.purge
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#netlist.purge_nets
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netlist.simplify
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#schematic.simplify
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# Tolerances for the devices extracted parameters
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# tolerance(device_class_name, parameter_name [, :absolute => absolute_tolerance] [, :relative => relative_tolerance])
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tolerance("pfet_01v8", "W", :absolute => 1.nm, :relative => 0.001)
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tolerance("pfet_01v8", "L", :absolute => 1.nm, :relative => 0.001)
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tolerance("pfet_01v8_hvt", "W", :absolute => 1.nm, :relative => 0.001)
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tolerance("pfet_01v8_hvt", "L", :absolute => 1.nm, :relative => 0.001)
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tolerance("nfet_01v8", "W", :absolute => 1.nm, :relative => 0.001)
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tolerance("nfet_01v8", "L", :absolute => 1.nm, :relative => 0.001)
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tolerance("nfet_01v8_lvt", "W", :absolute => 1.nm, :relative => 0.001)
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tolerance("nfet_01v8_lvt", "L", :absolute => 1.nm, :relative => 0.001)
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#max_res(1000000)
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#min_caps(1e-15)
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max_branch_complexity(65536)
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max_depth(16)
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if ! compare
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#raise "ERROR : Netlists don't match"
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puts "ERROR : Netlists don't match"
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else
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puts "CONGRATULATIONS! Netlists match."
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end
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# time spent for the LVS
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time = Time.now
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hours = ((time - tstart)/3600).to_i
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minutes = ((time - tstart)/60 - hours * 60).to_i
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seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i
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$stdout.write "LVS finished at : #{time.hour}:#{time.min}:#{time.sec} - LVS duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n"</text>
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</klayout-macro>
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