mirror of https://github.com/VLSIDA/OpenRAM.git
27 lines
1.1 KiB
Plaintext
27 lines
1.1 KiB
Plaintext
[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Temporary files saved in /home/jesse/output/
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[globals/read_config]: Configuration file is /home/jesse/openram/compiler/tests/configs/config.py
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[globals/read_config]: Output saved in /home/jesse/openram/./
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[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
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[globals/init_paths]: Creating temp directory: /home/jesse/output/
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[characterizer/<module>]: Initializing characterizer...
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[characterizer/<module>]: Analytical model enabled.
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[verify/<module>]: Initializing verify...
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[verify/<module>]: Finding DRC/LVS/PEX tools.
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[globals/get_tool]: Using DRC: /usr/local/bin/magic
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[globals/get_tool]: Using LVS: /usr/local/bin/netgen
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[globals/get_tool]: Using PEX: /usr/local/bin/magic
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[globals/get_tool]: Using GDS: /usr/local/bin/magic
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[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4
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[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4
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[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4
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ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
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Inst (4) -> Mod (6)
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bl_0_0 -> bl0
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br_0_0 -> bl1
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vdd -> wl0
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gnd -> wl1
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-> vpwr
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-> vgnd
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