mirror of https://github.com/VLSIDA/OpenRAM.git
59 lines
2.2 KiB
Python
59 lines
2.2 KiB
Python
from template import template
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from globals import OPTS
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<<<<<<< HEAD
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import os
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from math import ceil, log
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=======
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>>>>>>> 3dd65b1a (modified template engine & sram multibank class)
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class sram_multibank:
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def __init__(self, sram):
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<<<<<<< HEAD
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rw_ports = [i for i in sram.all_ports if i in sram.read_ports and i in sram.write_ports]
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r_ports = [i for i in sram.all_ports if i in sram.read_ports and i not in sram.write_ports]
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w_ports = [i for i in sram.all_ports if i not in sram.read_ports and i in sram.write_ports]
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self.dict = {
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'module_name': OPTS.output_name,
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'bank_module_name': OPTS.output_name + '_1bank',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'ports': sram.all_ports,
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'rw_ports': rw_ports,
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'r_ports': r_ports,
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'w_ports': w_ports,
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'banks': list(range(sram.num_banks)),
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'data_width': sram.word_size,
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'addr_width': sram.bank_addr_size + ceil(log(sram.num_banks, 2)),
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'bank_sel': ceil(log(sram.num_banks, 2)),
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'num_wmask': sram.num_wmasks
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}
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def verilog_write(self, name):
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template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v")
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t = template(template_filename, self.dict)
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t.write(name)
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=======
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dict = {
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'module_name': OPTS.output_name,
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'bank_module_name': OPTS.output_name + '_1bank',
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'vdd': 'vdd',
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'gnd': 'gnd',
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'ports': sram.all_ports,
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'rw_ports': sram.readwrite_ports,
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'r_ports': sram.read_ports,
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'w_ports': sram.write_ports,
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'banks': sram.banks,
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'data_width': sram.word_size,
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'addr_width': sram.addr_size,
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'bank_sel': list(range(sram.num_banks)),
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'num_wmask': sram.num_wmasks
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}
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def verilog_write():
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t = template('../sram/sram_multibank_template.v', dict)
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t.write(OPTS.output_name + '.v')
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>>>>>>> 3dd65b1a (modified template engine & sram multibank class)
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