[globals/init_openram]: Initializing OpenRAM... [globals/setup_paths]: Temporary files saved in /home/jesse/output/ [globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run1.py [globals/read_config]: Output saved in /home/jesse/openram/compiler/./ [globals/import_tech]: Adding technology path: /home/jesse/openram/technology [globals/init_paths]: Creating temp directory: /home/jesse/output/ [verify/]: Initializing verify... [verify/]: Finding DRC/LVS/PEX tools. [globals/get_tool]: Using DRC: /usr/local/bin/magic [globals/get_tool]: Using LVS: /usr/local/bin/netgen [globals/get_tool]: Using PEX: /usr/local/bin/magic [characterizer/]: Initializing characterizer... [characterizer/]: Analytical model enabled. [globals/setup_bitcell]: Using bitcell: bitcell |==============================================================================| |========= OpenRAM v1.1.5 =========| |========= =========| |========= VLSI Design and Automation Lab =========| |========= Computer Science and Engineering Department =========| |========= University of California Santa Cruz =========| |========= =========| |========= Usage help: openram-user-group@ucsc.edu =========| |========= Development help: openram-dev-group@ucsc.edu =========| |========= Temp dir: /home/jesse/output/ =========| |========= See LICENSE for license info =========| |==============================================================================| ** Start: 06/24/2020 22:54:09 Technology: scn4m_subm Total size: 32 bits Word size: 2 Words: 16 Banks: 1 Write size: None RW ports: 1 R-only ports: 0 W-only ports: 0 DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). [sram_config/recompute_sizes]: Recomputing with words per row: 1 [sram_config/recompute_sizes]: Rows: 16 Cols: 2 [sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4 Words per row: 1 Output files are: /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.sp /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.v /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lib /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.py /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.html /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.log /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lef /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.gds [dff_array/__init__]: Creating row_addr_dff rows=4 cols=1 [dff_array/__init__]: Creating data_dff rows=1 cols=2 [precharge_array/__init__]: Creating precharge_array [sense_amp_array/__init__]: Creating sense_amp_array [write_driver_array/__init__]: Creating write_driver_array [and2_dec/__init__]: Creating and2_dec and2_dec [and3_dec/__init__]: Creating and3_dec and3_dec [wordline_driver_array/__init__]: Creating wordline_driver_array [wordline_driver/__init__]: Creating wordline_driver wordline_driver [replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 2 [bitcell_base_array/__init__]: Creating bitcell_array 16 x 2 [bitcell_base_array/__init__]: Creating dummy_array 1 x 2 [bitcell_base_array/__init__]: Creating dummy_array_0 19 x 1 [bitcell_base_array/__init__]: Creating dummy_array_1 19 x 1 [control_logic/__init__]: Creating control_logic_rw [dff_buf/__init__]: Creating dff_buf [dff_buf_array/__init__]: Creating dff_buf_array [dff_buf/__init__]: Creating dff_buf_0 [pand2/__init__]: Creating pand2 pand2 [pdriver/__init__]: creating pdriver pdriver [pbuf/__init__]: creating pbuf with size of 2 [pdriver/__init__]: creating pdriver pdriver_0 [pdriver/__init__]: creating pdriver pdriver_1 [pand3/__init__]: Creating pand3 pand3 [pdriver/__init__]: creating pdriver pdriver_2 [pand3/__init__]: Creating pand3 pand3_0 [pdriver/__init__]: creating pdriver pdriver_3 [pdriver/__init__]: creating pdriver pdriver_4 [delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] ** Submodules: 0.6 seconds ** Placement: 0.0 seconds [router_tech/__init__]: Track width: 2.400 [router_tech/__init__]: Track space: 1.200 [router_tech/__init__]: Track wire width: 1.200 *** Init supply router: 2.2 seconds [supply_grid_router/route]: Running supply router on vdd and gnd... [supply_grid_router/create_routing_grid]: Size: 215.7 x 423.2 **** Retrieving pins: 0.0 seconds **** Analyzing pins: 0.0 seconds [router/find_blockages]: Finding blockages. **** Finding blockages: 0.1 seconds [router/convert_blockages]: Converting blockages. **** Converting blockages: 0.0 seconds [router/convert_pins]: Converting pins for vdd. [router/convert_pins]: Converting pins for gnd. **** Converting pins: 0.4 seconds [router/separate_adjacent_pin]: Comparing vdd and gnd adjacency [router/separate_adjacent_pin]: Removed 0 adjacent grids. **** Separating adjacent pins: 0.1 seconds [router/enclose_pins]: Enclosing pins for vdd [router/enclose_pins]: Enclosing pins for gnd **** Enclosing pins: 0.2 seconds *** Finding pins and blockages: 0.8 seconds [supply_grid_router/route_supply_rails]: Routing supply rail gnd. [supply_grid_router/route_supply_rails]: Routing supply rail vdd. *** Routing supply rails: 1.2 seconds [supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for vdd [supply_grid_router/route_simple_overlaps]: Routed 102 simple overlap pins [supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for gnd [supply_grid_router/route_simple_overlaps]: Routed 173 simple overlap pins *** Simple overlap routing: 0.0 seconds [supply_grid_router/route_pins_to_rails]: Maze routing vdd with 0 pin components to connect. [supply_grid_router/route_pins_to_rails]: Maze routing gnd with 1 pin components to connect. [router/run_router]: Found path: cost=3 [router/run_router]: [[v3d[-6, 145, 0]], [v3d[-6, 145, 1]], [v3d[-6, 144, 1]]] *** Maze routing supplies: 0.5 seconds ** Routing: 4.7 seconds [verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm 0 [verify.magic/run_lvs]: sram_2_16_scn4m_subm LVS matches ** Verification: 7.7 seconds ** SRAM creation: 13.1 seconds LEF: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lef ** LEF: 0.4 seconds GDS: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.gds ** GDS: 0.2 seconds SP: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.sp ** Spice writing: 0.1 seconds LIB: Characterizing... [characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 39.2968 ] [characterizer.lib/prepare_tables]: Slews: [0.0125 0.05 0.4 ] [characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('SS', 5.0, 25), ('FF', 5.0, 25)] [characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25) [characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_TT_5p0V_25C.lib [characterizer.delay/analytical_power]: Dynamic Power: 7.041373912099999 mW [characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW [characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) [characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.3470349836940743, 0.006179820369407407 [characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.3650838947762967, 0.00798471147762963 [characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.4372795391051854, 0.015204275910518518 [characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.3470349836940743, 0.006179820369407407 [characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.3650838947762967, 0.00798471147762963 [characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.4372795391051854, 0.015204275910518518 [characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.3470349836940743, 0.006179820369407407 [characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.3650838947762967, 0.00798471147762963 [characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.4372795391051854, 0.015204275910518518 [verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm 0 [verify.magic/run_lvs]: sram_2_16_scn4m_subm LVS matches [characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25) [characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_SS_5p0V_25C.lib [characterizer.delay/analytical_power]: Dynamic Power: 6.401249010999999 mW [characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW [characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) [characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.481738482063482, 0.006797802406348149 [characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.5015922842539264, 0.008783182625392592 [characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.581007493015704, 0.016724703501570373 [characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.481738482063482, 0.006797802406348149 [characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.5015922842539264, 0.008783182625392592 [characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.581007493015704, 0.016724703501570373 [characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.481738482063482, 0.006797802406348149 [characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.5015922842539264, 0.008783182625392592 [characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.581007493015704, 0.016724703501570373 [verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm 0 [verify.magic/run_lvs]: sram_2_16_scn4m_subm LVS matches [characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25) [characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_FF_5p0V_25C.lib [characterizer.delay/analytical_power]: Dynamic Power: 7.82374879122222 mW [characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW [characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) [characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.212331485324667, 0.0055618383324666665 [characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.2285755052986669, 0.007186240329866667 [characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.293551585194667, 0.013683848319466669 [characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.212331485324667, 0.0055618383324666665 [characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.2285755052986669, 0.007186240329866667 [characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.293551585194667, 0.013683848319466669 [characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.212331485324667, 0.0055618383324666665 [characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.2285755052986669, 0.007186240329866667 [characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.293551585194667, 0.013683848319466669 [verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm 0 [verify.magic/run_lvs]: sram_2_16_scn4m_subm LVS matches ** Characterization: 24.0 seconds Config: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.py ** Config: 0.0 seconds Datasheet: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.html ** Datasheet: 0.0 seconds Verilog: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.v ** Verilog: 0.0 seconds [globals/cleanup_paths]: Purging temp directory: /home/jesse/output/ [verify.magic/print_drc_stats]: DRC runs: 4 [verify.magic/print_lvs_stats]: LVS runs: 4 [verify.magic/print_pex_stats]: PEX runs: 0 ** End: 37.8 seconds