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OpenRAM
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794 Commits

Author SHA1 Message Date
mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
mrg 43d2058b3c Remove temp files 2020-10-08 10:35:27 -07:00
mrg 9a0fc8047b Remove diff 2020-10-08 09:53:52 -07:00
mrg 7076c376e0 Remove log from branch 2020-10-08 09:53:17 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg a145a37cf7 PEP8 fixes in regress.py 2020-10-05 15:56:12 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg c4952ca8be Skip full sram pex test too slow 2020-10-05 13:51:20 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 64cc620440 Add sram pex test 2020-10-02 14:55:10 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg a62b82128c Skip riscv func test because too slow 2020-10-02 13:33:58 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
mrg 392afd4d4b Add unit test for hierarchical wordline. 2020-09-15 13:46:21 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg 12fd60e8c3 Fix pbitcell array test 2020-09-09 12:02:09 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg b762580ee2 Skip global test for now 2020-08-19 11:36:21 -07:00
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg f58fc6579f Rename local/global tests 2020-08-18 15:58:44 -07:00