OpenRAM

Author	SHA1	Message	Date
Michael Timothy Grimes	b90f5c9a59	pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports	2018-02-08 14:21:15 -08:00
Michael Timothy Grimes	64e7ed5b5e	Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports Adding 04_pbitcell_test.py: The benchtest for pbitcell Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read transistors and their corresponding vias. Then several drc corrections need to be made.	2018-01-09 13:39:42 -08:00

Author

SHA1

Message

Date

Michael Timothy Grimes

b90f5c9a59

pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd

current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports

2018-02-08 14:21:15 -08:00

Michael Timothy Grimes

64e7ed5b5e

Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports

Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.

2018-01-09 13:39:42 -08:00

2 Commits