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OpenRAM
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3,545 Commits 4 Branches 63 Tags 78 MiB
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3545 Commits

Author SHA1 Message Date
mrg 3062aba214 Fix update to exclude bits with RBLs 2020-09-09 13:03:05 -07:00
mrg 138cbfac15 Flatten dummy pbitcell too 2020-09-09 12:58:22 -07:00
mrg 12fd60e8c3 Fix pbitcell array test 2020-09-09 12:02:09 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
mrg 8e91ec1770 Add check_pins function 2020-09-08 13:31:50 -07:00
mrg 1269bf6e16 Global bitcell working 2020-09-04 13:06:58 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
Hunter Nichols 500327d59b Fixed import in simulation and fixed names in functional 2020-09-04 02:24:18 -07:00
mrg 1534295326 Ground dummy lines in replica bitcell array 2020-09-03 14:04:20 -07:00
mrg f6f6242d68 Ground dummy lines in replica bitcell array 2020-09-03 10:45:28 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg 4ec47d8ee1 Refactor global and local to be a bitcell_base_array 2020-09-01 11:59:01 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
Hunter Nichols 13b1d4613c Moved spice naming checking code from design to the spice base module 2020-08-31 14:36:13 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg da827d923f Merge branch 'wlbuffer' into dev 2020-08-26 10:00:34 -07:00
mrg c321d85595 Fix syntax error for dual port 2020-08-26 09:54:41 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bdb18b4cab Fix disconnected replica pins 2020-08-25 14:51:49 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 856cce1e62 Add -json for detailed LVS output 2020-08-25 13:58:28 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 3f45d10797 fix column decoder 2020-08-25 02:46:16 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00
jcirimel 854d51c721 merge dev 2020-08-19 14:25:41 -07:00
mrg b762580ee2 Skip global test for now 2020-08-19 11:36:21 -07:00
mrg 593a98e29a Update local bitcell array for dual port 2020-08-19 11:35:55 -07:00
jcirimel b7ef5496c4 decoder drc clean 2020-08-19 00:39:55 -07:00
mrg e215c0e016 Drafting global bitcell array 2020-08-18 16:30:55 -07:00
mrg 5776788574 Order of wordlines and bitlines in bank 2020-08-18 16:30:38 -07:00
mrg 224e359208 Fix pin order for replica array 2020-08-18 15:59:05 -07:00
mrg f58fc6579f Rename local/global tests 2020-08-18 15:58:44 -07:00
mrg e3e4bac922 Fix replica bitcell array for right only RBL 2020-08-18 15:47:52 -07:00
mrg 59d65c46c3 Fix bug in not adding RBLs in local bitcell array 2020-08-18 15:11:10 -07:00
mrg 2643a96f97 Order inputs wordline, bitline, supply 2020-08-18 14:29:36 -07:00
mrg b288bba43e Add global bitcell array test 2020-08-18 14:29:23 -07:00
mrg f98fbb175b Merge branch 'wlbuffer' into dev 2020-08-18 10:06:52 -07:00
mrg e37a9234cc Update replica column call to new refactor 2020-08-18 09:14:50 -07:00
mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-18 09:01:41 -07:00
mrg bc974ff78e Update replica column unit tests for new refactor 2020-08-18 08:56:24 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
jcirimel 35eac54c0d update freepdk bitcell for pex 2020-08-17 17:47:43 -07:00