luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,545 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3099 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low a23f72d5a3 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
mrg 0ef06ec1e1 Fix dff_buf width in netlist_only mode 2020-02-10 20:06:34 +00:00
mrg 6bf33a980f Add conservative well spacing between library FF and our pgates. 2020-02-10 19:28:30 +00:00
mrg f7915ec55e Route to top of NMOS to prevent poly overlap nmos 2020-02-10 17:12:39 +00:00
jcirimel 101eb28112 revert example scn4m to non netlist only 2020-02-09 23:52:11 -08:00
jcirimel 27eced1fbe netlist_only done 2020-02-09 23:51:01 -08:00
jcirimel 7038fad930 s8 gdsless netlist only working up to pdriver 2020-02-09 23:10:33 -08:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
mrg 4d85640a00 Change col addr spacing to col addr size 2020-02-07 22:20:16 +00:00
mrg 2ff058f5d5 PEP8 Cleanup and reverse pitch offset of col addr routing 2020-02-06 22:59:30 +00:00
mrg 4b06ab9eaf Move port 2 column address bus down. 
PEP 8 cleanup.
 2020-02-06 19:46:10 +00:00
mrg 5e514215d5 Force vertical vias on pnand3 2020-02-06 16:44:19 +00:00
mrg f0ecf385e8 Nwell fixes in pgates. 
Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.
 2020-02-06 16:20:09 +00:00
Jesse Cirimelli-Low b107934672 fix styling 2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
mrg 596302d9a9 Update pgate well and well contacts. 
Extend well left and right past a cell boundary.
Use asymmetric well contacts.
 2020-02-05 18:22:45 +00:00
mrg 04d254542d Add general well_extend_active DRC in design class. 2020-02-05 18:22:22 +00:00
mrg 4526986de3 Update contact well support. 
Add asymmetric tap overlap support in DRC rules.
Add static nwell and pwell contact in class for measurements.
 2020-02-05 18:21:01 +00:00
jcirimel 7cb3091140 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into custom_mod 2020-02-04 23:40:54 -08:00
jcirimel ed11145ca4 add custom module file, make dff clk pin dynamic 2020-02-04 23:35:06 -08:00
mrg 304971ff60 Fix ptx so nmos and pmos have same active offset and gates align 2020-02-04 17:38:35 +00:00
mrg 53217e4030 Check min well width in contact and redo position 2020-02-04 17:37:58 +00:00
mrg 5aed893725 Add nwell/pwell tap test 2020-02-03 18:41:06 +00:00
mrg 34c9b3a0a5 Fix well offset computation for PMOS 2020-02-03 17:37:53 +00:00
Jesse Cirimelli-Low 6cf20a0353 add technology based module customization 2020-01-30 19:44:24 +00:00
mrg 400cf0333a Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
mrg 0880c393fd Fix base bitcell syntax error. Remove some unused imports. 2020-01-30 01:58:30 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann b5701af864 column_mux: Allow y axis mirroring 
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:39 +01:00
Bastian Koppelmann ed66fca031 write_driver/sense_amp/precharge arrays: Allow y axis mirroring 
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:39 +01:00
Bastian Koppelmann dd1afe0313 Bitcell arrays: Allow mirroring on the y axis 
this allows for bitcells that need to be mirrored on the y axis, like
thin cells. However, the portdata elements also need to be mirrored on
the y axis. Otherwise the router will fail horribly when connecting
bitlines.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:21 +01:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 9749c522d1 tech: Make power_grid configurable 
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.

For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:34 +01:00
Bastian Koppelmann 90a4a72bba modules: Use add_power_pin API for all modules 
sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:49 +01:00
Bastian Koppelmann 988df8ebb9 hierarchy_layout: Add methods to create via stacks 
this allows us to simplify add_power_pin() and gives a clean
API to create vias through multiple layers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:32 +01:00
Bastian Koppelmann 3fb2b9c1c3 Bitcell arrays: Create abstract base class 
a lot of functions of dummy- and bitcell-array are either copy-pasted or
have just slight differences. Merge all of those into an abstract base
class such that we don't have too much duplicate code.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 10:59:58 +01:00
Jesse Cirimelli-Low 6e070925b6 update magic for multiport 2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell 2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low d42cd9a281 pbitcell working with bitline adjustments 2020-01-27 10:03:31 +00:00
Matt Guthaus e62beae805 Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
mrg 877ea53b7f Fix conflicting boundary name 2020-01-24 21:24:44 +00:00
mrg 71cbe74017 Round middle position fix 2020-01-24 18:00:28 +00:00
mrg aa8f389f28 Add fudge factor to pbitcell wells 2020-01-24 17:45:24 +00:00
Jesse Cirimelli-Low 1062cbfd7f begin fixes to pbitcell, prepare multibank pex 2020-01-24 10:24:29 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
jcirimel 40c01dab85 fix bl in stim file 2020-01-21 01:44:15 -08:00
jcirimel 73691f6054 fix bug in top level bitline label placement 2020-01-21 00:20:52 -08:00
Jesse Cirimelli-Low 5778901cfe pull bitline labels to top level spice 2020-01-20 12:16:30 +00:00
jcirimel 364842569a fix s_en in stim 2020-01-16 12:16:49 -08:00
mrg 306740f0f3 Add empty minarea function 2020-01-16 19:27:59 +00:00
mrg 262782cba0 Remove print, fix compare 2020-01-16 19:27:39 +00:00
mrg a2387da29d PEP format design 2020-01-16 19:26:57 +00:00
mrg ea00258be9 Cleanup contact 2020-01-16 19:26:43 +00:00
jcirimel 075bf0d841 label bitcell in stim, add s_en top level to stim 2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low 2733c3bf3f fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
Jesse Cirimelli-Low 05ab018ffc strip padding character from gds reading 2020-01-07 00:01:32 +00:00
Bastian Koppelmann 2c610036b2 router/supply_grid_router: Print init time to the user 
this can take considerable amount of time, so the user knows that
useful work is done.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 12:24:14 +01:00
Bastian Koppelmann c0c89e465a vector: Implement hash cache for vector3d and vector 
this gives us a small runtime improvement in the router.

For FreePDK45 word_size=8, num_words=256

Improved
*** Maze routing supplies: 89.8 seconds
** Routing: 279.3 seconds

Non-improved
*** Maze routing supplies: 105.1 seconds
** Routing: 293.5 seconds

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 12:16:10 +01:00
Bastian Koppelmann 7ff5121d8c base/pin_layout: Implement hash cache 
the hash value only depends of the properties 'rect' and 'layer' so we
only compute the hash if those values are changed. Otherwise we just
return the precomputed value. This gives us a major speedup (~10x) if
the hash is used as a key in a dict.

During the grouping of pins in analyze_pins() this gives the best
improvements. For example for FreePDK45 with num_bits=8, num_words=256

Improved
**** Analyzing pins: 20.9 seconds
** Routing: 293.8 seconds
** SRAM creation: 349.8 seconds

Non-improved
**** Analyzing pins: 267.9 seconds
** Routing: 537.5 seconds
** SRAM creation: 592.9 seconds

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:39:59 +01:00
Bastian Koppelmann 14e8a26246 base/pin_layout: Make rect and layer properties 
only rect and layer are used to compute the hash for a pin. Having
those as properties allows us to cache the hash value and only update it
if either rect or layer are written.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:33:34 +01:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Matthew Guthaus a6f5e59e18 Remove unused layers and simplify layer check to work without it. 2019-12-23 21:49:47 +00:00
Matthew Guthaus 082f575e2a Use active_width in ptx again despite colliding with DRC rule 2019-12-23 21:45:09 +00:00
Matthew Guthaus bec12f5b94 Cleanup. 2019-12-23 21:16:08 +00:00
Matt Guthaus 4ad920eaf7 Small fixes to tech usage. 2019-12-23 08:42:52 -08:00
Matt Guthaus 9ad06a7770 Move write mask vias to center to avoid data pins. 2019-12-20 11:48:27 -08:00
Matt Guthaus 89396698ef Non-preferred via in pnand active 2019-12-20 10:36:14 -08:00
Matt Guthaus 82496a66fe Simplify supply code. 2019-12-20 10:35:57 -08:00
Matt Guthaus 9e8b03d6c2 Merge branch 'dev' into tech_migration 2019-12-19 16:23:22 -08:00
Matt Guthaus d2461e5011 Supply indexing bug resolved. Recompute width/height basted on insts. 2019-12-19 16:19:21 -08:00
Matt Guthaus 0da8164ea6 Remove some unnecessary via directions. 2019-12-19 13:54:50 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Bastian Koppelmann 11760a9993 sram_factory: Add check for duplicate module name 
sram_factory cannot handle duplicate module name, thus we bail out and
raise an error if a user attempts that.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-19 16:31:52 +01:00
Bastian Koppelmann 1df16eceb6 sram_factory: Give proper priority to overrides 
modules overridden by the user are the highest priority, then modules
overridden by the technology. If nothing is overriden, use the defaults
from OPTS (if they exist) or use the requested module_type.

This fixes that custom tech_modules could not be used, if they had a default in
OPTS even if the latter was not overridden by the user.

We don't need extra defaults in the tech_modules, as we now only use them,
if they have been overridden by the tech_module.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-19 15:58:00 +01:00
Matt Guthaus 36cb675150 Fix minwidth for multiple via bug. 2019-12-18 09:30:00 -08:00
Bastian Koppelmann fab963701b sram_base: Instantiate "dff_array" and "bank" through sram_factory 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:50 +01:00
Bastian Koppelmann 451ef4d896 sram_factory: Allow a prefered module name 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:47 +01:00
Bastian Koppelmann de6b207798 hierachy_layout: Move number of via arg to add_power_pins() 
this allows custom modules to state how many vias they need
for power rails.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:43 +01:00
Jesse Cirimelli-Low 88d3da0b4a fix control logic pex labels with multiport 2019-12-18 12:45:12 +00:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matt Guthaus aceaa9fb21 Standardize contact names. 2019-12-17 15:55:20 -08:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matthew Guthaus fc4685c7f7 Cleanup. 2019-12-17 23:07:01 +00:00
Matthew Guthaus 449b0a7c28 Make wire test programmatic 2019-12-17 22:36:38 +00:00
Matt Guthaus c025ce6356 Add li to preferred direction 2019-12-17 14:06:23 -08:00
Matt Guthaus 24546461ad Fix over-writing of active spacing rule. 2019-12-17 11:23:59 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus a79d03fef4 Remove poly contact 2019-12-16 17:18:49 -08:00
Matt Guthaus d3a2c46cb9 Remove some contact tests 2019-12-16 17:15:29 -08:00
Matt Guthaus 6058af994c Fix ignore gds files 2019-12-16 15:39:32 -08:00
Matt Guthaus 3eb0dad06a Remove cells from DRC/LVS in the blackbox tech list. 2019-12-16 15:33:30 -08:00
Matt Guthaus acbbbe9403 Make exception more readable. 2019-12-16 12:07:40 -08:00
Matt Guthaus f30d0b9197 Fix KeyError for bitell types. 2019-12-16 12:04:33 -08:00
Matt Guthaus 5176a70f84 Add comments to module importing routines 2019-12-16 10:21:24 -08:00
Matt Guthaus 2a9129ef45 Small fix to tech and config over-rides 2019-12-16 10:11:26 -08:00
Matt Guthaus be4893839b Remove old drc/lvs override name 2019-12-16 10:05:52 -08:00
Bastian Koppelmann 306c0b92c3 globals: Add tech module path to Pythonpath if it exists 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:56:16 +01:00
Bastian Koppelmann 74cd4f989d Remove hardcoded module class names 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:56:06 +01:00
Bastian Koppelmann 233ec010ff modules: Create a class that wraps all the module class names 
this removes hard coded values from the module instatiations. It also allows
users to override certain modules with their custom cells.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:38 +01:00
Matt Guthaus f71cfe0d9d Generalize active and poly stacks 2019-12-13 14:56:14 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus 8d3f1d19cb Fix missing rule 2019-12-11 18:02:32 -08:00
Matt Guthaus 76f7019432 Merge branch 'dev' into tech_migration 2019-12-11 17:59:51 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matt Guthaus f9a66e86b4 Add npc option to contact 2019-12-11 09:09:59 -08:00
Matt Guthaus 31de5ab87e Merge remote-tracking branch 'bkoppelmann/master' into dev 2019-12-11 08:46:52 -08:00
Bastian Koppelmann 928b02aa1f gdsMill: Fix reader/writer ignoring the 'DATATYPE' of 'PATH' records 
most readers (like KLayout/Calibre) will not open gds files omiting the
DATATYPE.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-11 10:47:38 +01:00
Aditi Sinha 5b3846e1e5 Changed replica bitcell array to work with bank tests for non power of two rows 2019-12-08 13:24:39 +00:00
Matt Guthaus 4a1b10ff0d Remove extra cast 2019-12-05 21:33:13 -08:00
Matthew Guthaus f3286fb0c2 Don't add boundary to ptx 2019-12-06 02:37:12 +00:00
Matthew Guthaus 5af22b79e2 Only add boundary for if there's a DRC stdc layer 2019-12-06 02:17:58 +00:00
Matt Guthaus 53c72c6054 Merge branch 'tech_migration' of github.com:VLSIDA/PrivateRAM into tech_migration 2019-12-05 15:41:56 -08:00
Matt Guthaus d150b165de Merge branch 'tech_migration' of github.com:VLSIDA/PrivateRAM into tech_migration 2019-12-05 15:38:29 -08:00
Matt Guthaus b1d8a35aa7 Add contact variation 2019-12-05 15:38:25 -08:00
Matthew Guthaus 3deeaf7164 Decrease verbosity of boundary layer 2019-12-05 23:33:23 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matthew Guthaus 8f473b26a9 Add replica bitcell test for 1 port 2019-12-05 01:14:06 +00:00
Matthew Guthaus d519c00aa1 Fix contact order in test 2019-12-05 01:06:31 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 0d35941241 Fix missing dbUnit conversion in gdsMill 2019-12-03 12:06:58 -08:00
Matt Guthaus 7b9e7ff35b Nominal corner only for sim tests. Netlist only for speed. 2019-11-30 12:48:25 -08:00
Matt Guthaus 615c24f7bc Merge branch 'dev' into tech_migration 2019-11-30 12:38:35 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 46c2cbd2d9 Check nominal_corner_only in new corner creation routine 2019-11-29 14:47:02 -08:00
Matt Guthaus bedae87315 Only use max/min and typical corner 2019-11-29 13:31:44 -08:00
Matt Guthaus 2a912dab7a Remove unused config files 2019-11-29 12:35:35 -08:00
Matt Guthaus 0cdd3af1aa Change default nominal corners to false and enable in test config. 2019-11-29 12:08:53 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus abd8b0a23a Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
Matt Guthaus b71d630643 None for layer means unused. 2019-11-26 13:34:39 -08:00
Matt Guthaus 04045cf672 Fix syntax error 2019-11-26 13:24:19 -08:00
Matt Guthaus f4599b7121 Default tools are calibre except for SCMOS 2019-11-26 13:23:18 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matt Guthaus 909321326d Ignore unused layers 2019-11-26 13:21:29 -08:00
Matt Guthaus 67a0928303 Merge branch 'dev' into tech_migration 2019-11-21 11:02:33 -08:00
Matt Guthaus 982e12be5e Increment minor version 2019-11-21 11:00:22 -08:00
Matt Guthaus 807923cbf1 Ignore pycache dirs. Fix output error message. 2019-11-21 10:11:19 -08:00
Matt Guthaus 190c5a078e Fix permissions on pwrite_driver test 2019-11-20 11:49:39 -08:00
Matt Guthaus 3364f47e56 Fix wrong supply voltage in config files. 2019-11-20 09:50:27 -08:00
Matt Guthaus 240c416100 Remove extra print 2019-11-17 10:40:01 -08:00
Matthew Guthaus cdf01c6c23 Fix test 30 for generic configs 2019-11-17 00:49:38 +00:00
Matthew Guthaus b3fb4e3183 Make unit test configs generic to tech_name 2019-11-17 00:44:31 +00:00
Matthew Guthaus b3b3cf0210 Merge remote-tracking branch 'origin/dev' into tech_migration 2019-11-17 00:15:18 +00:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
Matthew Guthaus 0b3d2fe9de Undo pdriver size change for now. 2019-11-16 19:54:39 +00:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Aditi Sinha 2c7aa5d0da Non-power of 2 address decode tentative 2019-11-15 03:59:57 +00:00
Matthew Guthaus 7e9d08206c Fix config import to be location independent 2019-11-14 20:18:18 +00:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matthew Guthaus bba6995653 Call debugger if debug_level more than 0 and an error. 2019-11-08 19:42:09 +00:00
Matthew Guthaus 8d158e9eb5 Fix lpp change 2019-11-08 15:45:25 +00:00
Matthew Guthaus 32f1cde897 PEP8 formatting 2019-11-07 16:48:37 +00:00
Matthew Guthaus 0dea153919 PEP8 formatting 2019-11-07 16:33:13 +00:00
Matthew Guthaus a2422cc8d4 Sometimes round down pdriver to fix polarity 2019-11-06 21:51:21 +00:00
Matthew Guthaus 35e65fc6f2 PEP8 wordline driver 2019-11-06 21:19:36 +00:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 764d4da1bd Clean up config file organization. Improve gdsMill debug output. 2019-10-23 10:48:18 -07:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
vagrant 67c768d22c Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
Hunter Nichols d722311822 Merge branch 'dev' into update_scmos_models 2019-10-03 13:16:32 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus cbbcb97a10 Merge branch 'dev' into feedthru 2019-09-27 09:42:51 -07:00
Matt Guthaus 99507ba5c5 Remove rbl_bl_delay_bar from w_en logic inputs. 2019-09-07 23:22:01 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus 322af0ec09 Remove sense enable during writes 2019-09-07 20:04:48 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus 93c89895c9 Remove unused test structures 2019-09-06 14:58:47 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 6bee66f9dc Forgot to add cs_bar to rw port rails. 2019-09-06 09:29:23 -07:00
Matt Guthaus 969cca28e4 Enable sensing during writes. Need to add dedicated test. 2019-09-06 07:16:50 -07:00
jsowash 1c65b90c70 Merge branch 'dev' into add_wmask 2019-09-05 09:15:05 -07:00
Matt Guthaus 678b2cc3fa Fix functional test clk name 2019-09-04 18:59:08 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
jsowash 8c33749223 Uncommented offset_all_coordinates. 2019-09-04 16:41:27 -07:00
jsowash febc053587 Moved SRAM macro in LEF file to origin and removed poly. 2019-09-04 16:11:12 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 8c601ce939 Model tests don't need layout 2019-09-04 16:06:12 -07:00
Matt Guthaus c5568e86fe Enable spice and don't purge option to test 30 2019-09-04 14:33:25 -07:00
jsowash fbecb9bc02 Added poly to LEF files. 2019-09-04 14:06:17 -07:00
jsowash d6e7047e2f Added metal4 to lef files since it's now used with a wmask. 2019-09-04 13:04:51 -07:00
Matt Guthaus eadb5d5e48 Allow gds file for front end with new options 2019-09-04 10:26:54 -07:00
jsowash 496a9919b8 Added wmask as a type group to .lib. 2019-09-04 09:45:11 -07:00
jsowash 452cc5e443 Added wmask to lib.py. 2019-09-04 09:29:45 -07:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash abb86c338b Added port specification. 2019-09-03 14:52:43 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
jsowash 01bdea23ae Merge branch 'add_wmask' of https://github.com/VLSIDA/PrivateRAM into add_wmask 2019-09-03 11:50:57 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
jsowash 4a8ec7a687 Added 2 port test for wmask. 2019-09-03 11:49:37 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash e8435d0d83 Added test for picorv32 memory without characterization. 2019-08-30 11:24:20 -07:00
jsowash e3b42430bd Changed max_gap_size_wmask to take into account column ffs. 2019-08-29 17:09:17 -07:00
jsowash bbe235074c Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing. 2019-08-29 16:41:58 -07:00
Matt Guthaus a78245786c Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-29 16:06:39 -07:00
Matt Guthaus 7fe9e5704d Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
jsowash 37116ce9d8 Increased spacing between wmask and data dffs. 2019-08-29 16:00:50 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash af3d2af0ec Merge branch 'dev' into add_wmask 2019-08-29 12:56:11 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
jsowash 5099ff6f6c Changed A/Z pins to copy_layout_pin and made en (B) pin a single pin. 2019-08-29 09:01:35 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus bdf29c3a26 Fix non-preferred route width again. This time it is likely right. 2019-08-22 13:57:14 -07:00
Matt Guthaus 560d768010 Fix syntax error in router 2019-08-22 13:46:32 -07:00
Matt Guthaus afaa946f9c Fix width of non-preferred trunk wire 2019-08-22 12:03:38 -07:00
jsowash 27ec617315 Fixed M1.5 error in 8mux tests which came from pdriver. 2019-08-22 09:34:53 -07:00
Matt Guthaus 2ffdfb18a4 Fix trunks less than a pitch in channel route 2019-08-21 17:11:02 -07:00
jsowash a8df5528f9 Added 2 mux test for wmask. 2019-08-21 16:06:36 -07:00
Matt Guthaus 98f526427e Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 15:33:03 -07:00
Matt Guthaus 9ada9a7dfa Fix pitch in channel router to support M3/M4. 2019-08-21 15:32:49 -07:00
jsowash 737e873923 Changed via direction for via1 in flip flops. 2019-08-21 14:49:54 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
jsowash 980760b724 Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask. 2019-08-21 14:02:57 -07:00
Matt Guthaus 5f3ffdb8ba Output name and version in help 2019-08-21 14:00:55 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
jsowash 4f01eeb3c1 Combined changes to the pin locations and vias. 2019-08-21 12:36:53 -07:00
jsowash c2015335b0 Fixed merge issues. 2019-08-21 11:54:22 -07:00
jsowash 4813c01d56 Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively. 2019-08-21 11:50:28 -07:00
Matt Guthaus b0821a5a0e Re-add simplified power pins on edges 2019-08-21 11:42:56 -07:00
Matt Guthaus b94af3e3fd Add vias for new channel routes 2019-08-21 11:33:43 -07:00
Matt Guthaus f281510828 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 11:20:42 -07:00
Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array. 2019-08-21 11:20:35 -07:00
jsowash 43d45fba98 Moved pwr/gnd pins to the right of the rail. 2019-08-21 10:44:04 -07:00
Matt Guthaus c39b09c736 Merge branch 'add_wmask' of github.com:VLSIDA/PrivateRAM into add_wmask 2019-08-21 10:18:59 -07:00
Matt Guthaus 54ab9440db Use pdriver instead of pinv in pand gates. 2019-08-21 10:18:46 -07:00
jsowash 0cbc4a7acf Moved wmask dff above data dff and changed channel route to m3/m4 for data and m1/m2 for wmask. 2019-08-21 10:07:20 -07:00
Matt Guthaus 53d0544291 Minor cleanup and additional assertion checking. 2019-08-21 08:50:12 -07:00
Matt Guthaus f2568fec80 Change permissions on tests to +x. Add single bank wmask test. 2019-08-21 08:49:46 -07:00
jsowash 71af70a636 Moved pwr/gnd vias and corrected width boundary. 2019-08-20 09:14:23 -07:00
jsowash 316132a33c Sized inverter for number of driven write drivers. 2019-08-19 13:31:49 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash a28c9fed8b Fixed bug for more than 2 wmasks and changed test to test 4 wmasks. 2019-08-16 14:27:44 -07:00
jsowash d02ea06ff2 Added method to route between the output of wmask AND array and en of write driver. 2019-08-16 14:12:41 -07:00
jsowash aaa1e3a614 Added change to route wmask en between driver and AND gates. Need to apply it to all cases. 2019-08-16 10:23:51 -07:00
jsowash 92e0671e15 Removed DRC error with AND array in freepdk45 and moved pin on en_{} pin in port data. 2019-08-15 12:36:17 -07:00
jsowash f0f811bad9 Added a condiitonal to only route wmask dff when there's a write size. 2019-08-14 12:40:14 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash aa4803f3c4 Increased enable pin's width for larger # of column mux ways. 2019-08-11 15:25:05 -07:00
jsowash 2573b5f48b Fixed merge conflict. 2019-08-11 14:39:36 -07:00
jsowash d259efbcda Connected wdriver_sel between write_mask_and_array and write_driver_array. 2019-08-11 14:33:08 -07:00
Matt Guthaus e5618b88af Don't add sense amp to write only port. Fix write_and None define. 2019-08-11 08:46:36 -07:00
Matt Guthaus d56a972d61 Update ngspice tests due to new version 2019-08-10 17:59:30 -07:00
Matt Guthaus c09005dab9 Redo logic for detecting bad bitlines 2019-08-10 17:32:36 -07:00
Matt Guthaus 6cf7366c56 Gate sen during first half period 2019-08-10 16:30:02 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Matt Guthaus 23676c0f37 Route bl in SRAM write ports too 2019-08-10 12:53:07 -07:00
Matt Guthaus 34d28a19e6 Connect wl_en in all ports to bank. 2019-08-10 12:30:23 -07:00
Matt Guthaus bac684a82a Fix control logic routing. 2019-08-10 08:53:02 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Hunter Nichols 2573d4e7d0 Removed testing code from config file. 2019-08-08 19:27:44 -07:00
Hunter Nichols 1d22d39667 Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
jsowash 49fffcbc92 Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver. 2019-08-08 15:49:23 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
jsowash 0cfa0ac755 Shortened write driver enable pin so that a write mask can be used without a col mux in layout. 2019-08-08 12:57:32 -07:00
jsowash 59e5441aef Added write mask to write driver array 2019-08-08 08:46:58 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Hunter Nichols fc1cba099c Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Matt Guthaus 275891084b Add pand3 2019-08-07 16:33:29 -07:00
Matt Guthaus c2655fcaa9 Update pnor2 to new placement logic 2019-08-07 16:01:05 -07:00
jsowash 9409f60237 Merge branch 'dev' into add_wmask 2019-08-07 09:42:55 -07:00
jsowash abb9af0ea8 Added layout pins for wmask_and_array 2019-08-07 09:33:19 -07:00
jsowash a6bb410560 Begin implementing a write mask layout as the port data level. 2019-08-07 09:12:21 -07:00
Hunter Nichols 6860d3258e Added graph functions to compute analytical delay based on graph path. 2019-08-07 01:50:48 -07:00
Matt Guthaus ae46a464b9 Undo delay changes. Fix bus order for DRC. 2019-08-06 17:17:59 -07:00
Hunter Nichols 2ce7323838 Removed all unused analytical delay functions. 2019-08-06 17:09:25 -07:00
Matt Guthaus a2f81aeae4 Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. 2019-08-06 16:29:07 -07:00
Hunter Nichols 2efc0a3983 Merge branch 'dev' into analytical_cleanup 2019-08-06 14:51:30 -07:00
Matt Guthaus ad35f8745e Add direction to pins of all modules 2019-08-06 14:14:09 -07:00
Matt Guthaus c3f38a5cac ngspice delays updated (again) 2019-08-05 16:09:27 -07:00
Matt Guthaus aae8566ff2 Update golden delays. Fix uninitialized boolean. 2019-08-05 15:45:59 -07:00
Matt Guthaus 4d11de64ac Additional debug. Smaller psram func tests. 2019-08-05 13:53:14 -07:00
Matt Guthaus e4532083da Increase stages and FO of fixed delay line. 2019-08-05 13:52:32 -07:00
jsowash a4a72a9639 Merge branch 'dev' into add_wmask 2019-08-01 13:49:52 -07:00
Matt Guthaus 7ba97ee0ba Fix missing port in control logic 2019-08-01 12:42:51 -07:00
Matt Guthaus 8771ffbfed Fix bug to add all p_en_bar to banks 2019-08-01 12:28:21 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus a8d09acd40 Use ordered dict instead of sorting keys 2019-08-01 12:21:30 -07:00
jsowash e4d8ba90a5 Merge branch 'dev' into add_wmask 2019-08-01 12:07:14 -07:00
Matt Guthaus d403362183 Sort keys for random read address choice. 2019-08-01 11:32:49 -07:00
jsowash bb1627bcec Added test to end of w_mask_and_array so a regression test will be performed on it. 2019-07-31 14:59:33 -07:00
jsowash 9819b5356e Merge branch 'dev' into add_wmask 2019-07-31 14:43:48 -07:00
jsowash 774f08da51 Added layout pins to and test for write_mask_and_array. 2019-07-31 14:11:37 -07:00
Hunter Nichols b4ef0ec36d Removed unused characterization module. 2019-07-30 20:33:17 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00
Hunter Nichols c12dd987dc Fixed pbitcell graph edge formation. 2019-07-30 00:49:43 -07:00
Matt Guthaus 98878a0a27 Conditionally path exclude 2019-07-27 12:14:00 -07:00
Matt Guthaus 8e43469486 Update spice results 2019-07-27 12:13:44 -07:00
Matt Guthaus d7bc3e8207 Add dummy pbitcell 2019-07-27 12:13:35 -07:00
Matt Guthaus 2824315f79 Fix error in wmask if 2019-07-27 11:51:40 -07:00
Matt Guthaus 5cb320a4ef Fix wrong pin error. 2019-07-27 11:44:35 -07:00
Matt Guthaus fa4f98b122 Fix ALL of the indents. 2019-07-27 11:30:48 -07:00
Matt Guthaus 37fffb2ed2 Fix bad indent. 2019-07-27 11:14:56 -07:00
Matt Guthaus 468a759d1e Fixed control problems (probably) 
Extended functional tests for 15 cycles (slow, but more checking)
Fixed s_en to be gated AFTER the RBL.
 2019-07-27 11:09:08 -07:00
Matt Guthaus 52029d8e48 Fix incorrect port_data BL pin name. 2019-07-27 06:11:45 -07:00
Matt Guthaus 179efe4d04 Fix bitline names in merge error 2019-07-26 22:03:50 -07:00
Matt Guthaus e750ef22f5 Undo some control logic changes. 2019-07-26 21:41:27 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 7eea63116f Control logic LVS clean 2019-07-26 15:50:10 -07:00
Matt Guthaus dce852d945 Restructure control logic for improved drive and timing. 2019-07-26 14:54:55 -07:00
Matt Guthaus 3327fa58c0 Add some signal names to functional test comments 2019-07-26 14:49:53 -07:00
Hunter Nichols dc46d07ca3 Removed unused code for input loads 2019-07-26 14:20:47 -07:00
Matt Guthaus 8ebc568e8b Minor cleanup. Skip more tests until analytical fixed. 2019-07-26 08:33:06 -07:00
Matt Guthaus 20d9c30a64 Use non-analytical models for now 2019-07-25 14:55:42 -07:00
Matt Guthaus 88c399bc6c Skip prune test for now 2019-07-25 14:49:11 -07:00
Matt Guthaus d5419f99f6 Skip model tests for now 2019-07-25 14:46:33 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
Matt Guthaus 0bb41b8a5d Fix duplicate paths for timing checks 2019-07-25 13:25:58 -07:00
jsowash de485182bc Cleaned up comments about wmask. 2019-07-25 13:21:17 -07:00
jsowash 61ba23706c Removed comments for rw pen() and added a wmask func test. 2019-07-25 12:24:27 -07:00
Matt Guthaus 80df996720 Modify control logic for new RBL. 2019-07-25 11:19:16 -07:00
Matt Guthaus 5452ed69e7 Always have a precharge. 2019-07-25 10:31:39 -07:00
Matt Guthaus 54b312eaf9 Add return type 2019-07-24 17:00:38 -07:00
Matt Guthaus 2f03c594c5 Remove success initialization 2019-07-24 16:59:19 -07:00
Matt Guthaus cfc04064af Remove print. 2019-07-24 16:57:57 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
jsowash c8bbee884b Removed layout related rw port's special pen. 2019-07-24 16:01:12 -07:00
jsowash 3bcb79d9d5 Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value. 2019-07-24 15:01:20 -07:00
Matt Guthaus fe0db68965 Refactor to share get_measurement_variant 2019-07-24 11:29:29 -07:00
Matt Guthaus 9cb96bda7d Mostly formatting. Added write measurements. 2019-07-24 10:57:33 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
jsowash 01493aab3e Added wmask valuesto functional test through add_wmask() 2019-07-23 15:58:54 -07:00
Matt Guthaus 07401fc6ea Make control bus routing offset consistent 2019-07-23 09:39:28 -07:00
jsowash ddf5148fa5 Removed code where if there was no write mask, word_size=write_size. Now it stays None. 2019-07-22 14:58:43 -07:00
jsowash ad0af54a9f Removed dupliction of addr_size. 2019-07-22 13:18:52 -07:00
jsowash 2b29e505e0 Reversed order of wmask bits in functional.py since python lists go left to right. Made # of en bits equal to num_masks. 2019-07-22 12:44:35 -07:00
jsowash 72e16f8fe6 Added ability to do partial writes to addresses that have already been written to. 2019-07-22 11:19:14 -07:00
jsowash a69d35b50a Removed write_size from parameters. 2019-07-21 15:53:05 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
jsowash 082decba18 Temporarily made the functional tests write/read only all 0's or 1's 2019-07-18 15:26:38 -07:00
jsowash 5f37067da7 Turned write_mask_array into write_mask_and_array with flip flops from sram_base 2019-07-18 15:24:41 -07:00
Matt Guthaus 864639d96e Remove old replica bitline. 2019-07-18 15:19:40 -07:00
Matt Guthaus a707c6fa50 Convert psram tests to only 2 port. 2019-07-18 14:49:54 -07:00
jsowash 917a69723f Fixed typo 2019-07-17 12:26:05 -07:00
jsowash 720739a192 Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask 2019-07-17 11:04:17 -07:00
Hunter Nichols 9696401f34 Added graph exclusions to replica column to reduce s_en paths. 2019-07-16 23:47:34 -07:00
mrg e2602dd79b Add comments for pins. Fix noconn in dummy pbitcell. 2019-07-16 17:30:31 -07:00
mrg 37fcf3bf37 Move classes to individual file. 2019-07-16 15:18:04 -07:00
mrg 8ca656959b Change direction of RBL bitline pins 2019-07-16 15:09:46 -07:00
mrg b546ecce2c Check 2 ports only for layout. 2019-07-16 14:11:54 -07:00
mrg 12fa36317e Cleanup unit test. Fix s_en control bug for r-only. 2019-07-16 13:51:31 -07:00
mrg 2f55911604 Simplify column decoder placement. 2019-07-16 11:55:25 -07:00
mrg 70ee026fcf Add cell names to psingle_bank test 2019-07-16 11:54:57 -07:00
mrg 42ad0cd282 Add pbitcell RW test 2019-07-16 11:54:39 -07:00
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
mrg 37c15937e2 Add multiple control logic port types. 2019-07-15 17:07:50 -07:00
jsowash 021d604832 Removed wmask from addwrite() 2019-07-15 16:48:36 -07:00
jsowash ab27c70279 Merge branch 'dev' into add_wmask 2019-07-15 14:42:23 -07:00
jsowash ea2f786dcf Redefined write_size inrecompute_sizes() to take the new word_size() 2019-07-15 14:41:26 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg 2271946eef Fix replica array pin names 2019-07-12 14:39:56 -07:00
mrg 8815ddf7f1 Remove unnecessary feasible period search. 2019-07-12 11:55:42 -07:00
mrg 9092fa4ee6 Remove multiport control logic test since it doesn't have a bitcell anymore. 2019-07-12 11:18:47 -07:00
mrg d72691f6c2 Make mirror optional argument 2019-07-12 11:14:47 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 80145c0a92 Only enable pdb post-mortem when not purging temp for debug. 2019-07-12 10:57:59 -07:00
mrg 17d144b5b5 Clean up multiport test options to be consistent. 2019-07-12 10:39:55 -07:00
jsowash dfa2b29b8f Begin adding wmask netlist and spice tests. 2019-07-12 10:34:29 -07:00
mrg aa552f8e96 Remove debug trace 2019-07-12 10:17:33 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
Bin Wu c9c839ca46 fix the delay measure bug in pex tests 2019-07-10 04:39:40 -07:00
Bin Wu e4070ddad8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-07-10 03:09:12 -07:00
jsowash 5258016c9f Changed location of port for din_reg. 2019-07-06 12:27:24 -07:00
jsowash 6fe78fe04a Removed begin end for Verilog without wmask. 2019-07-06 11:29:34 -07:00
jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. 2019-07-05 15:55:03 -07:00
jsowash ad9193ad5a Verified 1rw mask writing and changed verilog.py accordingly. 2019-07-05 15:08:59 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash f29631695c Finished merge 2019-07-05 11:43:31 -07:00
jsowash 150259e2ba Added write_size to control_logic_r parameters. 2019-07-05 11:40:02 -07:00
mrg f542613d78 Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
mrg bfe4213fce Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
mrg 4c6556f1bc Add port address module 2019-07-05 09:04:48 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
mrg dd62269e0b Some cleanup 2019-07-05 08:18:58 -07:00
jsowash 02a0cd71ac fixed merge conflict 2019-07-04 11:14:32 -07:00
jsowash 125112b562 Added wmask flip flop. Need work on placement still. 2019-07-04 10:34:14 -07:00
mrg 3176ae9d50 Fix pnand2 height in bank select. Unsure how it passed before. 2019-07-03 15:12:22 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
jsowash 474ac67af5 Added optional write_size and wmask. 2019-07-03 10:14:15 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
mrg 2abe859df1 Fix shared bank offset. 2019-07-01 16:29:59 -07:00
jsowash 67c6cdf3bb Fixed error where word_size was compared to num_words and added write_size to control_logic.py 2019-07-01 15:51:40 -07:00
Bin Wu 9ce968b446 megre with dev changes 2019-06-30 00:50:18 -07:00
Bin Wu 1fcb20f846 clean pex test based on feedback 2019-06-30 00:16:04 -07:00
jsowash 242771f710 Merge branch 'dev' into add_wmask 2019-06-28 15:44:27 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Hunter Nichols 3f5b60856a Fixed key error with analytical delay of write ports. 2019-06-28 13:49:04 -07:00
Hunter Nichols ce7e320505 Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 4f3340e973 Cleaned up graph additions to characterizer. 2019-06-25 16:37:35 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Bin Wu 8e5fa7c7ae fix the run_pex function for calibre 2019-06-25 15:06:07 -07:00
Hunter Nichols 04ce3d5f45 Split control logic into different tests to avoid factory errors. 2019-06-25 14:55:28 -07:00
Bin Wu 9ef2616d41 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-06-25 11:28:04 -07:00
Bin Wu 3f3ee9b885 add pex function for magic and openram test 2019-06-25 11:24:25 -07:00
jsowash 3bd69d2759 Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
Bin Wu 91febec3a2 add hspice and ngspice pex tests 2019-06-25 09:19:37 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
mrg 5c4df2410e Fix dummy row LVS issue 2019-06-14 15:06:04 -07:00
mrg d35f180609 Add dummy row 2019-06-14 15:05:14 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
mrg b67f06a65a Add replica column for inclusion in replica bitcell array 2019-06-14 12:15:16 -07:00
mrg d8baa5384d Remove useless comments. Add missing copyright. 2019-06-14 10:13:13 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg 8418aea95a Revert height to width 2019-06-03 15:36:14 -07:00
mrg 58f51b72f1 Merge fixes 2019-06-03 15:31:49 -07:00
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
mrg bd4d965e37 Begin single layer supply router 2019-06-03 15:27:37 -07:00
mrg 4612c9c182 Move power pins before no route option 2019-06-03 15:27:37 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 1268a7927b Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-06-03 15:27:37 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
mrg bf86969972 Create sram subdirectory. 2019-05-31 08:56:24 -07:00
Hunter Nichols 36214792eb Removed some debug measurements that were causing failures. 2019-05-28 17:04:27 -07:00
Hunter Nichols ad229b1504 Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking. 2019-05-28 16:55:09 -07:00
mrg 72f4a223c3 Move power pins before no route option 2019-05-27 16:38:47 -07:00
mrg c2cc901300 Add boundary to every module and pgate for visual debug. 2019-05-27 16:32:38 -07:00
mrg e738353b5c Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-05-27 16:19:29 -07:00
Hunter Nichols e2d1f7ab0a Added smarter name checking for the characterizer. 2019-05-27 13:08:59 -07:00
mrg 26146b6838 Fix SCN3ME_SUBM stuff. 
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-05-26 22:28:16 -07:00
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols 412f9bb463 Added additional check to bitline to reduce false positives. 2019-05-17 01:56:22 -07:00
Hunter Nichols 03a762d311 Replaced constant string comparisons with enums 2019-05-16 14:18:33 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols a80698918b Fixed test issues, removed all bitcells not relevant for timing graph. 2019-05-15 17:17:26 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols b30c20ffb5 Added graph creation to characterizer, re-arranged pin creation. 2019-05-14 01:15:50 -07:00
Hunter Nichols b4cce65889 Added incorrect read checking in characterizer. 2019-05-13 19:38:46 -07:00
mrg 3fa8c5543a Merge branch 'dev' into scn3me_subm 2019-05-08 17:52:38 -07:00
mrg a5ed9b56cd Optional m4 in design class 2019-05-08 17:51:38 -07:00
Matt Guthaus c24879162a Add back scn3me_subm tech files 2019-05-08 16:06:21 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Hunter Nichols 5bfc42fdbb Added quality improvements to graph: improved naming, auto vdd/gnd removal 2019-04-29 23:57:25 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 978ba9d2f2 Refactor run scripts. 
Run DRC, LVS, and PEX share a run_*.sh script.
 2019-04-26 15:43:46 -07:00
Matt Guthaus 946a0aca86 Simplify DRC and LVS run scripts. 
Modified run scripts to work on local only files in the temp
directory. This assumes the files and subckts are named the
same as the clel name. Script now copies library files
to the temp directory as well.
 2019-04-26 15:17:39 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 9cead23f22 Add hierarchy to netgen LVS command. 2019-04-26 13:46:34 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Jesse Cirimelli-Low e507fbd5e9 Merge branch 'datasheet_gen' into dev 2019-04-26 12:29:37 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols f35385f42a Cleaned up names, added exclusions to narrow paths for analysis. 2019-04-24 23:51:09 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus 59d2e45744 Move characterization on/off feedback to report_status. 2019-04-24 11:30:38 -07:00
Matt Guthaus 7f5e6dd6f8 Fix unconnected supply pin bug in supply router. 
Simplified some of the supply router pin groups so that it assumes
each group is fully connected. When computing enclosures of the
pins on the routing grid, it will remove disconnected enclosure
shapes to keep things connected.
 2019-04-24 10:54:22 -07:00
Matt Guthaus 66c703d932 Simplify router code to clean it up a bit. 2019-04-22 15:30:35 -07:00
Matt Guthaus 5b828f32cb Create auxiliary run_drc.sh and run_lvs.sh with arguments for calibre 2019-04-22 15:12:59 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Jesse Cirimelli-Low 49e5f97eb4 fixed bug where log would fail to generate if output folder did not exist 2019-04-17 15:02:10 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus a35bf29bdd Improve print output for debugging layout objects. 2019-04-17 13:41:17 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols c1411f4227 Applied quick corner estimation to analytical delay. 2019-04-09 12:26:54 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus df4e2fead8 Return empty set instead of a list. 2019-04-01 15:59:57 -07:00
Matt Guthaus 07ecf52b9f Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
Matt Guthaus 5f37677225 Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 50d3b4cb8d Added some bitline measures to the model_checker 2019-03-19 15:03:57 -07:00
Matt Guthaus 95d96bd45d Add OPENRAM_TMP environment check 2019-03-08 11:12:30 -08:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 196710ec3e Remove factory from lef and verilog tests 2019-03-08 09:22:48 -08:00
Matt Guthaus bd256d33d6 Remove syntax error 2019-03-08 08:35:18 -08:00
Matt Guthaus 7129f79dc4 Merge remote-tracking branch 'origin' into tech_reorg 2019-03-08 08:33:46 -08:00
Matt Guthaus d8f64500e6 Remove factory create from lib tests so that we can give required name 2019-03-08 08:31:26 -08:00
Hunter Nichols e39f9ee481 Merge branch 'dev' into multiport_characterization 2019-03-07 12:31:14 -08:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Jesse Cirimelli-Low e6311dd44a Merge branch 'datasheet_gen' into dev 2019-03-06 23:47:19 -08:00
Jesse Cirimelli-Low 4754e6851d add_db takes commline line argv for path 2019-03-06 22:21:05 -08:00
Jesse Cirimelli-Low c1770036ac made the add_db code much simpler 2019-03-06 22:20:34 -08:00
Jesse Cirimelli-Low 83e810f8b8 added sorting to deliverables output 2019-03-06 21:12:21 -08:00
Jesse Cirimelli-Low fac9ff9be6 changed add_db.py to uncommenting method 2019-03-06 20:59:52 -08:00
Matt Guthaus 95137a2c26 Wrap debug line 2019-03-06 14:24:24 -08:00
Matt Guthaus 77229d5121 Reduce verbosity 2019-03-06 14:24:18 -08:00
Matt Guthaus c4c844a8a2 Remove duplicate module name checking since we use the factory 2019-03-06 14:14:46 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus acf2798a18 Add link to presentation in README 2019-03-06 08:29:43 -08:00
Matt Guthaus cfc14f327e Factor default corner out of import_tech 2019-03-06 07:46:30 -08:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 7e67b741f6 Merge branch 'dev' into multiport_characterization 2019-03-04 00:43:03 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus fb7264bae2 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-28 08:44:18 -08:00
Jesse Cirimelli-Low 3802c537e5 added add_db.py to add .db files to datasheets 2019-02-27 22:20:06 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus f865e66181 Remove git_id file 2019-02-25 16:47:38 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus c79b97eb51 Merge remote-tracking branch 'origin/dev' into multiport 2019-02-25 15:46:39 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus 638afaeb31 Remove duplicate profile stats script 2019-02-25 10:14:02 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Jesse Cirimelli-Low 34294443d4 updated logos and css for official colors 2019-02-25 07:46:34 -08:00
Jesse Cirimelli-Low 677588290d merging with dev now that it is passing 2019-02-25 07:05:06 -08:00
Matt Guthaus a210fdda0f Fix arguments for none verification 2019-02-24 10:49:35 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract. 2019-02-24 07:26:21 -08:00
Jesse Cirimelli-Low b9525e0f9e Merge branch 'dev' into datasheet_gen 2019-02-23 15:45:51 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Jesse Cirimelli-Low 8c9c910855 Merge branch 'datasheet_gen' into dev 2019-02-22 11:41:03 -08:00
Jesse Cirimelli-Low ff09254590 fixed analytical flag 2019-02-22 08:19:54 -08:00
Jesse Cirimelli-Low 0cabee060d fixed area rounding 2019-02-22 06:57:54 -08:00
Jesse Cirimelli-Low b4f1d53a1b fixed DRC datasheet error 2019-02-22 06:46:28 -08:00
Matt Guthaus d043c72277 Fix temp name error in openram.py 2019-02-21 11:16:21 -08:00
Matt Guthaus bb408d0a45 Add missing / in output path for log 2019-02-21 10:23:30 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low 723ec9925f Merge branch 'datasheet_gen' into dev 2019-02-15 21:47:24 -08:00
Jesse Cirimelli-Low d533a8ae26 fixed logger typo 2019-02-15 21:45:05 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Jesse Cirimelli-Low 3f761afcbc Merge branch 'datasheet_gen' into dev 2019-02-13 17:43:31 -08:00
Matt Guthaus d4c21cd26e Remove extraneous character. 2019-02-13 17:41:33 -08:00
Matt Guthaus 2553439447 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2019-02-13 17:01:41 -08:00
Matt Guthaus c359bbf42a Fix deprecation warnings in regex by converting to raw strings. Add error if unable to find DRC errors in Magic. 2019-02-13 17:01:26 -08:00
Jesse Cirimelli-Low e890c0e188 fixed -v logging 2019-02-13 15:21:16 -08:00
Hunter Nichols 4faec52409 Allowed data collection and analysis to run independently. 2019-02-12 20:58:50 -08:00
Hunter Nichols a4bb481612 Added tracking for available data. 2019-02-12 16:28:37 -08:00
Jesse Cirimelli-Low 36d8d98b17 Merge branch 'dev' into datasheet_gen 2019-02-08 12:05:04 -08:00
Hunter Nichols 9e23e6584a Made variance plot look slightly better. 2019-02-07 15:30:47 -08:00
Hunter Nichols 5e9851c5f1 Merge branch 'dev' into multiport_characterization 2019-02-07 14:31:26 -08:00
Hunter Nichols ebf43298c0 Added mean/variance plotting 2019-02-07 14:26:48 -08:00
Matt Guthaus d9efb682dd Do not clean up if preserve temp in local_drc_check 2019-02-07 11:08:34 -08:00
Jesse Cirimelli-Low bfc20a9aa9 removes debug corners 2019-02-07 06:38:07 -08:00
Jesse Cirimelli-Low be4b7697cb Merge branch 'dev' into datasheet_gen 2019-02-07 06:35:57 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Hunter Nichols d0edda93ad Added more variance analysis for the delay data 2019-02-07 02:27:22 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Hunter Nichols 690055174d Fixed bug in control logic test with port configs. 2019-02-06 20:09:01 -08:00
Hunter Nichols 56e79c050b Changed test values to fix tests. 2019-02-06 15:27:29 -08:00
Hunter Nichols 01c8405d12 Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Jesse Cirimelli-Low 374e7a31eb Merge branch 'dev' into datasheet_gen 2019-02-05 17:14:58 -08:00
Hunter Nichols e3d003d410 Adjusted test values to account for recent changes. 2019-02-05 00:43:16 -08:00
Hunter Nichols 543e0a1b9a Merge branch 'dev' into multiport_characterization 2019-02-04 23:54:16 -08:00
Hunter Nichols 12723adb0c Modified some testing and initial delay chain sizes. 2019-02-04 23:38:26 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Hunter Nichols 8d7823e4dd Added delay ratio comparisons between model and measurements 2019-01-31 00:26:27 -08:00
Jesse Cirimelli-Low 475db65d26 added units to AREA on datasheet 2019-01-30 17:49:43 -08:00
Matt Guthaus ec1fb087b5 Check membership of keys without using keys() list 2019-01-30 13:02:34 -08:00
Hunter Nichols 45fceb1f4e Added word per row to sram config with a default arguement to fix test. 2019-01-30 11:43:47 -08:00
Matt Guthaus 74fbe8fe63 Convert source and target lists to sets for faster contains check. 2019-01-30 11:15:47 -08:00
Matt Guthaus 07f4d639eb Remove non-rectangular error and just skip them. 2019-01-30 10:25:01 -08:00
Matt Guthaus 7836929db2 Use hash of tuples instead of checking rectangle in list 2019-01-30 10:03:07 -08:00
Matt Guthaus aaf028cacf Optimize hpwl runtime. Fix error in via cost when L shape. 2019-01-30 08:49:47 -08:00
Matt Guthaus 82a09be026 Move inspect into if statement for runtime 2019-01-30 08:42:25 -08:00
Hunter Nichols c10c9e4009 Refactored some code and other additional improvements. 2019-01-29 23:02:28 -08:00
Hunter Nichols 242a63accb Fixed issues introduced by pdriver additions in model unit test 2019-01-29 16:43:30 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 1bdf4dbe4f Re-enable abort on supply error. 2019-01-28 17:07:38 -08:00
Matt Guthaus 47a3dfafee Merge branch 'driver_sizing' into dev 2019-01-28 15:12:01 -08:00
Matt Guthaus f84dc3cadc Fix hspice delay golden results 2019-01-28 10:39:09 -08:00
Jesse Cirimelli-Low ed901aba5f changed datetime to date 2019-01-28 10:29:27 -08:00
Matt Guthaus d77bba3af2 Fix clock fanout to include internal FF. Update delays in golden tests. 2019-01-28 08:48:32 -08:00
Matt Guthaus 881c449c7c Fix error in offset computation for right drivers 2019-01-28 07:53:36 -08:00
Matt Guthaus c4438584fe Move jog for wl to mid-cells rather than mid-pins. 2019-01-27 12:59:02 -08:00
Matt Guthaus 18805423e3 Simplify pdriver code. 2019-01-25 17:18:12 -08:00
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 01ab253925 Move gdsMill license to README 2019-01-25 15:56:12 -08:00
Matt Guthaus d2864370aa Temporarily disable abort on supply error 2019-01-25 15:43:57 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 0c3baa5172 Added some comments to the spice files. 2019-01-25 15:00:00 -08:00
Matt Guthaus 1afd4341bd Update stage effort of clk_buf_driver 2019-01-25 14:22:37 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Hunter Nichols ee03b4ecb8 Added some data variation checking 2019-01-24 09:25:09 -08:00
Jesse Cirimelli-Low 65c5cc9fe7 added support for more corner variations 2019-01-24 07:09:51 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Hunter Nichols d527b7da62 Added delay error calculations 2019-01-23 13:19:35 -08:00
Matt Guthaus 8a85d3141a Fix polarity problem. 2019-01-23 13:08:43 -08:00
Matt Guthaus d64d262d78 Fix pdriver instantiation. Change sizes based on word_size. 2019-01-23 12:51:28 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Jesse Cirimelli-Low ac17e71973 removed debug print statement 2019-01-22 15:47:16 -08:00
Jesse Cirimelli-Low 886dd4d313 Merge branch 'dev' into datasheet_gen 2019-01-22 15:24:44 -08:00
Jesse Cirimelli-Low 978990f4dd cleaned up debug.py edits 2019-01-22 15:24:38 -08:00
Matt Guthaus 23718b952f Check for print statements in more files since we now use print_raw 2019-01-18 10:16:55 -08:00
Matt Guthaus f5f27073be Merge remote-tracking branch 'origin/dev' into factory 2019-01-18 09:52:18 -08:00
Hunter Nichols 5885e3b635 Removed carriage returns, adjusted signal names generation for variable delay chain size. 2019-01-18 00:23:50 -08:00
Yusu Wang c20fb2a70e replace matrix to array 2019-01-17 12:01:08 -08:00
Hunter Nichols 4ced6be6bd Added data collection and some initial data 2019-01-17 09:54:34 -08:00
Hunter Nichols 5bbc43d0a0 Added data collection of wordline and s_en measurements. 2019-01-17 01:59:41 -08:00
Jesse Cirimelli-Low 9c8090d94b added debug.info to logging 2019-01-16 19:56:23 -08:00
Matt Guthaus 7a152ea13d Move sram_factory to root dir 2019-01-16 17:06:29 -08:00
Matt Guthaus 9ecfaf16ea Add the factory class 2019-01-16 17:04:28 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Jesse Cirimelli-Low 25b0da404f removed EOL error in comment 2019-01-16 16:08:41 -08:00
Jesse Cirimelli-Low 41b8e8665b updated datasheet descriptors 2019-01-16 15:43:08 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Jesse Cirimelli-Low 192c615a38 moved library page to new repo 2019-01-16 07:33:17 -08:00
Hunter Nichols cc0be510c7 Added some data scaling and error calculation in model check. 2019-01-16 00:46:24 -08:00
Jesse Cirimelli-Low 813a551691 comment parsing 1/2 complete; page gen setup complete 2019-01-15 20:48:20 -08:00
Jesse Cirimelli-Low 903cafb336 html parsing finished 2019-01-15 19:47:48 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Jesse Cirimelli-Low b66c53a99a added log file to datasheet 2019-01-13 15:02:13 -08:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 20b869f8e1 Remove tabs 2019-01-11 14:16:57 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Hunter Nichols 21663439cc Added slews measurements to the model checker. Removed unused code in bitline delay class. 2019-01-09 22:42:34 -08:00
Jesse Cirimelli-Low a25e0f6c8c Merge branch 'dev' into datasheet_gen 2019-01-09 13:48:43 -08:00
Matt Guthaus cdef5f0ecb Change kbits to bits in output 2019-01-09 16:57:12 -08:00
Matt Guthaus be9f81768d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-01-09 15:20:34 -08:00
Matt Guthaus 94a6cbc28b Remove extra bracket in pin blokc 2019-01-09 13:44:25 -08:00
Jesse Cirimelli-Low b0978e62f3 removed openram placeholder logo to stage for public push 2019-01-09 12:32:17 -08:00
Matt Guthaus 49d0b9d69c Remove old scn3me golden results. Remove indices from new golden results. 2019-01-09 12:04:17 -08:00
Matt Guthaus fe077a453a Change capitalization of message to be consistent 2019-01-09 12:00:14 -08:00
Matt Guthaus 7e635d02be Remove indices from pins in lib file 2019-01-09 12:00:00 -08:00
Matt Guthaus 4d0a8b9c8a Check for coverage executable and run without if not found. 2019-01-09 08:24:20 -08:00
Jesse Cirimelli-Low e9b8eab2c3 Merge branch 'dev' into datasheet_gen 2019-01-09 06:16:09 -08:00
Jesse Cirimelli-Low 8b8985dbd1 track table_gen 2019-01-09 06:15:22 -08:00
Jesse Cirimelli-Low 3f8628fa94 flask totally purged, fixed table headers 2019-01-08 20:04:30 -08:00
Jesse Cirimelli-Low e58515b89b tables stable and flask removed, headers are bugged 2019-01-08 19:50:47 -08:00
Jesse Cirimelli-Low 6033cc604d stable, but incomplete flaskless table gen rewrite 2019-01-08 18:54:20 -08:00
Jesse Cirimelli-Low 19a986c35c no-flask rewrite for initial datasheet case complete 2019-01-07 19:43:57 -08:00
Jesse Cirimelli-Low 24161a1df2 Merge branch 'dev' into datasheet_gen 2019-01-07 18:18:46 -08:00
Jesse Cirimelli-Low 1283cbc3be fixed EOL error in descriptor 2019-01-07 18:17:38 -08:00
Jesse Cirimelli-Low 5508ae945d updated file html description to simplify parsing 2019-01-07 17:08:47 -08:00
Matt Guthaus 2236ca40df Make xa least priority since it fails functional tests. 2019-01-03 19:20:31 -08:00
Jesse Cirimelli-Low 6acc8c8902 removed print debug statement 2019-01-03 13:41:25 -08:00
Jesse Cirimelli-Low 53b7e46db4 fixed bug where retrieving git id would fail depending on cwd 2019-01-03 12:28:29 -08:00
Hunter Nichols 272267358f Moved all bitline delay measurements to delay class. Added measurements to check delay model. 2019-01-03 05:51:28 -08:00
Jesse Cirimelli-Low c69e5fdb18 added compile time to datasheet 2019-01-02 10:30:03 -08:00
Jesse Cirimelli-Low cc27736a45 moved DRC and LVS error reports to datasheet.info from datasheet.py 2019-01-02 10:14:45 -08:00
Hunter Nichols 66b2fcdc91 Added data parsing to measurement objects and adding power measurements. 2018-12-20 15:54:56 -08:00
Hunter Nichols b10ef3fb7e Replaced delay measure statement with object implementation. 2018-12-19 18:33:06 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols dc20bf9e11 Added bitline measurements to ngspice delay test. 2018-12-13 22:31:08 -08:00
Hunter Nichols e4065929c2 Added bitline threshold delay checks to delay tests. 2018-12-13 22:21:30 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Jennifer Eve Sowash bc44c80d40 Added height to init in pdriver.py 2018-12-13 19:03:31 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Hunter Nichols 50f13eabce Added better port selection to bitline measurements. 2018-12-12 15:59:20 -08:00
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
Hunter Nichols 6ac474d642 Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
Hunter Nichols 82e074ebf0 Added initial structure for bitline measurements. 2018-12-11 14:06:11 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Matt Guthaus 37c10a2198 Merge branch 'supply_routing' into dev 2018-12-07 17:04:37 -08:00
Matt Guthaus b15584a821 Print start time after banner and init 2018-12-07 15:50:18 -08:00
Hunter Nichols 4d84731c34 Edited heuristic delay chain and delay model to account for read port differences. 2018-12-07 15:39:53 -08:00
Matt Guthaus 3f468b1c18 Only print_time when not a unit test or debug_level set 2018-12-07 15:14:28 -08:00
Jennifer Eve Sowash d302f1cd0a Merge branch 'pdriver' into dev 2018-12-07 14:37:25 -08:00
Matt Guthaus 5248482fab Merge branch 'dev' into supply_routing 2018-12-07 14:28:49 -08:00
Matt Guthaus 6f171ad147 Added router timing code. Commented combine adjacent pins due to run-time complexity 2018-12-07 13:54:18 -08:00
Matt Guthaus 5ed9904855 Cast dict_values to a list for pin_groups 2018-12-07 13:02:50 -08:00
Jennifer Eve Sowash a6eec10f41 Passed freepdk45 tests with pdriver.py 2018-12-07 12:58:05 -08:00
Matt Guthaus dfb2cf3cbd Change analyze_pins to a heuristic algorithm less than O(n^2) 2018-12-07 12:41:32 -08:00
Jennifer Eve Sowash a24e5229cb Fixed method of determining inverter number. 2018-12-07 10:19:18 -08:00
Matt Guthaus a96f492d0a Add profile scripts 2018-12-07 08:56:40 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 5319107afa Skip pdriver test until LVS fix 2018-12-07 07:41:35 -08:00
Matt Guthaus d38d5a6d58 Merge branch 'supply_routing' into dev 2018-12-07 07:39:53 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Matt Guthaus 537e0689fb Add combine adjacent pins back 2018-12-06 14:29:06 -08:00
Matt Guthaus c51752d245 Provide more stats in -v output 2018-12-06 14:11:15 -08:00
Matt Guthaus 514f6fda27 Increase size for warning of column mux limit 2018-12-06 13:57:38 -08:00
Matt Guthaus 3f1fbc3d90 Merge remote-tracking branch 'origin' into supply_routing 2018-12-06 13:53:51 -08:00
Matt Guthaus c0295a2c3d Rewrite if/else to be correct and more legible. 2018-12-06 13:23:39 -08:00
Matt Guthaus 46d3068821 Output number of words per row before SRAM creation. Recompute words per row in unit tests. 2018-12-06 13:11:47 -08:00
Matt Guthaus 6f1af4d0c9 Remove extraneous m2m3 via that causes DRC 2018-12-06 12:45:45 -08:00
Matt Guthaus b5a7274316 Change Netlisting to submodules to reflect what time is of 2018-12-06 11:59:20 -08:00
Matt Guthaus e4c67875d2 Add non-minimum width metal2 in route when vias can be close 2018-12-06 11:58:57 -08:00
Matt Guthaus b7bbc9b994 Add output on number of ports. 2018-12-06 11:58:34 -08:00
Matt Guthaus b72382b400 Fix offset bug with negative vertical supply rails 2018-12-06 11:58:19 -08:00
Jesse Cirimelli-Low afb32ed834 removed outdated 'unknown' for analytical frequency 2018-12-06 10:29:48 -08:00
Jesse Cirimelli-Low bf27eb8cd6 removed placeholder data 2018-12-06 10:17:12 -08:00
Jesse Cirimelli-Low 1633ae0265 base64 encode images for portability 2018-12-06 10:13:28 -08:00
Jesse Cirimelli-Low 02b4b13cc4 fixed config file path 2018-12-06 09:26:38 -08:00
Jesse Cirimelli-Low e41b90449d specify config file abs path 2018-12-06 05:34:05 -08:00
Hunter Nichols b157fc58a1 Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 448e8f4cfd Merged with dev 2018-12-05 17:49:42 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Matt Guthaus 7645a909eb Merge branch 'supply_routing' into dev 2018-12-05 17:24:51 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Jesse Cirimelli-Low 1dae539e1d track git_id 2018-12-05 16:13:52 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low 32bd91aafd track ORIG_HEAD file 2018-12-05 13:39:54 -08:00
Jesse Cirimelli-Low 7a20420030 get ORIG_HEAD with pre-commit hook 2018-12-05 13:38:09 -08:00
Matt Guthaus 2cd1322071 Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
Matt Guthaus fa3bf2915a Remove commented code 2018-12-05 09:56:19 -08:00
Matt Guthaus 0c0a23e6eb Cleanup code. Add time breakdown for SRAM creation. 2018-12-05 09:51:17 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Matt Guthaus f1c74d6bfb Merge branch 'dev' into supply_routing 2018-12-04 17:57:18 -08:00
Matt Guthaus d95b34caf2 Round output to look pretty 2018-12-04 17:08:47 -08:00
Matt Guthaus e750d446dc Fix syntax error. Enable skipped test. 2018-12-04 17:08:22 -08:00
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo. 2018-12-04 16:53:04 -08:00
Jesse Cirimelli-Low b6e7ddd023 Merge branch 'dev' into datasheet_gen 2018-12-04 16:27:04 -08:00
Matt Guthaus 7ce75398a8 Change warning to info 2018-12-04 09:42:47 -08:00
Matt Guthaus 7fce6f06ca Expand grids to maximal pin before removing blockages 2018-12-04 09:35:40 -08:00
Matt Guthaus 389bb91af4 Simplifying supply router to single grid track 2018-12-04 08:41:57 -08:00
Matt Guthaus 2a68b57215 Changed psram info to sram 2018-12-03 15:59:31 -08:00
Jesse Cirimelli-Low 2c12ef2161 added warning to test 30 coverage is not installed 2018-12-03 13:24:22 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jesse Cirimelli-Low 71bb1bb9f1 updated test 30 to dev version 2018-12-03 11:09:45 -08:00
Matt Guthaus c6f03e70d4 Convert supply to wider DRC rules 2018-12-03 11:09:17 -08:00
Jesse Cirimelli-Low c869c7e870 added tracking to new debug files 2018-12-03 10:54:50 -08:00
Jesse Cirimelli-Low 5646660765 added git id to datasheet 2018-12-03 10:53:50 -08:00
Jesse Cirimelli-Low 9501b99df7 merged branch wtih dev 2018-12-03 09:47:34 -08:00
Jennifer Eve Sowash da631618b6 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-12-03 09:14:13 -08:00
Matt Guthaus bcc6b95564 Add coverage exclusions. Add subprocess coverage. 2018-12-03 09:13:57 -08:00
Jennifer Sowash 887674aa85 Added pdriver.py for testing. 2018-12-03 09:11:12 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 49f7022416 Skip failing tests with comments for bugs. 2018-11-30 12:33:43 -08:00
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Matt Guthaus 7e054a51e2 Some techs don't need m1 power pins 2018-11-29 18:47:38 -08:00
Matt Guthaus 0af4263edb Remove extra rotated vias in bitcell array to simplify power routing 2018-11-29 18:13:15 -08:00
Matt Guthaus 0e7301fff8 Update unit test golden results. Skip two tests. 2018-11-29 17:28:57 -08:00
Matt Guthaus e98f7075e2 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-29 16:29:17 -08:00
Matt Guthaus 33a7683473 Remove used gated_clk instead of cs for read-only control logic. 2018-11-29 16:28:37 -08:00
Matt Guthaus a7be60529f Do not rotate vias in horizontal channel routes 2018-11-29 13:57:40 -08:00
Matt Guthaus 3c4d559308 Fixed syntax error referring to column mux 2018-11-29 13:29:16 -08:00
Matt Guthaus 3d3f54aa86 Add col addr line spacing for col addr decoder 2018-11-29 13:22:48 -08:00
Matt Guthaus 4df862d8af Convert channel router to take netlist of pins rather than names. 2018-11-29 12:12:10 -08:00
Matt Guthaus a7bc9e0de0 Use module height not instance uy for sram placement 2018-11-29 10:34:25 -08:00
Matt Guthaus 0a16d83181 Add more layout and functional port tests. 2018-11-29 10:28:43 -08:00
Matt Guthaus 14fa33e21d Remove 4 bank code and test for now. 2018-11-29 10:28:09 -08:00
Matt Guthaus 7054d0881a Fix col address dff spacing from bank. 2018-11-29 09:54:29 -08:00
Matt Guthaus 02a67f9867 Missing gap in port 1 col decoder 2018-11-28 18:07:31 -08:00
Matt Guthaus d041a498f3 Fix height of port 1 control bus. Adjust column decoder names. 2018-11-28 17:48:25 -08:00
Jesse Cirimelli-Low a4b1d2f13b added css style code 2018-11-28 17:21:50 -08:00
Jesse Cirimelli-Low 06805d1e70 file browser does not show files in root directory; removed test file 2018-11-28 17:18:59 -08:00
Matt Guthaus f8513da162 Remove local temp dir 2018-11-28 17:04:53 -08:00
Matt Guthaus a2a9cea37e Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
Jesse Cirimelli-Low 79c4b3c4cd added files links 2018-11-28 16:56:24 -08:00
Matt Guthaus 3cfe74cefb Functional simulation uses threshold for high and low noise margins 2018-11-28 16:55:04 -08:00
Jesse Cirimelli-Low 44638cb885 jinja2 file browser working 2018-11-28 16:48:24 -08:00
Matt Guthaus 25ae3a5eae Fix error of no control bus width 2018-11-28 15:42:51 -08:00
Matt Guthaus d99dcd33e2 Fix SRAM level control routing errors. 2018-11-28 15:30:52 -08:00
Matt Guthaus 143e4ed7f9 Change hierchical decoder output order to match changes to netlist. 2018-11-28 14:09:45 -08:00
Matt Guthaus b5b691b73d Fix missing via in clk input of control 2018-11-28 13:20:39 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus 93904d9f2d Control logic passes DRC/LVS in SCMOS 2018-11-28 11:02:24 -08:00
Matt Guthaus 410115e830 Modify dff_buf to stagger Q and Qb outputs. 2018-11-28 10:43:11 -08:00
Matt Guthaus 25611fcbc1 Remove dff_inv since we can just use dff_buf 2018-11-28 10:42:22 -08:00
Matt Guthaus ea6abfadb7 Stagger outputs of dff_buf 2018-11-28 09:48:16 -08:00
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
Jesse Cirimelli-Low a56e3f609b removed debug print statements 2018-11-28 09:39:58 -08:00
Jesse Cirimelli-Low 0920321a2e start of static html generation code 2018-11-27 19:49:05 -08:00
Matt Guthaus c43a140b5e All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
Matt Guthaus 5d59863efc Fix p_en_bar at top level. Change default scn4m period to 10ns. 2018-11-27 14:44:55 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
Matt Guthaus 0c286d6c29 Revert to 5V example until we fix spice models in scn4m_subm 2018-11-27 14:17:06 -08:00
Jesse Cirimelli-Low 5aa8c46c16 Merge branch 'dev' into datasheet_gen 2018-11-27 13:54:21 -08:00
Matt Guthaus bf31126679 Correct decoder output numbers to follow address order 2018-11-27 12:03:13 -08:00
Matt Guthaus b912f289a6 Remove extra X in instance names 2018-11-27 12:02:53 -08:00
Matt Guthaus 2237af0463 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-26 18:01:34 -08:00
Matt Guthaus cf23eacd0e Add wl_en 2018-11-26 18:00:59 -08:00
Matt Guthaus 21759d59b4 Remove inverter in wordline driver 2018-11-26 16:41:31 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus dd79fc560b Corretct modules for add_inst 2018-11-26 15:35:29 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 2eff166527 Rotate vias in pand2 2018-11-26 14:05:04 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash 524334d24d Merge branch 'dev' into pdriver 2018-11-26 13:15:47 -08:00
Hunter Nichols b06aa84824 Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. 2018-11-23 18:55:15 -08:00
Hunter Nichols 5f954689a5 In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Jesse Cirimelli-Low 29f19ad70f replaced absolute links with relative links 2018-11-20 12:27:54 -08:00
Jesse Cirimelli-Low 7d070c2652 Added links to logos 2018-11-20 11:51:38 -08:00
Hunter Nichols 67977bab3e Fixed port issue in bank. Changed golden data due to netlist change. 2018-11-20 11:39:14 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 2f29ad5510 Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. 2018-11-19 22:13:58 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Hunter Nichols e8f1c19af6 Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Hunter Nichols e9f6566e59 Fixed merge conflict, moved control logic mod instantiation, removed some commented out code. 2018-11-14 13:53:27 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. 2018-11-13 22:24:18 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse 2018-11-13 17:29:43 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Matt Guthaus 01ceedb348 Only check number of ports when doing layout. 2018-11-13 16:42:25 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Matt Guthaus aa779a7f82 Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash b366d88041 Merge branch 'dev' into pdriver 2018-11-12 11:30:37 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00
Hunter Nichols 6f6d45f025 Merge branch 'dev' into multiport_characterization 2018-11-11 23:47:49 -08:00
Matt Guthaus 732f35a362 Change channel router to route from bottom up to simplify code. 2018-11-11 12:25:53 -08:00
Matt Guthaus 791d74f63a Fix wrong exception handling that depended on order. Replaced with if/else instead. 2018-11-11 12:02:42 -08:00
Jesse Cirimelli-Low 0dd97e54dd reverted css to UCSC colors, fixed header styling, added placeholder openram logo 2018-11-11 09:27:07 -08:00
Jesse Cirimelli-Low 4227a7886a Merge branch 'dev' into datasheet_gen 2018-11-11 07:27:42 -08:00
Jesse Cirimelli-Low 91a63fb5c2 Merge branch 'dev' 2018-11-11 07:24:03 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low aadf160ce4 added missing space in sheet 2018-11-11 06:05:14 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Matt Guthaus 65b6bfd5e7 Change os to shutils 2018-11-10 10:06:33 -08:00
Matt Guthaus 3b6b93e2ca Save gds file in testutils when fail to figure out randomness in regression CI 2018-11-10 10:05:27 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Hunter Nichols ea1a1c7705 Added delay chain resizing based on analytical delay. 2018-11-09 17:14:52 -08:00
Matt Guthaus 550d5cc729 Fix path to config file in test 30 2018-11-09 16:33:08 -08:00
Matt Guthaus de61630962 Expand blocked pins to neighbor grid cells. 2018-11-09 14:25:10 -08:00
Matt Guthaus c5b408ae2d Add router output message 2018-11-09 11:10:40 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus cc619084c7 Clean up psingle_bank_test 2018-11-09 09:34:34 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Matt Guthaus 6aff552c0a Merge branch 'multiport_layout' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-09 08:53:27 -08:00
Matt Guthaus 8f3fa0e2f6 Fix blocked pin debug output. 2018-11-09 08:52:05 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Jesse Cirimelli-Low d6c0247ff2 added area to datasheet 2018-11-08 21:30:17 -08:00
Jesse Cirimelli-Low 30bffdf1b4 Merge branch 'dev' into datasheet_gen 2018-11-08 19:26:00 -08:00
Matt Guthaus 9c8d5395ff Update leakage data for scn4m 2018-11-08 18:16:01 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5d684b02e0 Leakage changed in ngspice test. 2018-11-08 18:00:09 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Matt Guthaus d03c9d5294 Fix write bl name list in replica bitline 2018-11-08 17:02:20 -08:00
Matt Guthaus fd5cd675ac Horizontal increments top down. 2018-11-08 17:01:57 -08:00
Matt Guthaus 18fbf30b46 Convert col decoder select routing to channel route. 2018-11-08 16:53:58 -08:00
Matt Guthaus e28978180f Vertical channel routes go from left right. Horizontal go bottom up. 2018-11-08 16:49:02 -08:00
Matt Guthaus ef2ed9a92c Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
Matt Guthaus 5d733154e9 Refactor bank to allow easier multiport. 2018-11-08 15:18:51 -08:00
Matt Guthaus 7b10e3bfec Convert port index lists to three simple lists. 2018-11-08 12:19:40 -08:00
Matt Guthaus b25650eb07 Netlist only mode for ngspice delay test 2018-11-08 12:19:06 -08:00
Matt Guthaus dd5b2a5b59 Fix missing fail when non-list item doesn't match. 2018-11-08 12:16:59 -08:00
Michael Timothy Grimes 7c3375fd4b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-08 09:59:52 -08:00
Matt Guthaus 929eae4a23 Document why sense amp is 8x isolation transistor 2018-11-07 16:09:50 -08:00
Matt Guthaus 5dfba21acc Change tx mux size back to 8. Document why it was chosen. 2018-11-07 16:03:48 -08:00
Matt Guthaus 3d2abc0873 Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
Matt Guthaus ad7fe1be51 Clean up code formatting. 2018-11-07 14:52:03 -08:00
Matt Guthaus 4e232c49ad Update precharge cell for multiport. 
Comment out pbitcell tests.
Add bitcell_1rw_1r test.
Move bitcell horizontal routing to metal1.
Extend precharge height for stacking.
 2018-11-07 14:46:51 -08:00
Matt Guthaus 050035ae8d Add magic/netgen to example config 2018-11-07 13:54:00 -08:00
Matt Guthaus 2e5ae70391 Enable psram 1rw 2mux layout test. 2018-11-07 13:37:08 -08:00
Matt Guthaus f04e76a54f Allow multiple must-connect pins with the same label. 2018-11-07 13:05:13 -08:00
Matt Guthaus 8d753b5ac7 Primitive cells only keep the largest pin shape. 2018-11-07 11:58:31 -08:00
Matt Guthaus 1fe767343e Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
Jesse Cirimelli-Low 00dd6ddfd0 Merge branch 'dev' into datasheet_gen 2018-11-07 10:47:37 -08:00
Jesse Cirimelli-Low 781bd13cc1 Merge branch 'dev' into datasheet_gen 2018-11-07 10:08:45 -08:00
Matt Guthaus 485590052a Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-06 07:56:57 -08:00
Matt Guthaus 279fe4d103 Merge branch 'dev' into supply_routing 2018-11-06 07:56:29 -08:00
Matt Guthaus 86a8dca584 Merge branch 'dev' into supply_routing 2018-11-05 15:04:57 -08:00
Hunter Nichols ff169fcb2b Merged with dev, fixed config file conflict. 2018-11-05 14:58:52 -08:00
Hunter Nichols 4c26dede23 Unskipped functional tests and increases the number of ports on pbitcell functional tests. 2018-11-05 14:56:22 -08:00
Matt Guthaus 831e454b34 Remove redundant DRC run in magic. 2018-11-05 13:30:42 -08:00
Matt Guthaus 37b81c0af1 Remove options from example config files 2018-11-05 12:47:47 -08:00
Matt Guthaus 02bafb4757 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-11-05 12:44:46 -08:00
Hunter Nichols 9744bc516a Merge branch 'dev' into multiport_characterization 2018-11-05 10:40:29 -08:00
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
Michael Timothy Grimes 3c9821991b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-05 08:56:19 -08:00
Matt Guthaus 38dab77bfc Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
Matt Guthaus 5d2df76ef5 Skip 4mux test 2018-11-03 10:16:22 -07:00
Matt Guthaus 5ecfa88d2a Pad the routing grid by a few tracks to add an extra rail 2018-11-02 17:35:35 -07:00
Matt Guthaus a3666d82ab Reduce verbosity of level 1 debug. 2018-11-02 17:30:28 -07:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Hunter Nichols f05865b307 Fixed drc issues with replica bitline test. 2018-11-02 17:16:41 -07:00
Matt Guthaus f8e761313a Merge branch 'dev' into supply_routing 2018-11-02 16:39:49 -07:00
Matt Guthaus 852bfbc031 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2018-11-02 16:34:36 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Matt Guthaus ad1d3a3c78 Use default grid costs again. 2018-11-02 16:04:56 -07:00
Matt Guthaus 3950a9feff Merge branch 'supply_routing' into dev 2018-11-02 15:31:29 -07:00
Matt Guthaus 74c3de2812 Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Matt Guthaus 866eaa8b02 Add debug message when routes are diagonal. 2018-11-02 11:50:28 -07:00
Matt Guthaus 4d30f214da Add expanded blockages for paths an enclosures to handle wide metal spacing rules. 2018-11-02 11:11:32 -07:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Matt Guthaus 2eedc703d1 Rename function in pin_group 2018-10-31 16:13:28 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Jesse Cirimelli-Low c3d7e24df9 fixed broken links when -o flag set 2018-10-31 09:34:36 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Jesse Cirimelli-Low 5302fd205f fixed some final typos in datasheet 2018-10-30 23:03:05 -07:00
Jesse Cirimelli-Low 70ac2e8aa4 changed css to orange and black for Halloween; fixed CSb timing table in datasheet 2018-10-30 22:56:13 -07:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Jesse Cirimelli-Low 905f6f8b43 added docstring and renamed some functions 2018-10-30 21:37:30 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00
Matt Guthaus 7099ee76e9 Remove blocked grids from pins and secondary grids 2018-10-30 16:52:11 -07:00
Matt Guthaus 1344a8f7f1 Add remove adjacent feature for wide metal spacing 2018-10-30 12:24:13 -07:00
Matt Guthaus c4163d3401 Remove debug statements. 2018-10-29 13:50:56 -07:00
Matt Guthaus fa272be3bd Enumerate more enclosures. 2018-10-29 13:49:29 -07:00
Matt Guthaus cd87df8f76 Clean up enclosure code 2018-10-29 11:27:59 -07:00
Matt Guthaus f19bcace62 Merged in an old stash. 2018-10-29 11:18:12 -07:00
Matt Guthaus b7655eab10 Remove bug for combining pin with multiple other pins in a single iteration 2018-10-29 11:07:02 -07:00
Matt Guthaus bbffec863b Abandon connectors for now and opt for all enclosures 2018-10-29 10:59:22 -07:00
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts. 2018-10-29 10:32:42 -07:00
Matt Guthaus 851aeae8c4 Add pins_enclosed function to pin_group 2018-10-29 10:28:57 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Jesse Cirimelli-Low f1fb174b53 fixed bug where netlist_only still produced layout deliverables 2018-10-27 11:21:06 -07:00
Hunter Nichols 3bb8aa7e55 Fixed import errors with mux analytical delay model. 2018-10-26 17:37:25 -07:00
Matt Guthaus 0107e1c050 Reduce verbosity of utils 2018-10-26 13:02:31 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
Jesse Cirimelli-Low fcfee649d5 moved css into a seperate file to organize and disambiguate docstrings from multiline strings 2018-10-26 07:57:54 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 9e5d78cfc2 Fix bug in duplicate remove indices 2018-10-25 14:40:39 -07:00
Matt Guthaus 3407163cf1 Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00
Matt Guthaus 0544d02ca2 Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00
Matt Guthaus 3f17679000 Merge remote-tracking branch 'origin' into supply_routing 2018-10-25 09:36:03 -07:00
Matt Guthaus 57fb847d50 Fix check for missing simulator type in characterizer 2018-10-25 09:08:56 -07:00
Matt Guthaus 3d8aeaa732 Run delay and setup/hold tests in netlist_only mode 2018-10-25 09:07:00 -07:00
Matt Guthaus 58de655aac Split functional tests 2018-10-25 08:56:23 -07:00
Michael Timothy Grimes 3202e1eb09 Altering comment code in simulation.py to match the needs of delay.py 2018-10-25 00:58:01 -07:00
Michael Timothy Grimes 40450ac0f5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-25 00:36:46 -07:00
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
Matt Guthaus b1f3bd97e5 Enable all the 1bank tests. Mostly work in SCMOS. 2018-10-24 17:01:00 -07:00
Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections. 2018-10-24 16:41:33 -07:00
Matt Guthaus 94e5050513 Move overlap functions to pin_layout 2018-10-24 16:13:07 -07:00
Matt Guthaus dc73e8cb60 Odd bug that instances were not properly rotated. 2018-10-24 16:12:27 -07:00
Matt Guthaus 7e2bef624e Continue routing rails in same layer after a blockage 2018-10-24 12:32:27 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus cccde193d0 Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
Matt Guthaus 5f17525501 Added run-level option for write_control and enabled fast mode in functional tests 2018-10-24 09:32:44 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Matt Guthaus e90f9be6f5 Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Michael Timothy Grimes 2053a1ca4d Improved debug comments for functional test 2018-10-22 01:09:38 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 38a8c46034 Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 5276943ba2 Remove temp log file 2018-10-20 14:26:30 -07:00
Matt Guthaus 4c25bb09df Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
Matt Guthaus f5e68c5c32 Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias. 2018-10-20 12:54:12 -07:00
Matt Guthaus f9738253c6 Remove warning of track space and floor the space function. 2018-10-20 11:53:52 -07:00
Matt Guthaus a1f2a5befe Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 233a1425e4 Flatten bitcell array in netgen for now. See issue 52 2018-10-19 09:13:17 -07:00
jcirimel 74b806fa38
Merge pull request #54 from VLSIDA/datasheet_gen 
flask_table check fix
 2018-10-18 15:12:04 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Michael Timothy Grimes a06a0975db Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails 2018-10-15 13:58:40 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus a165446fa7 First implementation of multiple track spacing wide DRCs in routing grid. 2018-10-15 11:25:51 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Matt Guthaus 5e9fe65907 Remove banks from example configs 2018-10-12 10:23:34 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
Jesse Cirimelli-Low 50cc8023a4 deleted output file left in previous commit 2018-10-11 16:04:43 -07:00
Jesse Cirimelli-Low 35e0ba6fc4 fixed merge error 2018-10-11 16:03:05 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low d142136735 rewrite of redirected print statements to file write 2018-10-11 12:09:50 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Matt Guthaus 297ea81060 Change RBL size to 50% of row size. 2018-10-11 10:39:24 -07:00
Matt Guthaus 1333329dd4 Merge branch 'multiport' into supply_routing 2018-10-11 10:37:10 -07:00
Matt Guthaus f7d1df6ca7 Fix trim spice with new names 2018-10-11 10:36:49 -07:00
Matt Guthaus e759c9350b Skip psram 1 bank 2018-10-11 10:17:50 -07:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Hunter Nichols f30e54f33c Cleaned up indexing in variable that records cycle times. 2018-10-10 00:02:03 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols a3bec5518c Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test. 2018-10-09 00:36:14 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Jesse Cirimelli-Low 49268b025f fixed /tmp/ typo 2018-10-06 21:17:26 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 83fd2c0512 Fix openram_temp directory 2018-10-06 08:08:01 -07:00
Matt Guthaus 94ab69ea16 Supply router working, perhaps not efficiently though. 2018-10-05 15:57:34 -07:00
Matt Guthaus eb2304944b Fix .magicrc file name 2018-10-05 08:48:25 -07:00
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets. 2018-10-05 08:39:28 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 19114fe47f Add commented extraction when running DRC only 2018-10-05 08:18:53 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Matt Guthaus c3cd76048b Removed prints. Fixed offset for single track enclosure. 2018-10-04 14:44:25 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols bb79d9a62d Added regex pattern matching to trim_spice to handle multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes cf4b216888 Correcting functional inheritance from simulation. 2018-10-04 13:55:59 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Matt Guthaus a7246f5e7f Rename omits 0 size ports 2018-09-24 13:44:31 -07:00
Matt Guthaus 9b0142d6b9 Comment debug for possible performance issue 2018-09-24 11:44:32 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Matt Guthaus 2df9b79b28 Remove scn3me lib files. Remove bank references. 2018-09-24 11:28:43 -07:00
Matt Guthaus 7432192e5e Small change to test webhook 2018-09-24 09:11:44 -07:00
Matt Guthaus 922e3f4c13 Small change to test webhook 2018-09-21 15:05:46 -07:00
Matt Guthaus ade12c9dc2 Small change to test webhook 2018-09-21 15:03:16 -07:00
Matt Guthaus e1864a7a1e Small change to test webhook 2018-09-21 15:02:16 -07:00
Matt Guthaus 2b3b4bbee6 Small change to test webhook 2018-09-21 15:01:07 -07:00
Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port 2018-09-21 09:59:44 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Michael Timothy Grimes 2641841e4c Making correction to replica bitline netlist for multiport 2018-09-20 15:21:22 -07:00
Michael Timothy Grimes 938ded3dd6 Adding functional test to characterizer and unit tests in both single and multiport 2018-09-20 15:04:59 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus fd9ffe30d6 Add layer width options to route object 
Modify router to use track-width routes.
 2018-09-18 15:12:53 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus bfc8428df7 Convert router tests to scn4m_subm 2018-09-17 13:30:30 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Michael Timothy Grimes 43f5316eed Correcting format of replica_pbitcell. 2018-09-13 18:51:52 -07:00
Michael Timothy Grimes 9acc8a9532 Altering multiport checks across several unit tests. 2018-09-13 18:49:20 -07:00
Michael Timothy Grimes 332976dd73 s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules. 2018-09-13 18:46:43 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus e591176211 Change default to scn4m 2018-09-13 15:26:03 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 571dca5d5f Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus 849293b95b Converting grid data structures to sets to reduce size. 2018-09-13 09:10:29 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes f03cd7c3ba Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. 2018-09-12 20:22:12 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes 7dfd37f79c Altering control logic for multiport. Netlist changes only. 2018-09-12 00:59:07 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols ac3cc5c79b Merge branch 'dev' into multiport_characterization 2018-09-11 16:01:51 -07:00
Matt Guthaus a3c2b4384a Improve comments. Simplify function interface for channel route. 2018-09-11 15:53:12 -07:00
Hunter Nichols 676b6764c7 Merge branch 'dev' into multiport_characterization 2018-09-11 15:40:17 -07:00
Matt Guthaus 3587f90e94 Fix copy pasta error in create vertical channel route 2018-09-11 14:47:55 -07:00
Matt Guthaus 5e34233479 Finish new VCG testing. 
Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
 2018-09-11 14:24:13 -07:00
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus add0e3ad68 Add none option for verify wrapper with warning messages. 2018-09-11 10:17:24 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 0cdd3b99bf Generalized wl names using bitcell's list_all_wl_names function to accomodate multiport 2018-09-09 22:42:52 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes 252ae1effa add trailing 0 to web 2018-09-09 15:16:53 -07:00
Michael Timothy Grimes 68c00d7467 Removing din and dout list names in exchange for a read index. Write ports will always be in order (they will not skip numbers. Read ports however will skip the numbers assigned to wirte ports so the index of the read ports must be tracked. 2018-09-09 14:14:26 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Matt Guthaus 2d86492d91 Working on methodology of blockages, pins, and routing multiple pins. 2018-09-08 18:55:36 -07:00
Matt Guthaus 96c51f3464 Component shape functions. Find connected pins through overlaps. 2018-09-08 10:05:48 -07:00
Hunter Nichols 5cab786e21 Cleaned up analyze and some of its helper functions to be less cluttered. 2018-09-07 17:50:09 -07:00
Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. 
Refactored grid path class.
Added direction enum.
Does not route multi-track width wires in signal router.
 2018-09-07 14:46:58 -07:00
Hunter Nichols 83f6434476 Gave find_feasible_period a port input. 2018-09-07 00:53:11 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00