4 Commits

Author	SHA1	Message	Date
jcirimel	1e7ae06b7e	fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end	2020-10-08 05:32:03 -07:00
jcirimel	d40c3588ed	no wl for col end	2020-10-08 03:34:16 -07:00
jcirimel	5c263e0001	rep col done w/o power pins	2020-09-23 06:24:52 -07:00
jcirimel	d22164bd48	single port progess	2020-09-14 18:11:38 -07:00