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OpenRAM
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4,853 Commits 4 Branches 63 Tags 78 MiB
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4 Commits

Author SHA1 Message Date
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00