diff --git a/compiler/modules/col_cap_bitcell_1port.py b/compiler/modules/col_cap_bitcell_1port.py
index b57cfa3f..da69c9b1 100644
--- a/compiler/modules/col_cap_bitcell_1port.py
+++ b/compiler/modules/col_cap_bitcell_1port.py
@@ -16,7 +16,7 @@ class col_cap_bitcell_1port(bitcell_base):
     """
 
     def __init__(self, name="col_cap_bitcell_1port"):
-        bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_1port)
+        bitcell_base.__init__(self, name, prop=props.col_cap_1port)
         debug.info(2, "Create col_cap bitcell 1 port object")
 
         self.no_instances = True
diff --git a/compiler/modules/col_cap_bitcell_2port.py b/compiler/modules/col_cap_bitcell_2port.py
index acc0e489..3b42ca9d 100644
--- a/compiler/modules/col_cap_bitcell_2port.py
+++ b/compiler/modules/col_cap_bitcell_2port.py
@@ -16,7 +16,7 @@ class col_cap_bitcell_2port(bitcell_base):
     """
 
     def __init__(self, name="col_cap_bitcell_2port"):
-        bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_2port)
+        bitcell_base.__init__(self, name, prop=props.col_cap_2port)
         debug.info(2, "Create col_cap bitcell 2 port object")
 
         self.no_instances = True
diff --git a/compiler/modules/row_cap_bitcell_1port.py b/compiler/modules/row_cap_bitcell_1port.py
index 82849000..a0eceeb3 100644
--- a/compiler/modules/row_cap_bitcell_1port.py
+++ b/compiler/modules/row_cap_bitcell_1port.py
@@ -16,7 +16,7 @@ class row_cap_bitcell_1port(bitcell_base):
     """
 
     def __init__(self, name="row_cap_bitcell_1port"):
-        bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_1port)
+        bitcell_base.__init__(self, name, prop=props.row_cap_1port)
         debug.info(2, "Create row_cap bitcell 1 port object")
 
         self.no_instances = True
diff --git a/compiler/modules/row_cap_bitcell_2port.py b/compiler/modules/row_cap_bitcell_2port.py
index 771e9043..9eabc80f 100644
--- a/compiler/modules/row_cap_bitcell_2port.py
+++ b/compiler/modules/row_cap_bitcell_2port.py
@@ -16,7 +16,7 @@ class row_cap_bitcell_2port(bitcell_base):
     """
 
     def __init__(self, name="row_cap_bitcell_2port"):
-        bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_2port)
+        bitcell_base.__init__(self, name, prop=props.row_cap_2port)
         debug.info(2, "Create row_cap bitcell 2 port object")
 
         self.no_instances = True