From fe65a2043143ddc5bb17ee5673474b83cb2f2dc2 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 13 Mar 2023 14:44:50 -0700 Subject: [PATCH] Rename ROM unit tests. --- compiler/modules/{rom_base_bank.py => rom_bank.py} | 0 .../{05_rom_decoder_test.py => 06_rom_decoder_test.py} | 0 ...n_mux_array_test.py => 07_rom_column_mux_array_test.py} | 0 ...r_array_test.py => 08_rom_decoder_buffer_array_test.py} | 0 ...charge_array_test.py => 08_rom_precharge_array_test.py} | 0 ..._array_test.py => 10_rom_wordline_driver_array_test.py} | 0 .../tests/{05_rom_array_test.py => 14_rom_array_test.py} | 0 ..._control_logic_test.py => 16_rom_control_logic_test.py} | 0 ...5_rom_base_bank_1kB_test.py => 19_rom_bank_1kb_test.py} | 4 ++-- ...5_rom_base_bank_4kB_test.py => 19_rom_bank_4kb_test.py} | 4 ++-- macros/rom_configs/sky130_rom_common.py | 7 +++++++ 11 files changed, 11 insertions(+), 4 deletions(-) rename compiler/modules/{rom_base_bank.py => rom_bank.py} (100%) rename compiler/tests/{05_rom_decoder_test.py => 06_rom_decoder_test.py} (100%) rename compiler/tests/{05_rom_column_mux_array_test.py => 07_rom_column_mux_array_test.py} (100%) rename compiler/tests/{05_rom_decoder_buffer_array_test.py => 08_rom_decoder_buffer_array_test.py} (100%) rename compiler/tests/{05_rom_precharge_array_test.py => 08_rom_precharge_array_test.py} (100%) rename compiler/tests/{05_rom_wordline_driver_array_test.py => 10_rom_wordline_driver_array_test.py} (100%) rename compiler/tests/{05_rom_array_test.py => 14_rom_array_test.py} (100%) rename compiler/tests/{05_rom_control_logic_test.py => 16_rom_control_logic_test.py} (100%) rename compiler/tests/{05_rom_base_bank_1kB_test.py => 19_rom_bank_1kb_test.py} (91%) rename compiler/tests/{05_rom_base_bank_4kB_test.py => 19_rom_bank_4kb_test.py} (91%) create mode 100644 macros/rom_configs/sky130_rom_common.py diff --git a/compiler/modules/rom_base_bank.py b/compiler/modules/rom_bank.py similarity index 100% rename from compiler/modules/rom_base_bank.py rename to compiler/modules/rom_bank.py diff --git a/compiler/tests/05_rom_decoder_test.py b/compiler/tests/06_rom_decoder_test.py similarity index 100% rename from compiler/tests/05_rom_decoder_test.py rename to compiler/tests/06_rom_decoder_test.py diff --git a/compiler/tests/05_rom_column_mux_array_test.py b/compiler/tests/07_rom_column_mux_array_test.py similarity index 100% rename from compiler/tests/05_rom_column_mux_array_test.py rename to compiler/tests/07_rom_column_mux_array_test.py diff --git a/compiler/tests/05_rom_decoder_buffer_array_test.py b/compiler/tests/08_rom_decoder_buffer_array_test.py similarity index 100% rename from compiler/tests/05_rom_decoder_buffer_array_test.py rename to compiler/tests/08_rom_decoder_buffer_array_test.py diff --git a/compiler/tests/05_rom_precharge_array_test.py b/compiler/tests/08_rom_precharge_array_test.py similarity index 100% rename from compiler/tests/05_rom_precharge_array_test.py rename to compiler/tests/08_rom_precharge_array_test.py diff --git a/compiler/tests/05_rom_wordline_driver_array_test.py b/compiler/tests/10_rom_wordline_driver_array_test.py similarity index 100% rename from compiler/tests/05_rom_wordline_driver_array_test.py rename to compiler/tests/10_rom_wordline_driver_array_test.py diff --git a/compiler/tests/05_rom_array_test.py b/compiler/tests/14_rom_array_test.py similarity index 100% rename from compiler/tests/05_rom_array_test.py rename to compiler/tests/14_rom_array_test.py diff --git a/compiler/tests/05_rom_control_logic_test.py b/compiler/tests/16_rom_control_logic_test.py similarity index 100% rename from compiler/tests/05_rom_control_logic_test.py rename to compiler/tests/16_rom_control_logic_test.py diff --git a/compiler/tests/05_rom_base_bank_1kB_test.py b/compiler/tests/19_rom_bank_1kb_test.py similarity index 91% rename from compiler/tests/05_rom_base_bank_1kB_test.py rename to compiler/tests/19_rom_bank_1kb_test.py index be3fcb3a..f0a61dee 100644 --- a/compiler/tests/05_rom_base_bank_1kB_test.py +++ b/compiler/tests/19_rom_bank_1kb_test.py @@ -30,7 +30,7 @@ class rom_bank_test(openram_test): rom_data = test_data, word_size = 1) - a = factory.create(module_type="rom_base_bank", rom_config=conf) + a = factory.create(module_type="rom_bank", rom_config=conf) a.sp_write(OPTS.openram_temp + 'simulation_file.sp') self.local_check(a) @@ -41,4 +41,4 @@ if __name__ == "__main__": (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/05_rom_base_bank_4kB_test.py b/compiler/tests/19_rom_bank_4kb_test.py similarity index 91% rename from compiler/tests/05_rom_base_bank_4kB_test.py rename to compiler/tests/19_rom_bank_4kb_test.py index b9a37a21..7fa2005d 100644 --- a/compiler/tests/05_rom_base_bank_4kB_test.py +++ b/compiler/tests/19_rom_bank_4kb_test.py @@ -31,7 +31,7 @@ class rom_bank_test(openram_test): rom_data = test_data, word_size = 2) - a = factory.create(module_type="rom_base_bank", rom_config=conf) + a = factory.create(module_type="rom_bank", rom_config=conf) a.sp_write(OPTS.openram_temp + 'simulation_file.sp') self.local_check(a) @@ -42,4 +42,4 @@ if __name__ == "__main__": (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/macros/rom_configs/sky130_rom_common.py b/macros/rom_configs/sky130_rom_common.py new file mode 100644 index 00000000..40ebd414 --- /dev/null +++ b/macros/rom_configs/sky130_rom_common.py @@ -0,0 +1,7 @@ + +tech_name = "sky130" +nominal_corner_only = True + +#route_supplies = "ring" +check_lvsdrc = True +