From fdf92d0da1fdcc88b8c0119600e80aed8ad534b5 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Jun 2020 16:41:26 -0700 Subject: [PATCH] Rename test 14 --- ...1r_array_test.py => 14_replica_bitcell_array_1rw_1r_test.py} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename compiler/tests/{14_replica_bitcell_1rw_1r_array_test.py => 14_replica_bitcell_array_1rw_1r_test.py} (95%) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py similarity index 95% rename from compiler/tests/14_replica_bitcell_1rw_1r_array_test.py rename to compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index 3f869255..a36fc80f 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -13,7 +13,7 @@ from globals import OPTS from sram_factory import factory import debug -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))