From fc85dfe29fd27b02b19a3c6d37631297abf6bf5b Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 21 Apr 2020 15:21:57 -0700
Subject: [PATCH] Add boundary to all pgates

---
 compiler/pgates/pand2.py         | 1 +
 compiler/pgates/pand3.py         | 1 +
 compiler/pgates/pbuf.py          | 1 +
 compiler/pgates/pdriver.py       | 1 +
 compiler/pgates/pinv.py          | 1 +
 compiler/pgates/pinvbuf.py       | 1 +
 compiler/pgates/pnand2.py        | 3 ++-
 compiler/pgates/pnand3.py        | 1 +
 compiler/pgates/pnor2.py         | 1 +
 compiler/pgates/precharge.py     | 3 ++-
 compiler/pgates/ptristate_inv.py | 1 +
 compiler/pgates/pwrite_driver.py | 1 +
 12 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py
index 23fd5e5b..995296b6 100644
--- a/compiler/pgates/pand2.py
+++ b/compiler/pgates/pand2.py
@@ -45,6 +45,7 @@ class pand2(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         self.DRC_LVS()
         
     def add_pins(self):
diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py
index dd1d87f7..f8cc2ac3 100644
--- a/compiler/pgates/pand3.py
+++ b/compiler/pgates/pand3.py
@@ -44,6 +44,7 @@ class pand3(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         self.DRC_LVS()
         
     def add_pins(self):
diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py
index 3171324b..6f9719eb 100644
--- a/compiler/pgates/pbuf.py
+++ b/compiler/pgates/pbuf.py
@@ -37,6 +37,7 @@ class pbuf(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("A", "INPUT")
diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index 5aa5393e..4bf654a4 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -76,6 +76,7 @@ class pdriver(pgate.pgate):
 
         self.width = self.inv_inst_list[-1].rx()
         self.height = self.inv_inst_list[0].height
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("A", "INPUT")
diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py
index 3ec3e23e..d5a26a7a 100644
--- a/compiler/pgates/pinv.py
+++ b/compiler/pgates/pinv.py
@@ -64,6 +64,7 @@ class pinv(pgate.pgate):
                               "A",
                               position="farleft")
         self.route_outputs()
+        self.add_boundary()
         
     def add_pins(self):
         """ Adds pins for spice netlist """
diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py
index b8ecb3bf..fe376bc4 100644
--- a/compiler/pgates/pinvbuf.py
+++ b/compiler/pgates/pinvbuf.py
@@ -47,6 +47,7 @@ class pinvbuf(pgate.pgate):
         self.place_modules()
         self.route_wires()
         self.add_layout_pins()
+        self.add_boundary()
         
         self.offset_all_coordinates()
         
diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py
index 2f21c0bb..8398abbc 100644
--- a/compiler/pgates/pnand2.py
+++ b/compiler/pgates/pnand2.py
@@ -57,7 +57,8 @@ class pnand2(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
-
+        self.add_boundary()
+        
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "B", "Z", "vdd", "gnd"]
diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py
index 83e57c0a..fd563145 100644
--- a/compiler/pgates/pnand3.py
+++ b/compiler/pgates/pnand3.py
@@ -67,6 +67,7 @@ class pnand3(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
+        self.add_boundary()
         
     def add_ptx(self):
         """ Create the PMOS and NMOS transistors. """
diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py
index 75840f26..9dbc0c52 100644
--- a/compiler/pgates/pnor2.py
+++ b/compiler/pgates/pnor2.py
@@ -56,6 +56,7 @@ class pnor2(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
+        self.add_boundary()
 
     def add_pins(self):
         """ Adds pins for spice netlist """
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index afe14a05..7adec605 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -68,7 +68,8 @@ class precharge(design.design):
         self.route_vdd_rail()
         self.route_bitlines()
         self.connect_to_bitlines()
-
+        self.add_boundary()
+        
     def add_pins(self):
         self.add_pin_list(["bl", "br", "en_bar", "vdd"],
                           ["OUTPUT", "OUTPUT", "INPUT", "POWER"])
diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py
index 9586e72b..22f6b164 100644
--- a/compiler/pgates/ptristate_inv.py
+++ b/compiler/pgates/ptristate_inv.py
@@ -56,6 +56,7 @@ class ptristate_inv(pgate.pgate):
         self.connect_rails()
         self.route_inputs()
         self.route_outputs()
+        self.add_boundary()
         
     def add_pins(self):
         """ Adds pins for spice netlist """
diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py
index 16830e62..da5eacdc 100644
--- a/compiler/pgates/pwrite_driver.py
+++ b/compiler/pgates/pwrite_driver.py
@@ -52,6 +52,7 @@ class pwrite_driver(design.design):
         self.place_modules()
         self.route_wires()
         self.route_supplies()
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("din", "INPUT")