From f8fc7c12b3a026b079345685217b3afc39402eb1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:02:28 -0700 Subject: [PATCH] Remove ms_flop and replace with dff. Might break setup_hold tests. --- compiler/characterizer/setup_hold.py | 6 +- compiler/modules/dff.py | 19 ++++ compiler/modules/ms_flop.py | 50 --------- compiler/modules/ms_flop_array.py | 136 ----------------------- technology/freepdk45/gds_lib/ms_flop.gds | Bin 40960 -> 0 bytes technology/freepdk45/sp_lib/ms_flop.sp | 29 ----- technology/scn3me_subm/layers.map | 16 --- technology/scn3me_subm/mag_lib/.magicrc | 5 +- technology/scn3me_subm/sp_lib/dff.sp | 28 +---- 9 files changed, 30 insertions(+), 259 deletions(-) delete mode 100644 compiler/modules/ms_flop.py delete mode 100644 compiler/modules/ms_flop_array.py delete mode 100644 technology/freepdk45/gds_lib/ms_flop.gds delete mode 100644 technology/freepdk45/sp_lib/ms_flop.sp delete mode 100644 technology/scn3me_subm/layers.map diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index ee35af46..eaef6bac 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -3,7 +3,7 @@ import tech from .stimuli import * import debug from .charutils import * -import ms_flop +import dff from globals import OPTS @@ -16,8 +16,8 @@ class setup_hold(): def __init__(self, corner): # This must match the spice model order self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"] - self.model_name = "ms_flop" - self.model_location = OPTS.openram_tech + "sp_lib/ms_flop.sp" + self.model_name = "dff" + self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] debug.info(2,"Feasible period from technology file: {0} ".format(self.period)) diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 62e424cb..d72aae2e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -21,6 +21,25 @@ class dff(design.design): self.height = dff.height self.pin_map = dff.pin_map + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + from tech import spice + c_eff = self.calculate_effective_capacitance(load) + f = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*f + power_leak = spice["msflop_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + from tech import spice, parameter + c_load = load + c_para = spice["flop_para_cap"]#ff + transition_prob = spice["flop_transition_prob"] + return transition_prob*(c_load + c_para) + def analytical_delay(self, slew, load = 0.0): # dont know how to calculate this now, use constant in tech file from tech import spice diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py deleted file mode 100644 index bb8e2ca2..00000000 --- a/compiler/modules/ms_flop.py +++ /dev/null @@ -1,50 +0,0 @@ -import globals -import design -from math import log -import design -from tech import GDS,layer -import utils - -class ms_flop(design.design): - """ - Memory address flip-flop - """ - - pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"] - (width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"]) - - def __init__(self, name="ms_flop"): - design.design.__init__(self, name) - - self.width = ms_flop.width - self.height = ms_flop.height - self.pin_map = ms_flop.pin_map - - def analytical_delay(self, slew, load = 0.0): - # dont know how to calculate this now, use constant in tech file - from tech import spice - result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) - return result - - def analytical_power(self, proc, vdd, temp, load): - """Returns dynamic and leakage power. Results in nW""" - from tech import spice - c_eff = self.calculate_effective_capacitance(load) - f = spice["default_event_rate"] - power_dyn = c_eff*vdd*vdd*f - power_leak = spice["msflop_leakage"] - - total_power = self.return_power(power_dyn, power_leak) - return total_power - - def calculate_effective_capacitance(self, load): - """Computes effective capacitance. Results in fF""" - from tech import spice, parameter - c_load = load - c_para = spice["flop_para_cap"]#ff - transition_prob = spice["flop_transition_prob"] - return transition_prob*(c_load + c_para) - - - \ No newline at end of file diff --git a/compiler/modules/ms_flop_array.py b/compiler/modules/ms_flop_array.py deleted file mode 100644 index 061ad9be..00000000 --- a/compiler/modules/ms_flop_array.py +++ /dev/null @@ -1,136 +0,0 @@ -import debug -import design -from tech import drc -from math import log -from vector import vector -from globals import OPTS - -class ms_flop_array(design.design): - """ - An Array of D-Flipflops used for to store Data_in & Data_out of - Write_driver & Sense_amp, address inputs of column_mux & - hierdecoder - """ - - def __init__(self, columns, word_size, name=""): - self.columns = columns - self.word_size = word_size - if name=="": - name = "flop_array_c{0}_w{1}".format(columns,word_size) - design.design.__init__(self, name) - debug.info(1, "Creating {}".format(self.name)) - - self.words_per_row = int(self.columns / self.word_size) - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_ms_flop_array() - - def create_layout(self): - self.width = self.columns * self.ms.width - self.height = self.ms.height - - self.place_ms_flop_array() - self.add_layout_pins() - self.DRC_LVS() - - def add_modules(self): - from importlib import reload - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms = self.mod_ms_flop("ms_flop") - self.add_mod(self.ms) - - def add_pins(self): - for i in range(self.word_size): - self.add_pin("din[{0}]".format(i)) - for i in range(self.word_size): - self.add_pin("dout[{0}]".format(i)) - self.add_pin("dout_bar[{0}]".format(i)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") - - def create_ms_flop_array(self): - self.ms_inst={} - for i in range(0,self.columns,self.words_per_row): - name = "Xdff{0}".format(i) - index = int(i/self.words_per_row) - self.ms_inst[index]=self.add_inst(name=name, - mod=self.ms) - self.connect_inst(["din[{0}]".format(index), - "dout[{0}]".format(index), - "dout_bar[{0}]".format(index), - "clk", - "vdd", "gnd"]) - - def place_ms_flop_array(self): - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) - if (i % 2 == 0 or self.words_per_row>1): - base = vector(i*self.ms.width,0) - mirror = "R0" - else: - base = vector((i+1)*self.ms.width,0) - mirror = "MY" - self.ms_inst[index].place(offset=base, - mirror=mirror) - - def add_layout_pins(self): - - for i in range(self.word_size): - - # Route both supplies - for n in ["vdd", "gnd"]: - for supply_pin in self.ms_inst[i].get_pins(n): - pin_pos = supply_pin.center() - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=pin_pos) - self.add_layout_pin_rect_center(text=n, - layer="metal3", - offset=pin_pos) - - - din_pins = self.ms_inst[i].get_pins("din") - for din_pin in din_pins: - self.add_layout_pin(text="din[{}]".format(i), - layer=din_pin.layer, - offset=din_pin.ll(), - width=din_pin.width(), - height=din_pin.height()) - - dout_pin = self.ms_inst[i].get_pin("dout") - self.add_layout_pin(text="dout[{}]".format(i), - layer="metal2", - offset=dout_pin.ll(), - width=dout_pin.width(), - height=dout_pin.height()) - - doutbar_pin = self.ms_inst[i].get_pin("dout_bar") - self.add_layout_pin(text="dout_bar[{}]".format(i), - layer="metal2", - offset=doutbar_pin.ll(), - width=doutbar_pin.width(), - height=doutbar_pin.height()) - - - # Continous clk rail along with label. - self.add_layout_pin(text="clk", - layer="metal1", - offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1), - width=self.width, - height=drc["minwidth_metal1"]) - - - - - - - def analytical_delay(self, slew, load=0.0): - return self.ms.analytical_delay(slew=slew, load=load) - diff --git a/technology/freepdk45/gds_lib/ms_flop.gds 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z{@lMG_`2eY2cM((7dNynX7eZRIr<4IHgV4}tv@C2r``C2^3i_$LF*;I#(mUDjJj$3 zo7PM9qyIS%;$!@q)=PfYoyZ@Ox8nCn{^@wOe#FHel%M$cgVx*apC7#c;yWnzpF#GY zpVR-F*4z8fmj5*RzvYkp=gr!8>LJdgmS1CGF=vm-@y1ug1S=y>tKD z^2a-r_iDWB{y*+t^~}%Y{YJY#;EMxwV-@KkP z!qwdGDu2_un2nFm&pF0?{?V@AZv7pUPf}d?58|x@wEm=geA+*AJhgx3JEHo(PwU6? ze&*eQud43i!Don?f2MUY+x|)8vwp?%C-?@v+>E>_u0PhHm!H=zgzVu zf6o)o8`FAe{^0jK^}IE$cb-`N89$Gq zpP_o3{hIOf$o0#l^`KvtQ;%F88_yrV9z#Dvd7Sf;@#`_Hri_nC`-Sl_X}^%ir1c<= wVf9#<_NV_fxW83B`~UG?3-2|U{R7(GE$T;G-K@t1%6Wd(j&fqVu2AE_wZ_y7O^ diff --git a/technology/freepdk45/sp_lib/ms_flop.sp b/technology/freepdk45/sp_lib/ms_flop.sp deleted file mode 100644 index 03016e5d..00000000 --- a/technology/freepdk45/sp_lib/ms_flop.sp +++ /dev/null @@ -1,29 +0,0 @@ -*master-slave flip-flop with both output and inverted ouput - -.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd -*clk inverter -mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNff1 clk_bar clk gnd gnd NMOS_VTG W=90n L=50n m=1 - -*transmission gate 1 -mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1 - -*foward inverter -mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1 - -*backward inverter -mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1 - -*transmission gate 2 -mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1 -.ENDS dlatch - -.SUBCKT ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ENDS flop - diff --git a/technology/scn3me_subm/layers.map b/technology/scn3me_subm/layers.map deleted file mode 100644 index d10d5f2d..00000000 --- a/technology/scn3me_subm/layers.map +++ /dev/null @@ -1,16 +0,0 @@ -Pwell drawing 41 0 -Nwell drawing 42 0 -Active drawing 43 0 -Poly1 drawing 46 0 -Pselect drawing 45 0 -Nselect drawing 44 0 -contact drawing 25 0 -P1Con drawing 47 0 -ActX drawing 48 0 -Metal1 drawing 49 0 -Via drawing 50 0 -Metal2 drawing 51 0 -Via2 drawing 61 0 -Metal3 drawing 62 0 -Glass drawing 52 0 -text drawing 83 0 diff --git a/technology/scn3me_subm/mag_lib/.magicrc b/technology/scn3me_subm/mag_lib/.magicrc index d6068ec3..f52d0592 100644 --- a/technology/scn3me_subm/mag_lib/.magicrc +++ b/technology/scn3me_subm/mag_lib/.magicrc @@ -1,2 +1,5 @@ path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech -tech load SCN3ME_SUBM.30 +tech load SCN3ME_SUBM.30 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp index 61515ab6..d3fa7635 100644 --- a/technology/scn3me_subm/sp_lib/dff.sp +++ b/technology/scn3me_subm/sp_lib/dff.sp @@ -1,47 +1,27 @@ +*********************** "dff" ****************************** * Positive edge-triggered FF -.subckt dff D Q clk vdd gnd +.SUBCKT dff D Q clk vdd gnd M0 vdd clk a_2_6# vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M10 gnd clk a_2_6# gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u -.ends dff + +.ENDS dff