From 8e243258e491269eddb9735687912162f93cb524 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 24 Oct 2018 16:56:47 -0700 Subject: [PATCH 1/4] Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. --- compiler/bitcells/bitcell_1rw_1r.py | 7 +++-- compiler/characterizer/lib.py | 24 ++------------- ...est.py => 05_bitcell_1rw_1r_array_test.py} | 29 ++++++++---------- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 16384 bytes 4 files changed, 18 insertions(+), 42 deletions(-) rename compiler/tests/{04_bitcell_1rw_1r_test.py => 05_bitcell_1rw_1r_array_test.py} (53%) diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 9cec7d8d..1f5721fc 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -19,9 +19,10 @@ class bitcell_1rw_1r(design.design): design.design.__init__(self, "cell_1rw_1r") debug.info(2, "Create bitcell with 1RW and 1R Port") - self.width = bitcell.width - self.height = bitcell.height - self.pin_map = bitcell.pin_map + self.width = bitcell_1rw_1r.width + self.height = bitcell_1rw_1r.height + debug.info(1, "Multiport width {}, height {}".format(self.width, self.height)) + self.pin_map = bitcell_1rw_1r.pin_map def analytical_delay(self, slew, load=0, swing = 0.5): # delay of bit cell is not like a driver(from WL) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 7ae25b73..6added12 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -17,7 +17,6 @@ class lib: self.sram = sram self.sp_file = sp_file self.use_model = use_model - #self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later. self.set_port_indices() self.prepare_tables() @@ -27,30 +26,11 @@ class lib: self.characterize_corners() def set_port_indices(self): + """Copies port information set in the SRAM instance""" self.total_port_num = self.sram.total_ports self.read_ports = self.sram.read_index self.write_ports = self.sram.write_index - - def gen_port_names(self): - """Generates the port names to be written to the lib file""" - #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here. - self.write_ports = [] - self.read_ports = [] - self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports - - #save a member variable to avoid accessing global. readwrite ports have different control signals. - self.readwrite_port_num = OPTS.num_rw_ports - - #Generate the port names. readwrite ports are required to be added first for this to work. - for readwrite_port_num in range(OPTS.num_rw_ports): - self.read_ports.append(readwrite_port_num) - self.write_ports.append(readwrite_port_num) - #This placement is intentional. It makes indexing input data easier. See self.data_values - for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports): - self.read_ports.append(read_port_num) - for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports): - self.write_ports.append(write_port_num) - + def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes diff --git a/compiler/tests/04_bitcell_1rw_1r_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py similarity index 53% rename from compiler/tests/04_bitcell_1rw_1r_test.py rename to compiler/tests/05_bitcell_1rw_1r_array_test.py index 67db3710..04afa899 100755 --- a/compiler/tests/04_bitcell_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 """ -Run regresion tests on a parameterized bitcell +Run a regression test on a basic array """ import unittest @@ -11,29 +11,24 @@ import globals from globals import OPTS import debug -OPTS = globals.OPTS +#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") -@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test") -class bitcell_1rw_1r_test(openram_test): +class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - OPTS.bitcell = "bitcell_1rw_1r" globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bitcell import bitcell - from bitcell_1rw_1r import bitcell_1rw_1r - import tech - OPTS.num_rw_ports=1 - OPTS.num_w_ports=0 - OPTS.num_r_ports=1 - debug.info(2, "Bitcell with 1 read/write and 1 read port") - #tx = bitcell_1rw_1r() - tx = bitcell() - self.local_check(tx) + import bitcell_array + + debug.info(2, "Testing 4x4 array for 6t_cell") + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4) + self.local_check(a) globals.end_openram() - - # instantiate a copy of the class to actually run the test if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds index 9f4e0650acba732fa94328acdb17a17f8c615e56..c282b61c0cc98469cab0e4c464a52c6d7403790c 100644 GIT binary patch delta 1520 zcmZ`(O=}ZT6n!t|qfIi&IEn2zO=jA(X=@u{lKE^GHc|!cA{MO(BJB?-qKN25%pe6f zLTT^Lg?242Dh~ybLbnQ~OIM;xtBZo5f?#9DeBEc`tloL|+;h*pmp7hAJ&)!{m;^|O zWN3igAyFceByov^&V{v{5ouf()~=~>Q#VURS2qn^C*aZZYr8A0FkGbr(N3IIX@$09 zbD@D)CswMb%1k<9bqJMU1|`Go;4aQZA$B8_peLJ_$XOC68WD;ADdBKs;q?5{?3v1? zC96}-@{PiBQdp1tY>OU5GN_rN-;4~WdS12(H**?ttb->`uuAV!O83D#b^`ii%HLBS zuEh3`y>&4Si}6@TCXQw5jR*QcP$N)IPQpw&0jqKfzKGZ1jh137g4UAXNwnmJBriXT zih(X_xDpDns`##(SOGptTZnhaFW0sS<)a#8`zF{-y4;YPZMMBLQUD=cf*DnSg}%FO z8~kAH#$cuX?`;A<*!ptB33#Sx{xsOCe5+Aq95%88%}UG49@>NrR7~+B<}5qS5!aoi zhnSpM>LysXu5NLnMN$2aL$@iIVim31`iJm-_>FMJrdm2Mm=3YGxyS#`lhfJGPd5EX z>|6dNn4hU;cqLCVZk0nZ5Z&vJPrqL9Kw!-X-{ky!%wz*C~MmZLfKJxnhFmb qr3+QXw9gLrx@DJx=iEFJFk#Le=J19+20Ly7-C3|`kFe;}tMDIQ?P@sy delta 1478 zcmZux&rcIk5PlD6t8I6?wuRQEbW5RtEhfe67OTeXb>szahFr1^k;Z~fjP=_{S z^MT$-D^~WXX%_F)TM15A29e=L*B0iY5W5x->Ct*is$KA0`cx2c9+)mh%egcnn;r$ee?ZDE$m>_Yp`%Eejup1hXO9t4x{DXEM z+cZkMP8Es4z8C(4!{RIh4nF0cmcx{nJY`3lz|kE|21n-z{#BK~dZC+`^j9}9 zJZ2OyykZQYF;w`b9fnCe3Mb7tPWxb380Ji?omI8Ez%^w)D+_N-d2ePGXN_3g_j;Cx hx2*!=YjDRJ;P5A77zA5HcRD;Y2HCv*EC`qE%70v1Xu<#h From 6efe0f56c2e2dbfce72130119d597235757faa39 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 25 Oct 2018 14:53:03 -0700 Subject: [PATCH 2/4] Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. --- compiler/bitcells/bitcell_1rw_1r.py | 13 +- .../tests/05_bitcell_1rw_1r_array_test.py | 2 +- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 16384 bytes technology/scn4m_subm/gds_lib/cell_1rw_1r.gds | Bin 0 -> 6202 bytes technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 256 +++++++++--------- technology/scn4m_subm/sp_lib/cell_1rw_1r.sp | 14 + 6 files changed, 150 insertions(+), 135 deletions(-) create mode 100644 technology/scn4m_subm/gds_lib/cell_1rw_1r.gds create mode 100644 technology/scn4m_subm/sp_lib/cell_1rw_1r.sp diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 1f5721fc..2f13a910 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -21,7 +21,6 @@ class bitcell_1rw_1r(design.design): self.width = bitcell_1rw_1r.width self.height = bitcell_1rw_1r.height - debug.info(1, "Multiport width {}, height {}".format(self.width, self.height)) self.pin_map = bitcell_1rw_1r.pin_map def analytical_delay(self, slew, load=0, swing = 0.5): @@ -39,12 +38,12 @@ class bitcell_1rw_1r(design.design): def list_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = ["bl0[{0}]".format(col), - "br0[{0}]".format(col), - "bl1[{0}]".format(col), - "br1[{0}]".format(col), - "wl0[{0}]".format(row), - "wl1[{0}]".format(row), + bitcell_pins = ["bl0_{0}".format(col), + "br0_{0}".format(col), + "bl1_{0}".format(col), + "br1_{0}".format(col), + "wl0_{0}".format(row), + "wl1_{0}".format(row), "vdd", "gnd"] return bitcell_pins diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 04afa899..68dcc409 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -19,7 +19,7 @@ class bitcell_1rw_1r_array_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import bitcell_array - debug.info(2, "Testing 4x4 array for 6t_cell") + debug.info(2, "Testing 4x4 array for cell_1rw_1r") OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds index c282b61c0cc98469cab0e4c464a52c6d7403790c..fe12fc729b64479255fb28bbf2bad3acd31eec47 100644 GIT binary patch literal 16384 zcmeHOS&SXU6|L@hulsrC&1f)@0W*LxQKUG?n$3d;vB((sz<5#Y9~!Q|YkzFk$_UA??{ zM0~uKdQQJved^x2b#E=*Jt7dksEYy57t^9!TqqU_Ph1{f`=VDY@`DWrem1>*>dv38 zT061h7k5qV+atsey6V?0IsW(yXEy$4eCh2MoLc+4Wn!SNYa!-MqA4yD{eq55gJA8@ z#D?{^Zk||uvX{!YHqxb|rdqzu*K_HpDXG8M zbL+B3$`x(%T$k17|NoJ)WzR)1+j7qrcpmvWxntknsZ_oW>3mH@E#(SM8Y>xT#-T`N zyxAIS5>bcy=pa5FK(9~n86h>tD!c78w_k&k#%sp+!6!N6HHu%*cC1eJ?%8+O#Prn8 zRPzVp$g{OiK?@FVOrx|Kaz>OmtVhX==Ft_^EJC)M(W$>BekyBaJCUu7 z-cnrSV1(R^)&w6mv^#4p{j&b*8An;Wr43m-rn7c%-139H!>JyJ*1F@{H54M}p z&hkW-fi{b?lcnkTnda8ASsL|&J=#a{lid$imd<6(jmSAR68wS{rgKj_hB%6Jr}ngDuiT3=ehPc(`5EIj%XcY$ zyccfMp4k79($AR40Xv5?_Qc*<@F8c!URlOqf$#G6#QJHBtvzGB^#`CGaz?lHD4D^D z!yK>u0SIP@uMmID5x~$Nm$%4QcA^&RV7nPnXzEXmK+;Z(crhMP)%lDAd3@N==GAqq zSL&Dbw=@D_uRrfSvHz4FfrhWL{E#^U*>R8?N7*Bgu_yMAfR7PKq4q=W2vmZfH*aH< zX<<+7oVVez$XX-n(UNE{Vvg4`S|MjlM6JO`NyfY#M=xcaDmSCv;In?td|i5 z?c{f|&KKpLW?{8lI_s*(k(G7vp46DPDcfjIs}Qk~vs$jgFU~sXs+y46#?JHK;^)5^S;zgynCQpC ztn={vS3XISSUu}p{JgBgTO!PLZOb}5dn=uFv`3|^i!k9WW3EC;R@UuOa^5q#`AQFG z8zbvwY%@QdbqRapy)ExGJ9}J}b$NT-tgOqAqvEW?-d1Lv#1^v7!JkLgosX}tmWi?W zdoKF6t3L>K+_`)A#L$6*IQ2f*iZj1gh{h=9?fnLx!*7x^+HbWie(;9kg_j!$o|H4@ z@atE=u)hdVKdiBSKYl~bh;nmHY3Zl?!bcUKvHN|+XN26z@A@_L{u^hHM$$`iMwI9B zNiXpkNiXpkS%35_2=B&=-%ffL3eo$lXj~LbPhu!D^&9WjF#?^$eTOh6?lADJNX~dj z@vG`@9wGe)chh%!##>EW|2vot5IY_MEXG%%pX7}DThos>tI)r5Z*KcPhweQ%HyQXc z^pl)%PYe3{P{*%S`!VCW+y5c%gMr>=17~nea>hwFpKNUW1NpW>WApdQc1Dyt^#}h| zyzm~4#3MOl9v@bU=2jsVV4RHc6O!UL<5su+`oEATID>;4d;YAh8By-EzxE7tzpMC+ z-T2OfeuTNrcsxV3k?vO7lDLPsy-cBMZWzwj+z@%Sk)hWA`T`Flrl z{4%};gpvuw*&J|IV-FtZkem_avi()`dyi@TiSfhI@7)KzU&DVVH1=GH-;gt+yt4lA zLGTyI_8-X8AMS@ZFy4bin)qyHy0{xPE5X@C7o z#iQ|`>LDZ^$r%%TV|@)ybjWcF*MyC=O2~*`rhenit-7!Kam8cAx=9|4kehtt2{imX zt=b-brm^-LC1-?hoP6&V#q(a%NIa4=CivDqwFUhazXknxp2+`uq5MRDP5-ms7*Q(Ps{!>bQCfC zpHyW~JGie4e6@nVN*t))fSE@g(id_c@rmgRr=3^1>Y%+;Sgwwh$~&~%v-`}cbzJv= z-PWA{`iZ{4Ot#hgCvyF_W?OUWklqQeuE5Y*x0oLGw_;>^xTID`9q`q>>!^K&wtQUG zj@A92n$dCtX1(sXj>QXI|9#|WN9_rWR1cZ_%>QN>R((!)2XDuB;|o#e|9z-fK8h^e zRO)`0eW(GW5NB)z{^0uxbdf05c-4g&KU=fE8^uKcs9Z zS%d7m2IkN(dV`IzEYD_nKdrZ`-0wYa^$Q|5GxDO*yY$`Vq5#?)|9hhOmiKB#9EO+; YYtewxfsO|{9_VYX2h6rJ|V8~gT1GYE_`wR z_M2z-bPt|6J%94J5SLYIyEb0y@AHdBojZ z!t+xu&%@H)_{=(tS?ZSt8#P zV=tPoVbl&=`k#b;%JUl;aZY*uB%_o|-{p)Q`JNhe)6vM2QB$tcC8MTXzOB}C$*3u) zKi_k6X_azY-#k~b=KTL(DSP%@7_&Xke2(XluZIqvJTafh*GZkPv8bh7!G~%kBi(T* zk{NHbYE3Naa2*}QrvvDXC_W>kX05WvPWSem_)xuOd=`9?GwxLUoUvnda^m>O)7^#n z!-?T{qR6wg&qE6iZ@WfmHROzFaafO*CC#HV>c<klz1uKp|K8Ty&W7}u})ZMC}mj|i@y)n%~G!XAEk5(YL3!nQ$dwpjbw4>JGAdozm9?9& zHa}1EK&btYmbGR0WwSQ_df0Y1KC91i?1WNRH7PYwW;e+xOH{iVr5~&;5ABDw`e3^m z?JSRF8EDJ+46-zNf2MnD(JT$;!LIgU{G`u=m8C0b_eNx=ythik`NLL~$iKHb`1x6f zcqnymb*^ajF4V}HD652cD-2qocSOk<(c;cJidH%-KEBh+@Q6bEb?^=SxQGwd%Luv2 zPh<`2iST*VlgD@@i!W!hzbjJKD^d0@?Ju>OqU-PdjOB;a6{$UsnQ@T5 zB0Zq|=^eoQKaX=-kxJBlNV~U1SyzCcv%+-lX}2SeLfwfyE!ivgqKq%YUV47Uc);>q zf*w{waLS(8dlP)f8L?NEF_`1KtUa-Q8e?luski<(v_sD5wjM1@ z_~0<>wLcEQ67dz{uUP>M{ZV_5d}Swku@1JI5sjw)LM@dVFJjhf8Lf~r#-i5Xqb23O9Yrr?ooY9u-r%!-;020wg{+qm z4gKT~vd$O9o@QaSTsZ5>$B~tF(Vo<}Z&S9>o>n1ZBV)B(hM%8x&{b-W>dZQ^RELI_zy_)=BIk>m2-5WZhc4eYII^ zH{RzO6QerbzZI`>vw`4A zIb#MtxD|$B&mH_mW9=xuL(YhHb4_XKr|aqqiqF{kh2k?p?&Mcrgxo6NUsiwnFzH`BM(^zzziQh0-@)x*4*Gv=AZ+nS&N$bbe(yNxKYSu<{Qf%Vx(WKf zY2ZWnPIAVZdeDD8s{1}Qe%$e#Em-YdofrcqC`c;(K&EzYek5HSj6;j^vEjx%JntM(jU}*#DWvA>=a28PV>v zpSaDliqF`(M)k!AxszWV#aQpb^}jdpJxmzM8SioPD{m-W)h}rzyGhQNWk31Jn^69X z@Nwlok8#4SzxEwm`w7&m5skHXVGHDpXm^gE^b7cl<}boWm43l^jho;2K6K;e(7H@x z{TuKd%Uj={I@j{k9G)*nS9tkjC&2)AK`gr|1je&rN0docy}1@^5xf0?|10) zUCQ6v;`PgT7Z7?-BUU)4CYR>>LBF2`R+zyC+AA44?#XX*EUh3j5GzW-O_P!r!F zXGD8x{SEl8^_m?2sVw~s+#^~~W4>Q8a0TB<&iHhB{mmD_e@W@@WQ@Q0OI){%Ps>2W zzmzlD?bB$bXPg%AND) zEh?T*J0kSsR}{}%WX$F_&M02fV^qAx8OCgW^8v+ct!Grc<^zn`e5!L)C#v%r{a>s4 z$B1_4`0L|}NA;ijAtWBj8Do57eNA~D+TCSD>}@7FW5Rypms@pR>n_Ya>IWm%O_I+D zxoN-g1R6Siim`4)yj`xb`Yk1AM7xvke^v4Pe`q8g$r)pOYoFSKev99Oemqaq@t@{@ z_M1ZOf28PDV_EM{%4guT@(&(Y9#f2rcfTYEs)i!=BalG~^R6lu0U&wvLQ-wx$t*Z~(OVx|@F{8XgyFGi(oKH!2 z=ozrbn(<#h;TxFou~t5YJo~me){H)+cN%w=U}&xTOb=JSi|qVLL9LEH8vg402tI$4!3fe=|&}Ij5_GN206ohN$!ZK2$7Y zT``3Jd|HE2h0r Ys>;E^-+>1P9vFCF;DLb$KHwhsA3BlbN&o-= diff --git a/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..0b13d628845584a367f83602fefb4c3f8b3b7134 GIT binary patch literal 6202 zcmb7|KTuso6vj^;@c0u#Kp{dzBqkV42s}_Dh?+QKkr|s57L1Ju9G|S_&vV6-=4E)_ujkrMLSwC5c8*6@gT-x zE+(QA*Z=*#9t$zqYJc5!VkRW;YvtbP|DX>U_~Z^kc-_DT-#Gx(mP5MDMrRV;YeEfK>K1%V;4HXRClwR~xCt^`Q6EC_cJ@;SD zU`0E=2pbD+Y$3m8+PtRpqn~h^be0jyuK50ak=55G;~wv zi+sQ~u`pm6X3Jy_i3Brgqfdoa&_do6?JZ;^Slf zO?>EP&CfXTF>Vtdx>@rx&#SY^Yp!VxqnpyJ`Qsyh6Ce4TH9zx=kGVJTp_?^7ahL<* zo1>})x+y)+e>K1UsL|41#4C>)ZbYh`sq;nuYxnf*d!}cFJSIMLQ+mu&KLb-YRhvDze#`Sru3qp`my%N*QB1VYxjK7?>Qnqa|Wp$ zx+%TrC(qMI$!F3Jx+%TrCqI15zsWc}uI~AwpB(Wq|0eT@Zb~oueUBn0^@hwFx>=h) z+A(i$-fT!e?zels8lO7hG07dDDZT1v+{8EO2fx`j{?P4n>3RGf zKl8@3n^@+h?tGfki~f=Qv`^$&&3+Nm54tJ6=x2|DFaO{}H*0?4aqUn$(|ZV0dNIED zt;E9*@u8c2{*Ao;)a@nrA20Y<6_@!kecv~w=lS>eTRZ9AKk&36YX{xzdw%!$-@cW6 zTx&c-AU<@n=4a1G-6rHSsT;aks~>wzeC$6>eCTG)&;9%C!AtEQddAOni=X?3$vq3* zlwPbqEPpMO1Hf1!i-53Y4{TVvrc``$lZ@NYa$e)E0B z=P;$``SqJLC*^9*7BO!f`vru3qpcV_NA&GN-bW?iK z&zSize>6~>x8;7_a=2iH*57H4s~O%VNy4AvsS;*L9My} zn$(fQlwKS^?O1F0&A~&|2vd6Qe>cDXa{FnA{rS)s#LpP;A z_m8LFpY{AY$M4VM{Qk_IXJ9c#=GqT;*Z-%T_S9> -rect -18 -1 32 26 +rect 0 50 54 79 << pwell >> -rect -18 -51 32 -6 +rect 0 0 54 50 << ntransistor >> -rect -6 -18 -4 -12 -rect 2 -24 4 -12 -rect 10 -24 12 -12 -rect 18 -18 20 -12 -rect -6 -36 -4 -28 -rect 2 -36 4 -28 -rect 10 -36 12 -28 -rect 18 -36 20 -28 +rect 14 35 16 41 +rect 22 29 24 41 +rect 30 29 32 41 +rect 38 35 40 41 +rect 14 17 16 25 +rect 22 17 24 25 +rect 30 17 32 25 +rect 38 17 40 25 << ptransistor >> -rect 2 5 4 9 -rect 10 5 12 9 +rect 22 58 24 62 +rect 30 58 32 62 << ndiffusion >> -rect -11 -14 -6 -12 -rect -7 -18 -6 -14 -rect -4 -18 -3 -12 -rect 1 -20 2 -12 -rect -3 -24 2 -20 -rect 4 -24 5 -12 -rect 9 -24 10 -12 -rect 12 -20 13 -12 -rect 17 -18 18 -12 -rect 20 -14 25 -12 -rect 20 -18 21 -14 -rect 12 -24 17 -20 -rect -11 -30 -6 -28 -rect -7 -34 -6 -30 -rect -11 -36 -6 -34 -rect -4 -36 2 -28 -rect 4 -36 5 -28 -rect 9 -36 10 -28 -rect 12 -36 18 -28 -rect 20 -30 25 -28 -rect 20 -34 21 -30 -rect 20 -36 25 -34 +rect 9 39 14 41 +rect 13 35 14 39 +rect 16 35 17 41 +rect 21 33 22 41 +rect 17 29 22 33 +rect 24 29 25 41 +rect 29 29 30 41 +rect 32 33 33 41 +rect 37 35 38 41 +rect 40 39 45 41 +rect 40 35 41 39 +rect 32 29 37 33 +rect 9 23 14 25 +rect 13 19 14 23 +rect 9 17 14 19 +rect 16 17 22 25 +rect 24 17 25 25 +rect 29 17 30 25 +rect 32 17 38 25 +rect 40 23 45 25 +rect 40 19 41 23 +rect 40 17 45 19 << pdiffusion >> -rect 1 5 2 9 -rect 4 5 5 9 -rect 9 5 10 9 -rect 12 5 13 9 +rect 21 58 22 62 +rect 24 58 25 62 +rect 29 58 30 62 +rect 32 58 33 62 << ndcontact >> -rect -11 -18 -7 -14 -rect -3 -20 1 -12 -rect 5 -24 9 -12 -rect 13 -20 17 -12 -rect 21 -18 25 -14 -rect -11 -34 -7 -30 -rect 5 -36 9 -28 -rect 21 -34 25 -30 +rect 9 35 13 39 +rect 17 33 21 41 +rect 25 29 29 41 +rect 33 33 37 41 +rect 41 35 45 39 +rect 9 19 13 23 +rect 25 17 29 25 +rect 41 19 45 23 << pdcontact >> -rect -3 5 1 9 -rect 5 5 9 9 -rect 13 5 17 9 +rect 17 58 21 62 +rect 25 58 29 62 +rect 33 58 37 62 << psubstratepcontact >> -rect 5 -44 9 -40 +rect 25 9 29 13 << nsubstratencontact >> -rect 5 19 9 23 +rect 25 72 29 76 << polysilicon >> -rect 2 9 4 11 -rect 10 9 12 11 -rect 2 -5 4 5 -rect 10 2 12 5 -rect 11 -2 12 2 -rect -6 -12 -4 -7 -rect 2 -9 3 -5 -rect 2 -12 4 -9 -rect 10 -12 12 -2 -rect 18 -12 20 -7 -rect -6 -20 -4 -18 -rect 18 -20 20 -18 -rect -6 -28 -4 -27 -rect 2 -28 4 -24 -rect 10 -28 12 -24 -rect 18 -28 20 -27 -rect -6 -38 -4 -36 -rect 2 -38 4 -36 -rect 10 -38 12 -36 -rect 18 -38 20 -36 +rect 22 62 24 64 +rect 30 62 32 64 +rect 22 48 24 58 +rect 30 55 32 58 +rect 31 51 32 55 +rect 14 41 16 46 +rect 22 44 23 48 +rect 22 41 24 44 +rect 30 41 32 51 +rect 38 41 40 46 +rect 14 33 16 35 +rect 38 33 40 35 +rect 14 25 16 26 +rect 22 25 24 29 +rect 30 25 32 29 +rect 38 25 40 26 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 << polycontact >> -rect 7 -2 11 2 -rect -10 -11 -6 -7 -rect 3 -9 7 -5 -rect 20 -11 24 -7 -rect -8 -27 -4 -23 -rect 18 -27 22 -23 +rect 27 51 31 55 +rect 10 42 14 46 +rect 23 44 27 48 +rect 40 42 44 46 +rect 12 26 16 30 +rect 38 26 42 30 << metal1 >> -rect -18 19 5 23 -rect 9 19 32 23 -rect -18 12 32 16 -rect -10 -7 -6 12 -rect -3 2 0 5 -rect -3 -2 7 2 -rect -3 -12 0 -2 -rect 14 -5 17 5 -rect 7 -9 17 -5 -rect 14 -12 17 -9 -rect 20 -7 24 12 -rect -14 -18 -11 -14 -rect 25 -18 28 -14 -rect 5 -28 9 -24 -rect 5 -40 9 -36 -rect -17 -44 5 -40 -rect 9 -44 31 -40 -rect -17 -51 -4 -47 -rect 0 -51 14 -47 -rect 18 -51 31 -47 +rect 0 72 25 76 +rect 29 72 54 76 +rect 0 65 54 69 +rect 10 46 14 65 +rect 17 55 20 58 +rect 17 51 27 55 +rect 17 41 20 51 +rect 34 48 37 58 +rect 27 44 37 48 +rect 34 41 37 44 +rect 40 46 44 65 +rect 6 35 9 39 +rect 45 35 48 39 +rect 25 25 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 << m2contact >> -rect 5 19 9 23 -rect 5 5 9 9 -rect -18 -18 -14 -14 -rect -4 -27 0 -23 -rect 28 -18 32 -14 -rect 14 -27 18 -23 -rect -11 -34 -7 -30 -rect 21 -34 25 -30 -rect -4 -51 0 -47 -rect 14 -51 18 -47 +rect 25 72 29 76 +rect 25 58 29 62 +rect 2 35 6 39 +rect 16 26 20 30 +rect 48 35 52 39 +rect 34 26 38 30 +rect 9 19 13 23 +rect 41 19 45 23 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> -rect -18 -14 -14 23 -rect -18 -51 -14 -18 -rect -11 -30 -7 23 -rect 5 9 9 19 -rect -11 -51 -7 -34 -rect -4 -47 0 -27 -rect 14 -47 18 -27 -rect 21 -30 25 23 -rect 21 -51 25 -34 -rect 28 -14 32 23 -rect 28 -51 32 -18 +rect 2 39 6 76 +rect 2 0 6 35 +rect 9 23 13 76 +rect 25 62 29 72 +rect 9 0 13 19 +rect 16 6 20 26 +rect 34 6 38 26 +rect 41 23 45 76 +rect 41 0 45 19 +rect 48 39 52 76 +rect 48 0 52 35 +<< bb >> +rect 0 0 54 74 << labels >> -rlabel metal1 7 -49 7 -49 1 wl1 -rlabel psubstratepcontact 7 -42 7 -42 1 gnd -rlabel m2contact 7 21 7 21 5 vdd -rlabel metal1 -1 14 -1 14 1 wl0 -rlabel metal2 -16 -46 -16 -46 2 bl0 -rlabel metal2 -9 -46 -9 -46 1 bl1 -rlabel metal2 23 -46 23 -46 1 br1 -rlabel metal2 30 -46 30 -46 8 br0 +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel m2contact 27 74 27 74 5 vdd +rlabel metal1 19 67 19 67 1 wl0 +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 << end >> diff --git a/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp new file mode 100644 index 00000000..1a52d8d0 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.6u l=0.4u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.4u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.4u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.4u +MM3 Q Q_bar vdd vdd p w=0.8u l=0.4u +MM2 Q_bar Q vdd vdd p w=0.8u l=0.4u +.ENDS + From 98a00f985b9bed12a85ec93cf001e392553c2627 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 25 Oct 2018 23:55:31 -0700 Subject: [PATCH 3/4] Changed the analytical delay model to accept multiport options. Little substance to the values generated. --- compiler/bitcells/pbitcell.py | 16 ++++++ compiler/characterizer/delay.py | 82 +++++++++++++++++++++---------- compiler/characterizer/lib.py | 2 +- compiler/modules/bank.py | 28 ++++++----- compiler/modules/bitcell_array.py | 12 ++++- 5 files changed, 98 insertions(+), 42 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 908df0e0..0242f2ce 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -884,3 +884,19 @@ class pbitcell(design.design): Q_bar_pos = self.inverter_pmos_right.get_pin("S").center() vdd_pos = self.inverter_pmos_right.get_pin("D").center() self.add_path("metal1", [Q_bar_pos, vdd_pos]) + + def analytical_delay(self, slew, load=0, swing = 0.5): + #FIXME: Delay copied exactly over from bitcell + from tech import spice + r = spice["min_tx_r"]*3 + c_para = spice["min_tx_drain_c"] + result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing) + return result + + def analytical_power(self, proc, vdd, temp, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 #temporary + total_power = self.return_power(dynamic, leakage) + return total_power \ No newline at end of file diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index d699dc06..5fdc1fef 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -807,46 +807,74 @@ class delay(simulation): #Add test cycle of read/write port pair. One port could have been used already, but the other has not. self.gen_test_cycles_one_port(cur_read_port, cur_write_port) - def analytical_delay(self,sram, slews, loads): + def analytical_delay(self, slews, loads): """ Return the analytical model results for the SRAM. """ - debug.check(OPTS.num_rw_ports < 2 and OPTS.num_w_ports < 1 and OPTS.num_r_ports < 1 , - "Analytical characterization does not currently support multiport.") + if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0: + debug.warning("Analytical characterization results are not supported for multiport.") - delay_lh = [] - delay_hl = [] - slew_lh = [] - slew_hl = [] + power = self.analytical_power(slews, loads) + port_data = self.get_empty_measure_data_dict() for slew in slews: for load in loads: self.set_load_slew(load,slew) - bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load) - # Convert from ps to ns - delay_lh.append(bank_delay.delay/1e3) - delay_hl.append(bank_delay.delay/1e3) - slew_lh.append(bank_delay.slew/1e3) - slew_hl.append(bank_delay.slew/1e3) + bank_delay = self.sram.analytical_delay(self.vdd_voltage, self.slew,self.load) + for port in range(self.total_ports): + for mname in self.delay_meas_names+self.power_meas_names: + if "power" in mname: + port_data[port][mname].append(power.dynamic) + elif "delay" in mname: + port_data[port][mname].append(bank_delay[port].delay/1e3) + elif "slew" in mname: + port_data[port][mname].append(bank_delay[port].slew/1e3) + else: + debug.error("Measurement name not recognized: {}".format(mname),1) + sram_data = { "min_period": 0, + "leakage_power": power.leakage} + + return (sram_data,port_data) - power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) + # delay_lh = [] + # delay_hl = [] + # slew_lh = [] + # slew_hl = [] + # for slew in slews: + # for load in loads: + # self.set_load_slew(load,slew) + # bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load) + # # Convert from ps to ns + # delay_lh.append(bank_delay.delay/1e3) + # delay_hl.append(bank_delay.delay/1e3) + # slew_lh.append(bank_delay.slew/1e3) + # slew_hl.append(bank_delay.slew/1e3) + + # power = self.analytical_power() + + # sram_data = { "min_period": 0, + # "leakage_power": power.leakage} + # port_data = [{"delay_lh": delay_lh, + # "delay_hl": delay_hl, + # "slew_lh": slew_lh, + # "slew_hl": slew_hl, + # "read0_power": power.dynamic, + # "read1_power": power.dynamic, + # "write0_power": power.dynamic, + # "write1_power": power.dynamic, + # }] + # return (sram_data,port_data) + + def analytical_power(self, slews, loads): + """Get the dynamic and leakage power from the SRAM""" + #slews unused, only last load is used + load = loads[-1] + power = self.sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) #convert from nW to mW power.dynamic /= 1e6 power.leakage /= 1e6 debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic)) debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) + return power - sram_data = { "min_period": 0, - "leakage_power": power.leakage} - port_data = [{"delay_lh": delay_lh, - "delay_hl": delay_hl, - "slew_lh": slew_lh, - "slew_hl": slew_hl, - "read0_power": power.dynamic, - "read1_power": power.dynamic, - "write0_power": power.dynamic, - "write1_power": power.dynamic, - }] - return (sram_data,port_data) - def gen_data(self): """ Generates the PWL data inputs for a simulation timing test. """ for write_port in self.write_index: diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6added12..6cc177f6 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -482,7 +482,7 @@ class lib: if not hasattr(self,"d"): self.d = delay(self.sram, self.sp_file, self.corner) if self.use_model: - char_results = self.d.analytical_delay(self.sram,self.slews,self.loads) + char_results = self.d.analytical_delay(self.slews,self.loads) self.char_sram_results, self.char_port_results = char_results else: probe_address = "1" * self.sram.addr_size diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 0fb6be60..1e9401b8 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -927,23 +927,27 @@ class bank(design.design): def analytical_delay(self, vdd, slew, load): """ return analytical delay of the bank""" + results = [] + decoder_delay = self.row_decoder.analytical_delay(slew, self.wordline_driver.input_load()) word_driver_delay = self.wordline_driver.analytical_delay(decoder_delay.slew, self.bitcell_array.input_load()) + #FIXME: Array delay is the same for every port. bitcell_array_delay = self.bitcell_array.analytical_delay(word_driver_delay.slew) - if self.words_per_row > 1: - port = 0 #Analytical delay only supports single port - column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew, - self.sense_amp_array.input_load()) - else: - column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew) - - bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew, - self.bitcell_array.output_load()) - # output load of bitcell_array is set to be only small part of bl for sense amp. + #This also essentially creates the same delay for each port. Good structure, no substance + for port in range(self.total_ports): + if self.words_per_row > 1: + column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew, + self.sense_amp_array.input_load()) + else: + column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew) + + bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew, + self.bitcell_array.output_load()) + # output load of bitcell_array is set to be only small part of bl for sense amp. + results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) - result = decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay - return result + return results diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 511ef9a8..8328a0cf 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -199,13 +199,21 @@ class bitcell_array(design.design): return total_power def gen_wl_wire(self): - wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc("minwidth_metal1")) + if OPTS.netlist_only: + width = 0 + else: + width = self.width + wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1")) wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell return wl_wire def gen_bl_wire(self): + if OPTS.netlist_only: + height = 0 + else: + height = self.height bl_pos = 0 - bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc("minwidth_metal1")) + bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1")) bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell return bl_wire From 6dd959b638677487a234c87eb07630acde37f553 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 2 Nov 2018 16:34:26 -0700 Subject: [PATCH 4/4] Fix error in 8mux test. Fix comment in all tests. --- compiler/tests/00_code_format_check_test.py | 2 +- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 2 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_wire_test.py | 2 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 2 +- compiler/tests/04_single_level_column_mux_test.py | 2 +- compiler/tests/05_bitcell_1rw_1r_array_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- compiler/tests/06_hierarchical_decoder_test.py | 2 +- compiler/tests/06_hierarchical_predecode2x4_test.py | 2 +- compiler/tests/06_hierarchical_predecode3x8_test.py | 2 +- compiler/tests/07_single_level_column_mux_array_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/08_wordline_driver_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/11_dff_buf_test.py | 2 +- compiler/tests/11_dff_inv_array_test.py | 2 +- compiler/tests/11_dff_inv_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- compiler/tests/14_replica_bitline_test.py | 2 +- compiler/tests/16_control_logic_test.py | 2 +- compiler/tests/19_bank_select_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_test.py | 2 +- compiler/tests/20_psram_1bank_nomux_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/20_sram_4bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_4mux_func_test.py | 4 ++-- compiler/tests/22_psram_1bank_8mux_func_test.py | 3 ++- compiler/tests/22_psram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_8mux_func_test.py | 3 ++- compiler/tests/22_sram_1bank_nomux_func_test.py | 2 +- compiler/tests/23_lib_sram_model_test.py | 2 +- compiler/tests/23_lib_sram_prune_test.py | 2 +- compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 +- compiler/tests/26_pex_test.py | 2 +- compiler/tests/27_worst_case_delay_test.py | 2 +- compiler/tests/30_openram_test.py | 2 +- 76 files changed, 79 insertions(+), 77 deletions(-) diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py index 026f7e2b..869e81bd 100755 --- a/compiler/tests/00_code_format_check_test.py +++ b/compiler/tests/00_code_format_check_test.py @@ -116,7 +116,7 @@ def check_print_output(file_name): return(count) -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index b809c14d..046e6378 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -39,7 +39,7 @@ def setup_files(): return (gds_dir, gds_files) -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 0b35f159..0367c5f2 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -59,7 +59,7 @@ def setup_files(): return (gds_dir, sp_dir, allnames) -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 2fab1c4e..33aa45ae 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -43,7 +43,7 @@ class contact_test(openram_test): -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index f70d00be..915c5c78 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -84,7 +84,7 @@ class path_test(openram_test): -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 727c24f0..9a81810e 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -25,7 +25,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 04b9ab64..a3ed99ff 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -25,7 +25,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 20343b2e..e1febdbc 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -27,7 +27,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 37933702..af9a5d42 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -27,7 +27,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 09788a5e..08a20898 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -27,7 +27,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index f43d7dc7..01857eda 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -27,7 +27,7 @@ class ptx_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 557fee5b..1b18e14b 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -121,7 +121,7 @@ class wire_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 0b6bd8f5..e5dbbc5e 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -94,7 +94,7 @@ class pbitcell_test(openram_test): -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 3a7f846a..d457d2a9 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -25,7 +25,7 @@ class pinv_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index c1bb6aba..77ff5454 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -24,7 +24,7 @@ class pinv_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index 555aa0e5..49cb1cb1 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -23,7 +23,7 @@ class pinv_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 6882a719..84bc55ee 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -25,7 +25,7 @@ class pinv_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 9c55ebe3..d35f1ec7 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -23,7 +23,7 @@ class pinvbuf_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index b6739e4e..a2ac9288 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -27,7 +27,7 @@ class pnand2_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index db3817f5..f6daedda 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -27,7 +27,7 @@ class pnand3_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 978c03ad..ce4b19ae 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -26,7 +26,7 @@ class pnor2_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 02de2efd..e5419dab 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -39,7 +39,7 @@ class precharge_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 7a803d1c..ce9f00b9 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -37,7 +37,7 @@ class replica_pbitcell_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 3a7d6399..c43b15fd 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -41,7 +41,7 @@ class single_level_column_mux_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 68dcc409..1223085e 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -29,7 +29,7 @@ class bitcell_1rw_1r_array_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 4ea5c65a..93668e05 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -25,7 +25,7 @@ class array_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 4fc75ac5..4da5bec9 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -44,7 +44,7 @@ class pbitcell_array_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 513e07a8..09201149 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -69,7 +69,7 @@ class hierarchical_decoder_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index bcfd207a..e16916d6 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -35,7 +35,7 @@ class hierarchical_predecode2x4_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b89f4bea..ed5da57c 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -35,7 +35,7 @@ class hierarchical_predecode3x8_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 63f69bc5..800292b6 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -54,7 +54,7 @@ class single_level_column_mux_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index be8fc9d7..5ea9931b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -39,7 +39,7 @@ class precharge_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 7f0ca275..369b6774 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -37,7 +37,7 @@ class wordline_driver_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index af2c974c..a18631f9 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -42,7 +42,7 @@ class sense_amp_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index ab9dc615..fa374181 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -42,7 +42,7 @@ class write_driver_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index a55c6407..eed41dda 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -31,7 +31,7 @@ class dff_array_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index f0b75552..d2932cac 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -31,7 +31,7 @@ class dff_buf_array_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index f434f768..c9c25f16 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -23,7 +23,7 @@ class dff_buf_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/11_dff_inv_array_test.py b/compiler/tests/11_dff_inv_array_test.py index 2196a3f2..ed03e6bc 100755 --- a/compiler/tests/11_dff_inv_array_test.py +++ b/compiler/tests/11_dff_inv_array_test.py @@ -31,7 +31,7 @@ class dff_inv_array_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/11_dff_inv_test.py b/compiler/tests/11_dff_inv_test.py index 43d49246..53a92852 100755 --- a/compiler/tests/11_dff_inv_test.py +++ b/compiler/tests/11_dff_inv_test.py @@ -23,7 +23,7 @@ class dff_inv_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 4f9cfa3e..cb789155 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -27,7 +27,7 @@ class tri_gate_array_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 2cc745c2..1052f0de 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -23,7 +23,7 @@ class delay_chain_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index 6797bc65..9853b581 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -70,7 +70,7 @@ class replica_bitline_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 7a4ff768..ef435c4c 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -53,7 +53,7 @@ class control_logic_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index 23b7ec46..1245926b 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -40,7 +40,7 @@ class bank_select_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 4fceafec..9bf32423 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -49,7 +49,7 @@ class multi_bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 03544587..32d3917a 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -54,7 +54,7 @@ class multi_bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index d45283e0..dee59175 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -137,7 +137,7 @@ class psingle_bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 3c32b30d..da411d1f 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -48,7 +48,7 @@ class single_bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_psram_1bank_nomux_test.py b/compiler/tests/20_psram_1bank_nomux_test.py index 6106763c..a2992cba 100755 --- a/compiler/tests/20_psram_1bank_nomux_test.py +++ b/compiler/tests/20_psram_1bank_nomux_test.py @@ -128,7 +128,7 @@ class sram_1bank_test(openram_test): """ globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 8c275e7c..2c8e28f0 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -29,7 +29,7 @@ class sram_1bank_2mux_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 4ff443dc..489ff354 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -29,7 +29,7 @@ class sram_1bank_4mux_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index 695dcffe..2595582f 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -29,7 +29,7 @@ class sram_1bank_8mux_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index a89fb4e5..783bcad2 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -29,7 +29,7 @@ class sram_1bank_nomux_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index ff9fbaea..ab8c6ec2 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -48,7 +48,7 @@ class sram_2bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/20_sram_4bank_test.py b/compiler/tests/20_sram_4bank_test.py index fb34d3b0..25649e8e 100755 --- a/compiler/tests/20_sram_4bank_test.py +++ b/compiler/tests/20_sram_4bank_test.py @@ -47,7 +47,7 @@ class sram_4bank_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index a5aca3e8..5facb482 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -81,7 +81,7 @@ class timing_sram_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 9bfdb24b..faa8617d 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -52,7 +52,7 @@ class timing_setup_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 45a9b7f6..3ef27fc5 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -81,7 +81,7 @@ class timing_sram_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index d58bfc50..924d05a5 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -53,7 +53,7 @@ class timing_setup_test(openram_test): reload(characterizer) globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index d8233d08..1e1367ed 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -49,7 +49,7 @@ class psram_1bank_2mux_func_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 1ae684d9..d62e2855 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test") +#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test") class psram_1bank_4mux_func_test(openram_test): def runTest(self): @@ -49,7 +49,7 @@ class psram_1bank_4mux_func_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index d81e76f9..02ea2f3b 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -37,6 +37,7 @@ class psram_1bank_8mux_func_test(openram_test): c.words_per_row, c.num_banks)) s = sram(c, name="sram") + tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -48,7 +49,7 @@ class psram_1bank_8mux_func_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 681e24d5..ce852dff 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -49,7 +49,7 @@ class psram_1bank_nomux_func_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 7779ed4f..8b195c95 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -47,7 +47,7 @@ class sram_1bank_2mux_func_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index c16b86fe..cf972843 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -47,7 +47,7 @@ class sram_1bank_4mux_func_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index be8e538f..61c0efb7 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -38,6 +38,7 @@ class sram_1bank_8mux_func_test(openram_test): c.words_per_row, c.num_banks)) s = sram(c, name="sram") + tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) @@ -49,7 +50,7 @@ class sram_1bank_8mux_func_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 52d63f4a..43d640ab 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -47,7 +47,7 @@ class sram_1bank_nomux_func_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 8d5064d5..b111a57d 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -44,7 +44,7 @@ class lib_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 952072aa..7f0a9c47 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -55,7 +55,7 @@ class lib_test(openram_test): reload(characterizer) globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 1b2d317c..5534598e 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -54,7 +54,7 @@ class lib_test(openram_test): reload(characterizer) globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index f66104b6..d4bf2619 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -42,7 +42,7 @@ class lef_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 48ba29e8..eebeb258 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -38,7 +38,7 @@ class verilog_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index edb344f9..d374e485 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -306,7 +306,7 @@ class sram_func_test(openram_test): sti_file.file.close() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py index 42a07bef..52dd3422 100755 --- a/compiler/tests/27_worst_case_delay_test.py +++ b/compiler/tests/27_worst_case_delay_test.py @@ -73,7 +73,7 @@ class worst_case_timing_sram_test(openram_test): globals.end_openram() -# instantiate a copdsay of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 038a2e15..7450dfba 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -83,7 +83,7 @@ class openram_test(openram_test): globals.end_openram() -# instantiate a copy of the class to actually run the test +# run the test from the command line if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:]