diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py
index 9cec7d8d..2f13a910 100644
--- a/compiler/bitcells/bitcell_1rw_1r.py
+++ b/compiler/bitcells/bitcell_1rw_1r.py
@@ -19,9 +19,9 @@ class bitcell_1rw_1r(design.design):
         design.design.__init__(self, "cell_1rw_1r")
         debug.info(2, "Create bitcell with 1RW and 1R Port")
 
-        self.width = bitcell.width
-        self.height = bitcell.height
-        self.pin_map = bitcell.pin_map
+        self.width = bitcell_1rw_1r.width
+        self.height = bitcell_1rw_1r.height
+        self.pin_map = bitcell_1rw_1r.pin_map
 
     def analytical_delay(self, slew, load=0, swing = 0.5):
         # delay of bit cell is not like a driver(from WL)
@@ -38,12 +38,12 @@ class bitcell_1rw_1r(design.design):
  
     def list_bitcell_pins(self, col, row):
         """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
-        bitcell_pins = ["bl0[{0}]".format(col),
-                        "br0[{0}]".format(col),
-                        "bl1[{0}]".format(col),
-                        "br1[{0}]".format(col),
-                        "wl0[{0}]".format(row),
-                        "wl1[{0}]".format(row),
+        bitcell_pins = ["bl0_{0}".format(col),
+                        "br0_{0}".format(col),
+                        "bl1_{0}".format(col),
+                        "br1_{0}".format(col),
+                        "wl0_{0}".format(row),
+                        "wl1_{0}".format(row),
                         "vdd",
                         "gnd"]
         return bitcell_pins
diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index 908df0e0..0242f2ce 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -884,3 +884,19 @@ class pbitcell(design.design):
         Q_bar_pos = self.inverter_pmos_right.get_pin("S").center()
         vdd_pos = self.inverter_pmos_right.get_pin("D").center()
         self.add_path("metal1", [Q_bar_pos, vdd_pos])
+
+    def analytical_delay(self, slew, load=0, swing = 0.5):
+        #FIXME: Delay copied exactly over from bitcell
+        from tech import spice
+        r = spice["min_tx_r"]*3
+        c_para = spice["min_tx_drain_c"]
+        result = self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew, swing = swing)
+        return result
+        
+    def analytical_power(self, proc, vdd, temp, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
\ No newline at end of file
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index d699dc06..5fdc1fef 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -807,46 +807,74 @@ class delay(simulation):
             #Add test cycle of read/write port pair. One port could have been used already, but the other has not.
             self.gen_test_cycles_one_port(cur_read_port, cur_write_port)
 
-    def analytical_delay(self,sram, slews, loads):
+    def analytical_delay(self, slews, loads):
         """ Return the analytical model results for the SRAM. 
         """
-        debug.check(OPTS.num_rw_ports < 2 and OPTS.num_w_ports < 1 and OPTS.num_r_ports < 1 ,
-                    "Analytical characterization does not currently support multiport.")
+        if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
+            debug.warning("Analytical characterization results are not supported for multiport.")
         
-        delay_lh = []
-        delay_hl = []
-        slew_lh = []
-        slew_hl = []
+        power = self.analytical_power(slews, loads)
+        port_data = self.get_empty_measure_data_dict()
         for slew in slews:
             for load in loads:
                 self.set_load_slew(load,slew)
-                bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load)
-                # Convert from ps to ns
-                delay_lh.append(bank_delay.delay/1e3)
-                delay_hl.append(bank_delay.delay/1e3)
-                slew_lh.append(bank_delay.slew/1e3)
-                slew_hl.append(bank_delay.slew/1e3)
+                bank_delay = self.sram.analytical_delay(self.vdd_voltage, self.slew,self.load)
+                for port in range(self.total_ports):
+                    for mname in self.delay_meas_names+self.power_meas_names:
+                        if "power" in mname:
+                            port_data[port][mname].append(power.dynamic)
+                        elif "delay" in mname:
+                            port_data[port][mname].append(bank_delay[port].delay/1e3)
+                        elif "slew" in mname:
+                            port_data[port][mname].append(bank_delay[port].slew/1e3)
+                        else:
+                            debug.error("Measurement name not recognized: {}".format(mname),1)
+        sram_data = { "min_period": 0, 
+                      "leakage_power": power.leakage}                    
+         
+        return (sram_data,port_data)
         
-        power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) 
+        # delay_lh = []
+        # delay_hl = []
+        # slew_lh = []
+        # slew_hl = []
+        # for slew in slews:
+            # for load in loads:
+                # self.set_load_slew(load,slew)
+                # bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load)
+                # # Convert from ps to ns
+                # delay_lh.append(bank_delay.delay/1e3)
+                # delay_hl.append(bank_delay.delay/1e3)
+                # slew_lh.append(bank_delay.slew/1e3)
+                # slew_hl.append(bank_delay.slew/1e3)
+        
+        # power = self.analytical_power()
+        
+        # sram_data = { "min_period": 0, 
+                    # "leakage_power": power.leakage}
+        # port_data = [{"delay_lh": delay_lh,
+                      # "delay_hl": delay_hl,
+                      # "slew_lh": slew_lh,
+                      # "slew_hl": slew_hl,
+                      # "read0_power": power.dynamic,
+                      # "read1_power": power.dynamic,
+                      # "write0_power": power.dynamic,
+                      # "write1_power": power.dynamic,
+                # }]
+        # return (sram_data,port_data)
+    
+    def analytical_power(self, slews, loads):
+        """Get the dynamic and leakage power from the SRAM"""
+        #slews unused, only last load is used
+        load = loads[-1]
+        power = self.sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load) 
         #convert from nW to mW
         power.dynamic /= 1e6 
         power.leakage /= 1e6
         debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))        
         debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) 
+        return power
         
-        sram_data = { "min_period": 0, 
-                    "leakage_power": power.leakage}
-        port_data = [{"delay_lh": delay_lh,
-                      "delay_hl": delay_hl,
-                      "slew_lh": slew_lh,
-                      "slew_hl": slew_hl,
-                      "read0_power": power.dynamic,
-                      "read1_power": power.dynamic,
-                      "write0_power": power.dynamic,
-                      "write1_power": power.dynamic,
-                }]
-        return (sram_data,port_data)
-
     def gen_data(self):
         """ Generates the PWL data inputs for a simulation timing test. """
         for write_port in self.write_index:
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 7ae25b73..6cc177f6 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -17,7 +17,6 @@ class lib:
         self.sram = sram
         self.sp_file = sp_file        
         self.use_model = use_model
-        #self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
         self.set_port_indices()
         
         self.prepare_tables()
@@ -27,30 +26,11 @@ class lib:
         self.characterize_corners()
         
     def set_port_indices(self):
+        """Copies port information set in the SRAM instance"""
         self.total_port_num = self.sram.total_ports
         self.read_ports = self.sram.read_index
         self.write_ports = self.sram.write_index
-        
-    def gen_port_names(self):
-        """Generates the port names to be written to the lib file"""
-        #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here.
-        self.write_ports = []
-        self.read_ports = []
-        self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
-        
-        #save a member variable to avoid accessing global. readwrite ports have different control signals.
-        self.readwrite_port_num = OPTS.num_rw_ports
-        
-        #Generate the port names. readwrite ports are required to be added first for this to work.
-        for readwrite_port_num in range(OPTS.num_rw_ports):
-            self.read_ports.append(readwrite_port_num)
-            self.write_ports.append(readwrite_port_num)
-        #This placement is intentional. It makes indexing input data easier. See self.data_values
-        for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports):
-            self.read_ports.append(read_port_num)
-        for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports):
-            self.write_ports.append(write_port_num)
-        
+             
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
@@ -502,7 +482,7 @@ class lib:
         if not hasattr(self,"d"):
             self.d = delay(self.sram, self.sp_file, self.corner)
             if self.use_model:
-                char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
+                char_results = self.d.analytical_delay(self.slews,self.loads)
                 self.char_sram_results, self.char_port_results = char_results  
             else:
                 probe_address = "1" * self.sram.addr_size
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 0fb6be60..1e9401b8 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -927,23 +927,27 @@ class bank(design.design):
         
     def analytical_delay(self, vdd, slew, load):
         """ return  analytical delay of the bank"""
+        results = []
+        
         decoder_delay = self.row_decoder.analytical_delay(slew, self.wordline_driver.input_load())
 
         word_driver_delay = self.wordline_driver.analytical_delay(decoder_delay.slew, self.bitcell_array.input_load())
 
+        #FIXME: Array delay is the same for every port.
         bitcell_array_delay = self.bitcell_array.analytical_delay(word_driver_delay.slew)
 
-        if self.words_per_row > 1:
-            port = 0 #Analytical delay only supports single port
-            column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew,
-                                                                     self.sense_amp_array.input_load())
-        else:
-            column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
-            
-        bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew,
-                                                                    self.bitcell_array.output_load())
-        # output load of bitcell_array is set to be only small part of bl for sense amp.
+        #This also essentially creates the same delay for each port. Good structure, no substance
+        for port in range(self.total_ports):
+            if self.words_per_row > 1:
+                column_mux_delay = self.column_mux_array[port].analytical_delay(vdd, bitcell_array_delay.slew,
+                                                                         self.sense_amp_array.input_load())
+            else:
+                column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
+                
+            bl_t_data_out_delay = self.sense_amp_array.analytical_delay(column_mux_delay.slew,
+                                                                        self.bitcell_array.output_load())
+            # output load of bitcell_array is set to be only small part of bl for sense amp.
+            results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) 
 
-        result = decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay 
-        return result
+        return results
         
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 511ef9a8..8328a0cf 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -199,13 +199,21 @@ class bitcell_array(design.design):
         return total_power
 
     def gen_wl_wire(self):
-        wl_wire = self.generate_rc_net(int(self.column_size), self.width, drc("minwidth_metal1"))
+        if OPTS.netlist_only:
+            width = 0
+        else:
+            width = self.width
+        wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1"))
         wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
         return wl_wire
 
     def gen_bl_wire(self):
+        if OPTS.netlist_only:
+            height = 0
+        else:
+            height = self.height
         bl_pos = 0
-        bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), self.height, drc("minwidth_metal1"))
+        bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1"))
         bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
         return bl_wire
 
diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py
index 026f7e2b..869e81bd 100755
--- a/compiler/tests/00_code_format_check_test.py
+++ b/compiler/tests/00_code_format_check_test.py
@@ -116,7 +116,7 @@ def check_print_output(file_name):
     return(count)
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py
index b809c14d..046e6378 100755
--- a/compiler/tests/01_library_drc_test.py
+++ b/compiler/tests/01_library_drc_test.py
@@ -39,7 +39,7 @@ def setup_files():
     return (gds_dir, gds_files)
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py
index 0b35f159..0367c5f2 100755
--- a/compiler/tests/02_library_lvs_test.py
+++ b/compiler/tests/02_library_lvs_test.py
@@ -59,7 +59,7 @@ def setup_files():
 
     return (gds_dir, sp_dir, allnames)
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py
index 2fab1c4e..33aa45ae 100755
--- a/compiler/tests/03_contact_test.py
+++ b/compiler/tests/03_contact_test.py
@@ -43,7 +43,7 @@ class contact_test(openram_test):
         
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py
index f70d00be..915c5c78 100755
--- a/compiler/tests/03_path_test.py
+++ b/compiler/tests/03_path_test.py
@@ -84,7 +84,7 @@ class path_test(openram_test):
         
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py
index 727c24f0..9a81810e 100755
--- a/compiler/tests/03_ptx_1finger_nmos_test.py
+++ b/compiler/tests/03_ptx_1finger_nmos_test.py
@@ -25,7 +25,7 @@ class ptx_test(openram_test):
         globals.end_openram()
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py
index 04b9ab64..a3ed99ff 100755
--- a/compiler/tests/03_ptx_1finger_pmos_test.py
+++ b/compiler/tests/03_ptx_1finger_pmos_test.py
@@ -25,7 +25,7 @@ class ptx_test(openram_test):
         globals.end_openram()
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py
index 20343b2e..e1febdbc 100755
--- a/compiler/tests/03_ptx_3finger_nmos_test.py
+++ b/compiler/tests/03_ptx_3finger_nmos_test.py
@@ -27,7 +27,7 @@ class ptx_test(openram_test):
         globals.end_openram()
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py
index 37933702..af9a5d42 100755
--- a/compiler/tests/03_ptx_3finger_pmos_test.py
+++ b/compiler/tests/03_ptx_3finger_pmos_test.py
@@ -27,7 +27,7 @@ class ptx_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py
index 09788a5e..08a20898 100755
--- a/compiler/tests/03_ptx_4finger_nmos_test.py
+++ b/compiler/tests/03_ptx_4finger_nmos_test.py
@@ -27,7 +27,7 @@ class ptx_test(openram_test):
         globals.end_openram()
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py
index f43d7dc7..01857eda 100755
--- a/compiler/tests/03_ptx_4finger_pmos_test.py
+++ b/compiler/tests/03_ptx_4finger_pmos_test.py
@@ -27,7 +27,7 @@ class ptx_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py
index 557fee5b..1b18e14b 100755
--- a/compiler/tests/03_wire_test.py
+++ b/compiler/tests/03_wire_test.py
@@ -121,7 +121,7 @@ class wire_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_bitcell_1rw_1r_test.py b/compiler/tests/04_bitcell_1rw_1r_test.py
deleted file mode 100755
index 67db3710..00000000
--- a/compiler/tests/04_bitcell_1rw_1r_test.py
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/env python3
-"""
-Run regresion tests on a parameterized bitcell
-"""
-
-import unittest
-from testutils import header,openram_test
-import sys,os
-sys.path.append(os.path.join(sys.path[0],".."))
-import globals
-from globals import OPTS
-import debug
-
-OPTS = globals.OPTS
-
-@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test")
-class bitcell_1rw_1r_test(openram_test):
-
-    def runTest(self):
-        OPTS.bitcell = "bitcell_1rw_1r"
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        from bitcell import bitcell
-        from bitcell_1rw_1r import bitcell_1rw_1r
-        import tech
-        OPTS.num_rw_ports=1
-        OPTS.num_w_ports=0
-        OPTS.num_r_ports=1
-        debug.info(2, "Bitcell with 1 read/write and 1 read port")
-        #tx = bitcell_1rw_1r()
-        tx = bitcell()
-        self.local_check(tx)
-
-        globals.end_openram()
-
-
-
-# instantiate a copy of the class to actually run the test
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main()
diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index 0b6bd8f5..e5dbbc5e 100755
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -94,7 +94,7 @@ class pbitcell_test(openram_test):
 
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py
index 3a7f846a..d457d2a9 100755
--- a/compiler/tests/04_pinv_10x_test.py
+++ b/compiler/tests/04_pinv_10x_test.py
@@ -25,7 +25,7 @@ class pinv_test(openram_test):
         globals.end_openram()        
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py
index c1bb6aba..77ff5454 100755
--- a/compiler/tests/04_pinv_1x_beta_test.py
+++ b/compiler/tests/04_pinv_1x_beta_test.py
@@ -24,7 +24,7 @@ class pinv_test(openram_test):
 
         globals.end_openram()        
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py
index 555aa0e5..49cb1cb1 100755
--- a/compiler/tests/04_pinv_1x_test.py
+++ b/compiler/tests/04_pinv_1x_test.py
@@ -23,7 +23,7 @@ class pinv_test(openram_test):
 
         globals.end_openram()        
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py
index 6882a719..84bc55ee 100755
--- a/compiler/tests/04_pinv_2x_test.py
+++ b/compiler/tests/04_pinv_2x_test.py
@@ -25,7 +25,7 @@ class pinv_test(openram_test):
         globals.end_openram()        
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py
index 9c55ebe3..d35f1ec7 100755
--- a/compiler/tests/04_pinvbuf_test.py
+++ b/compiler/tests/04_pinvbuf_test.py
@@ -23,7 +23,7 @@ class pinvbuf_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py
index b6739e4e..a2ac9288 100755
--- a/compiler/tests/04_pnand2_test.py
+++ b/compiler/tests/04_pnand2_test.py
@@ -27,7 +27,7 @@ class pnand2_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py
index db3817f5..f6daedda 100755
--- a/compiler/tests/04_pnand3_test.py
+++ b/compiler/tests/04_pnand3_test.py
@@ -27,7 +27,7 @@ class pnand3_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py
index 978c03ad..ce4b19ae 100755
--- a/compiler/tests/04_pnor2_test.py
+++ b/compiler/tests/04_pnor2_test.py
@@ -26,7 +26,7 @@ class pnor2_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py
index 02de2efd..e5419dab 100755
--- a/compiler/tests/04_precharge_test.py
+++ b/compiler/tests/04_precharge_test.py
@@ -39,7 +39,7 @@ class precharge_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py
index 7a803d1c..ce9f00b9 100755
--- a/compiler/tests/04_replica_pbitcell_test.py
+++ b/compiler/tests/04_replica_pbitcell_test.py
@@ -37,7 +37,7 @@ class replica_pbitcell_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py
index 3a7d6399..c43b15fd 100755
--- a/compiler/tests/04_single_level_column_mux_test.py
+++ b/compiler/tests/04_single_level_column_mux_test.py
@@ -41,7 +41,7 @@ class single_level_column_mux_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py
new file mode 100755
index 00000000..1223085e
--- /dev/null
+++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+"""
+Run a regression test on a basic array
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
+
+class bitcell_1rw_1r_array_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        import bitcell_array
+
+        debug.info(2, "Testing 4x4 array for cell_1rw_1r")
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()
diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py
index 4ea5c65a..93668e05 100755
--- a/compiler/tests/05_bitcell_array_test.py
+++ b/compiler/tests/05_bitcell_array_test.py
@@ -25,7 +25,7 @@ class array_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index 4fc75ac5..4da5bec9 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -44,7 +44,7 @@ class pbitcell_array_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py
index 513e07a8..09201149 100755
--- a/compiler/tests/06_hierarchical_decoder_test.py
+++ b/compiler/tests/06_hierarchical_decoder_test.py
@@ -69,7 +69,7 @@ class hierarchical_decoder_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py
index bcfd207a..e16916d6 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_test.py
@@ -35,7 +35,7 @@ class hierarchical_predecode2x4_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py
index b89f4bea..ed5da57c 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_test.py
@@ -35,7 +35,7 @@ class hierarchical_predecode3x8_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py
index 63f69bc5..800292b6 100755
--- a/compiler/tests/07_single_level_column_mux_array_test.py
+++ b/compiler/tests/07_single_level_column_mux_array_test.py
@@ -54,7 +54,7 @@ class single_level_column_mux_test(openram_test):
         globals.end_openram()
         
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py
index be8fc9d7..5ea9931b 100755
--- a/compiler/tests/08_precharge_array_test.py
+++ b/compiler/tests/08_precharge_array_test.py
@@ -39,7 +39,7 @@ class precharge_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py
index 7f0ca275..369b6774 100755
--- a/compiler/tests/08_wordline_driver_test.py
+++ b/compiler/tests/08_wordline_driver_test.py
@@ -37,7 +37,7 @@ class wordline_driver_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py
index af2c974c..a18631f9 100755
--- a/compiler/tests/09_sense_amp_array_test.py
+++ b/compiler/tests/09_sense_amp_array_test.py
@@ -42,7 +42,7 @@ class sense_amp_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py
index ab9dc615..fa374181 100755
--- a/compiler/tests/10_write_driver_array_test.py
+++ b/compiler/tests/10_write_driver_array_test.py
@@ -42,7 +42,7 @@ class write_driver_test(openram_test):
         
         globals.end_openram()
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py
index a55c6407..eed41dda 100755
--- a/compiler/tests/11_dff_array_test.py
+++ b/compiler/tests/11_dff_array_test.py
@@ -31,7 +31,7 @@ class dff_array_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py
index f0b75552..d2932cac 100755
--- a/compiler/tests/11_dff_buf_array_test.py
+++ b/compiler/tests/11_dff_buf_array_test.py
@@ -31,7 +31,7 @@ class dff_buf_array_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py
index f434f768..c9c25f16 100755
--- a/compiler/tests/11_dff_buf_test.py
+++ b/compiler/tests/11_dff_buf_test.py
@@ -23,7 +23,7 @@ class dff_buf_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/11_dff_inv_array_test.py b/compiler/tests/11_dff_inv_array_test.py
index 2196a3f2..ed03e6bc 100755
--- a/compiler/tests/11_dff_inv_array_test.py
+++ b/compiler/tests/11_dff_inv_array_test.py
@@ -31,7 +31,7 @@ class dff_inv_array_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/11_dff_inv_test.py b/compiler/tests/11_dff_inv_test.py
index 43d49246..53a92852 100755
--- a/compiler/tests/11_dff_inv_test.py
+++ b/compiler/tests/11_dff_inv_test.py
@@ -23,7 +23,7 @@ class dff_inv_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py
index 4f9cfa3e..cb789155 100755
--- a/compiler/tests/12_tri_gate_array_test.py
+++ b/compiler/tests/12_tri_gate_array_test.py
@@ -27,7 +27,7 @@ class tri_gate_array_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py
index 2cc745c2..1052f0de 100755
--- a/compiler/tests/13_delay_chain_test.py
+++ b/compiler/tests/13_delay_chain_test.py
@@ -23,7 +23,7 @@ class delay_chain_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py
index 6797bc65..9853b581 100755
--- a/compiler/tests/14_replica_bitline_test.py
+++ b/compiler/tests/14_replica_bitline_test.py
@@ -70,7 +70,7 @@ class replica_bitline_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py
index 7a4ff768..ef435c4c 100755
--- a/compiler/tests/16_control_logic_test.py
+++ b/compiler/tests/16_control_logic_test.py
@@ -53,7 +53,7 @@ class control_logic_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py
index 23b7ec46..1245926b 100755
--- a/compiler/tests/19_bank_select_test.py
+++ b/compiler/tests/19_bank_select_test.py
@@ -40,7 +40,7 @@ class bank_select_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py
index 4fceafec..9bf32423 100755
--- a/compiler/tests/19_multi_bank_test.py
+++ b/compiler/tests/19_multi_bank_test.py
@@ -49,7 +49,7 @@ class multi_bank_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py
index 03544587..32d3917a 100755
--- a/compiler/tests/19_pmulti_bank_test.py
+++ b/compiler/tests/19_pmulti_bank_test.py
@@ -54,7 +54,7 @@ class multi_bank_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py
index d45283e0..dee59175 100755
--- a/compiler/tests/19_psingle_bank_test.py
+++ b/compiler/tests/19_psingle_bank_test.py
@@ -137,7 +137,7 @@ class psingle_bank_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py
index 3c32b30d..da411d1f 100755
--- a/compiler/tests/19_single_bank_test.py
+++ b/compiler/tests/19_single_bank_test.py
@@ -48,7 +48,7 @@ class single_bank_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_psram_1bank_nomux_test.py b/compiler/tests/20_psram_1bank_nomux_test.py
index 6106763c..a2992cba 100755
--- a/compiler/tests/20_psram_1bank_nomux_test.py
+++ b/compiler/tests/20_psram_1bank_nomux_test.py
@@ -128,7 +128,7 @@ class sram_1bank_test(openram_test):
         """
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py
index 8c275e7c..2c8e28f0 100755
--- a/compiler/tests/20_sram_1bank_2mux_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_test.py
@@ -29,7 +29,7 @@ class sram_1bank_2mux_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py
index 4ff443dc..489ff354 100755
--- a/compiler/tests/20_sram_1bank_4mux_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_test.py
@@ -29,7 +29,7 @@ class sram_1bank_4mux_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py
index 695dcffe..2595582f 100755
--- a/compiler/tests/20_sram_1bank_8mux_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_test.py
@@ -29,7 +29,7 @@ class sram_1bank_8mux_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py
index a89fb4e5..783bcad2 100755
--- a/compiler/tests/20_sram_1bank_nomux_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_test.py
@@ -29,7 +29,7 @@ class sram_1bank_nomux_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py
index ff9fbaea..ab8c6ec2 100755
--- a/compiler/tests/20_sram_2bank_test.py
+++ b/compiler/tests/20_sram_2bank_test.py
@@ -48,7 +48,7 @@ class sram_2bank_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/20_sram_4bank_test.py b/compiler/tests/20_sram_4bank_test.py
index fb34d3b0..25649e8e 100755
--- a/compiler/tests/20_sram_4bank_test.py
+++ b/compiler/tests/20_sram_4bank_test.py
@@ -47,7 +47,7 @@ class sram_4bank_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index a5aca3e8..5facb482 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -81,7 +81,7 @@ class timing_sram_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py
index 9bfdb24b..faa8617d 100755
--- a/compiler/tests/21_hspice_setuphold_test.py
+++ b/compiler/tests/21_hspice_setuphold_test.py
@@ -52,7 +52,7 @@ class timing_setup_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 45a9b7f6..3ef27fc5 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -81,7 +81,7 @@ class timing_sram_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py
index d58bfc50..924d05a5 100755
--- a/compiler/tests/21_ngspice_setuphold_test.py
+++ b/compiler/tests/21_ngspice_setuphold_test.py
@@ -53,7 +53,7 @@ class timing_setup_test(openram_test):
         reload(characterizer)
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py
index d8233d08..1e1367ed 100755
--- a/compiler/tests/22_psram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_2mux_func_test.py
@@ -49,7 +49,7 @@ class psram_1bank_2mux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py
index 1ae684d9..d62e2855 100755
--- a/compiler/tests/22_psram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_4mux_func_test.py
@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
+#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
 class psram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
@@ -49,7 +49,7 @@ class psram_1bank_4mux_func_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py
index d81e76f9..02ea2f3b 100755
--- a/compiler/tests/22_psram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_8mux_func_test.py
@@ -37,6 +37,7 @@ class psram_1bank_8mux_func_test(openram_test):
                                                                                                                 c.words_per_row,
                                                                                                                 c.num_banks))
         s = sram(c, name="sram")
+        tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
@@ -48,7 +49,7 @@ class psram_1bank_8mux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py
index 681e24d5..ce852dff 100755
--- a/compiler/tests/22_psram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_psram_1bank_nomux_func_test.py
@@ -49,7 +49,7 @@ class psram_1bank_nomux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py
index 7779ed4f..8b195c95 100755
--- a/compiler/tests/22_sram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_func_test.py
@@ -47,7 +47,7 @@ class sram_1bank_2mux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py
index c16b86fe..cf972843 100755
--- a/compiler/tests/22_sram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_4mux_func_test.py
@@ -47,7 +47,7 @@ class sram_1bank_4mux_func_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py
index be8e538f..61c0efb7 100755
--- a/compiler/tests/22_sram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_8mux_func_test.py
@@ -38,6 +38,7 @@ class sram_1bank_8mux_func_test(openram_test):
                                                                                                                 c.words_per_row,
                                                                                                                 c.num_banks))
         s = sram(c, name="sram")
+        tempspice = OPTS.openram_temp + "temp.sp"        
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
@@ -49,7 +50,7 @@ class sram_1bank_8mux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py
index 52d63f4a..43d640ab 100755
--- a/compiler/tests/22_sram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_func_test.py
@@ -47,7 +47,7 @@ class sram_1bank_nomux_func_test(openram_test):
         
         globals.end_openram()
         
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index 8d5064d5..b111a57d 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -44,7 +44,7 @@ class lib_test(openram_test):
             
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py
index 952072aa..7f0a9c47 100755
--- a/compiler/tests/23_lib_sram_prune_test.py
+++ b/compiler/tests/23_lib_sram_prune_test.py
@@ -55,7 +55,7 @@ class lib_test(openram_test):
         reload(characterizer)
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py
index 1b2d317c..5534598e 100755
--- a/compiler/tests/23_lib_sram_test.py
+++ b/compiler/tests/23_lib_sram_test.py
@@ -54,7 +54,7 @@ class lib_test(openram_test):
         reload(characterizer)
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py
index f66104b6..d4bf2619 100755
--- a/compiler/tests/24_lef_sram_test.py
+++ b/compiler/tests/24_lef_sram_test.py
@@ -42,7 +42,7 @@ class lef_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py
index 48ba29e8..eebeb258 100755
--- a/compiler/tests/25_verilog_sram_test.py
+++ b/compiler/tests/25_verilog_sram_test.py
@@ -38,7 +38,7 @@ class verilog_test(openram_test):
 
         globals.end_openram()
         
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py
index edb344f9..d374e485 100755
--- a/compiler/tests/26_pex_test.py
+++ b/compiler/tests/26_pex_test.py
@@ -306,7 +306,7 @@ class sram_func_test(openram_test):
         sti_file.file.close()
 
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py
index 42a07bef..52dd3422 100755
--- a/compiler/tests/27_worst_case_delay_test.py
+++ b/compiler/tests/27_worst_case_delay_test.py
@@ -73,7 +73,7 @@ class worst_case_timing_sram_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copdsay of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py
index 038a2e15..7450dfba 100755
--- a/compiler/tests/30_openram_test.py
+++ b/compiler/tests/30_openram_test.py
@@ -83,7 +83,7 @@ class openram_test(openram_test):
 
         globals.end_openram()
 
-# instantiate a copy of the class to actually run the test
+# run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
     del sys.argv[1:]
diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds
index 9f4e0650..fe12fc72 100644
Binary files a/technology/freepdk45/gds_lib/cell_1rw_1r.gds and b/technology/freepdk45/gds_lib/cell_1rw_1r.gds differ
diff --git a/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds
new file mode 100644
index 00000000..0b13d628
Binary files /dev/null and b/technology/scn4m_subm/gds_lib/cell_1rw_1r.gds differ
diff --git a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag
index 7d3823b8..e6420e89 100644
--- a/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag
+++ b/technology/scn4m_subm/mag_lib/cell_1rw_1r.mag
@@ -1,146 +1,148 @@
 magic
 tech scmos
-timestamp 1539900829
+timestamp 1540504134
 << nwell >>
-rect -18 -1 32 26
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 << pwell >>
-rect -18 -51 32 -6
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 << ntransistor >>
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 << ptransistor >>
-rect 2 5 4 9
-rect 10 5 12 9
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 << ndiffusion >>
-rect -11 -14 -6 -12
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-rect 1 5 2 9
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 << pdcontact >>
-rect -3 5 1 9
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 << psubstratepcontact >>
-rect 5 -44 9 -40
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 << nsubstratencontact >>
-rect 5 19 9 23
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 << polysilicon >>
-rect 2 9 4 11
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 << polycontact >>
-rect 7 -2 11 2
-rect -10 -11 -6 -7
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-rect 20 -11 24 -7
-rect -8 -27 -4 -23
-rect 18 -27 22 -23
+rect 27 51 31 55
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 << metal1 >>
-rect -18 19 5 23
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 << m2contact >>
-rect 5 19 9 23
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-rect -18 -18 -14 -14
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 << metal2 >>
-rect -18 -14 -14 23
-rect -18 -51 -14 -18
-rect -11 -30 -7 23
-rect 5 9 9 19
-rect -11 -51 -7 -34
-rect -4 -47 0 -27
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+rect 41 0 45 19
+rect 48 39 52 76
+rect 48 0 52 35
+<< bb >>
+rect 0 0 54 74
 << labels >>
-rlabel metal1 7 -49 7 -49 1 wl1
-rlabel psubstratepcontact 7 -42 7 -42 1 gnd
-rlabel m2contact 7 21 7 21 5 vdd
-rlabel metal1 -1 14 -1 14 1 wl0
-rlabel metal2 -16 -46 -16 -46 2 bl0
-rlabel metal2 -9 -46 -9 -46 1 bl1
-rlabel metal2 23 -46 23 -46 1 br1
-rlabel metal2 30 -46 30 -46 8 br0
+rlabel metal1 27 4 27 4 1 wl1
+rlabel psubstratepcontact 27 11 27 11 1 gnd
+rlabel m2contact 27 74 27 74 5 vdd
+rlabel metal1 19 67 19 67 1 wl0
+rlabel metal2 4 7 4 7 2 bl0
+rlabel metal2 11 7 11 7 1 bl1
+rlabel metal2 43 7 43 7 1 br1
+rlabel metal2 50 7 50 7 8 br0
 << end >>
diff --git a/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp
new file mode 100644
index 00000000..1a52d8d0
--- /dev/null
+++ b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp
@@ -0,0 +1,14 @@
+
+.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u
+MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u
+MM7 RA_to_R_left Q_bar gnd gnd n w=1.6u l=0.4u
+MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u
+MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u
+MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.4u
+MM1 Q Q_bar gnd gnd n w=2.4u l=0.4u
+MM0 Q_bar Q gnd gnd n w=2.4u l=0.4u
+MM3 Q Q_bar vdd vdd p w=0.8u l=0.4u
+MM2 Q_bar Q vdd vdd p w=0.8u l=0.4u
+.ENDS
+