From 6e40e2b9c7499602af880658d55e272ec01eadfb Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 11:07:04 -0800 Subject: [PATCH 1/9] Add initial README.md features with badges and links. --- HINTS.md | 110 +++++++++++++++++++++++ README.md | 186 +++++++++++---------------------------- images/license-badge.svg | 1 + 3 files changed, 161 insertions(+), 136 deletions(-) create mode 100644 HINTS.md create mode 100644 images/license-badge.svg diff --git a/HINTS.md b/HINTS.md new file mode 100644 index 00000000..b12704e5 --- /dev/null +++ b/HINTS.md @@ -0,0 +1,110 @@ +# Debugging + +When OpenRAM runs, it puts files in a temporary directory that is +shown in the banner at the top. Like: +``` + /tmp/openram_mrg_18128_temp/ +``` +This is where simulations and DRC/LVS get run so there is no network +traffic. The directory name is unique for each person and run of +OpenRAM to not clobber any files and allow simultaneous runs. If it +passes, the files are deleted. If it fails, you will see these files: ++ temp.gds is the layout (.mag files too if using SCMOS) ++ temp.sp is the netlist ++ test1.drc.err is the std err output of the DRC command ++ test1.drc.out is the standard output of the DRC command ++ test1.drc.results is the DRC results file ++ test1.lvs.err is the std err output of the LVS command ++ test1.lvs.out is the standard output of the LVS command ++ test1.lvs.results is the DRC results file + +Depending on your DRC/LVS tools, there will also be: ++ \_calibreDRC.rul\_ is the DRC rule file (Calibre) ++ dc_runset is the command file (Calibre) ++ extracted.sp (Calibre) ++ run_lvs.sh is a Netgen script for LVS (Netgen) ++ run_drc.sh is a Magic script for DRC (Magic) ++ .spice (Magic) + +If DRC/LVS fails, the first thing is to check if it ran in the .out and +.err file. This shows the standard output and error output from +running DRC/LVS. If there is a setup problem it will be shown here. + +If DRC/LVS runs, but doesn't pass, you then should look at the .results +file. If the DRC fails, it will typically show you the command that was used +to run Calibre or Magic+Netgen. + +To debug, you will need a layout viewer. I prefer to use Glade +on my Mac, but you can also use Calibre, Magic, etc. + +1. Calibre + + Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file: +``` + calibredrv temp.gds +``` + Select Verification->Start RVE and select the results database file in + the new form (e.g., test1.drc.db). This will start the RVE (results + viewer). Scroll through the check pane and find the DRC check with an + error. Select it and it will open some numbers to the right. Double + click on any of the errors in the result browser. These will be + labelled as numbers "1 2 3 4" for example will be 4 DRC errors. + + In the viewer ">" opens the layout down a level. + +2. Glade + + You can view errors in Glade as well. I like this because it is on my laptop. + You can get it from: http://www.peardrop.co.uk/glade/ + + To remote display over X windows, you need to disable OpenGL acceleration or use vnc + or something. You can disable by adding this to your .bashrc in bash: +``` + export GLADE_USE_OPENGL=no +``` + or in .cshrc/.tcshrc in csh/tcsh: +``` + setenv GLADE_USE_OPENGAL no +``` + To use this with the FreePDK45 or SCMOS layer views you should use the + tech files. Then create a .glade.py file in your user directory with + these commands to load the technology layers: +``` +ui().importCds("default", +"/Users/mrg/techfiles/freepdk45/display.drf", +"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1, +"/Users/mrg/techfiles/freepdk45/layers.map") +``` + Obviously, edit the paths to point to your directory. To switch + between processes, you have to change the importCds command (or you + can manually run the command each time you start glade). + + To load the errors, you simply do Verify->Import Calibre Errors select + the .results file from Calibre. + +3. Magic + + Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules + and Magic from: http://opencircuitdesign.com/ + + When running DRC or extraction, OpenRAM will load the GDS file, save + the .ext/.mag files, and export an extracted netlist (.spice). + +4. It is possible to use other viewers as well, such as: + * LayoutEditor http://www.layouteditor.net/ + + +# Example to output/input .gds layout files from/to Cadence + +1. To create your component layouts, you should stream them to + individual gds files using our provided layermap and flatten + cells. For example, +``` + strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds +``` +2. To stream a layout back into Cadence, do this: +``` + strmin -layerMap layers.map -attachTechFileOfLib NCSU\_TechLib\_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds +``` + When you import a gds file, make sure to attach the correct tech lib + or you will get incorrect layers in the resulting library. diff --git a/README.md b/README.md index b486823b..7824b9d2 100644 --- a/README.md +++ b/README.md @@ -1,23 +1,28 @@ -# BASIC SETUP +# OpenRAM +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg)](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/commits/dev) +[![License: BSD 3-clause](./image/license_badge.svg)](./LICENSE) -Please look at the OpenRAM ICCAD paper and presentation in the repository: -https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_paper.pdf -https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_presentation.pdf +An open-source static random access memory (SRAM) compiler. + +# Why OpenRAM? + + +# Basic Setup The OpenRAM compiler has very few dependencies: -* ngspice-26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) -* Python 3.5 and higher -* Python numpy (pip3 install numpy to install) -* flask_table (pip3 install flask to install) -* a setup script for each technology you want to use -* a technology directory for each technology with the base cells ++ ngspice-26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) ++ Python 3.5 and higher ++ Python numpy (pip3 install numpy to install) ++ flask_table (pip3 install flask to install) ++ a setup script for each technology you want to use ++ a technology directory for each technology with the base cells (comes with [SCMOS][SCMOS] and [FreePDK45][FreePDK45]) If you want to perform DRC and LVS, you will need either: -* Calibre (for FreePDK45 or SCMOS) -* Magic + Netgen (for SCMOS only) ++ Calibre (for [FreePDK45][FreePDK45] or [SCMOS][SCMOS]) ++ Magic + Netgen (for [SCMOS][SCMOS] only) -You must set two environment variables: OPENRAM_HOME should point to -the compiler source directory. OPENERAM_TECH should point to a root +You must set two environment variables: OPENRAM\_HOME should point to +the compiler source directory. OPENERAM\_TECH should point to a root technology directory that contains subdirs of all other technologies. For example, in bash, add to your .bashrc: ``` @@ -30,7 +35,7 @@ For example, in csh/tcsh, add to your .cshrc/.tcshrc: setenv OPENRAM_TECH "$HOME/openram/technology" ``` -We include the tech files necessary for FreePDK and SCMOS. The SCMOS +We include the tech files necessary for FreePDK and [SCMOS][SCMOS]. The [SCMOS][SCMOS] spice models, however, are generic and should be replaced with foundry models. If you are using FreePDK, you should also have that set up and have the @@ -43,16 +48,12 @@ For example, in csh/tcsh, add to your .tcshrc: ``` setenv FREEPDK45 "/bsoe/software/design-kits/FreePDK45" ``` -We do not distribute the PDK, but you may get it from: - https://www.eda.ncsu.edu/wiki/FreePDK45:Contents +We do not distribute the PDK, but you may download [FreePDK45][FreePDK45] -If you are using SCMOS, you should install Magic and netgen from: - http://opencircuitdesign.com/magic/ - http://opencircuitdesign.com/netgen/ -We have included the SCN4M design rules from QFlow: - http://opencircuitdesign.com/qflow/ +If you are using [SCMOS][SCMOS], you should install [Magic][Magic] and [Netgen][Netgen]. +We have included the SCN4M design rules from [Qflow][Qflow]. -# DIRECTORY STRUCTURE +# Directory Structure * compiler - openram compiler itself (pointed to by OPENRAM_HOME) * compiler/base - base data structure modules @@ -66,14 +67,14 @@ We have included the SCN4M design rules from QFlow: * compiler/tests - unit tests * technology - openram technology directory (pointed to by OPENRAM_TECH) * technology/freepdk45 - example configuration library for freepdk45 technology node - * technology/scn4m_subm - example configuration library SCMOS technology node + * technology/scn4m_subm - example configuration library [SCMOS][SCMOS] technology node * technology/scn3me_subm - unsupported configuration (not enough metal layers) * technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies * docs - LaTeX manual (outdated) * lib - IP library of pregenerated memories -# UNIT TESTS +# Unit Tests Regression testing performs a number of tests for all modules in OpenRAM. @@ -92,19 +93,19 @@ To increase the verbosity of the test, add one (or more) -v options: python tests/00_code_format_check_test.py -v -t freepdk45 ``` To specify a particular technology use "-t " such as -"-t freepdk45" or "-t scn4m_subm". The default for a unit test is scn4m_subm. +"-t freepdk45" or "-t scn4m\_subm". The default for a unit test is scn4m_subm. The default for openram.py is specified in the configuration file. -# CREATING CUSTOM TECHNOLOGIES +# Creating Custom Technologies -All setup scripts should be in the setup_scripts directory under the -$OPENRAM_TECH directory. Please look at the following file for an +All setup scripts should be in the setup\_scripts directory under the +$OPENRAM\_TECH directory. Please look at the following file for an example of what is needed for OpenRAM: ``` $OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py ``` -Each setup script should be named as: setup_openram_{tech name}.py. +Each setup script should be named as: setup\_openram\_{tech name}.py. Each specific technology (e.g., freepdk45) should be a subdirectory (e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files: @@ -124,115 +125,28 @@ Each specific technology (e.g., freepdk45) should be a subdirectory * Layer information * etc. -# DEBUGGING +# License -When OpenRAM runs, it puts files in a temporary directory that is -shown in the banner at the top. Like: -``` - /tmp/openram_mrg_18128_temp/ -``` -This is where simulations and DRC/LVS get run so there is no network -traffic. The directory name is unique for each person and run of -OpenRAM to not clobber any files and allow simultaneous runs. If it -passes, the files are deleted. If it fails, you will see these files: -* temp.gds is the layout -* (.mag files if using SCMOS) -* temp.sp is the netlist -* test1.drc.err is the std err output of the DRC command -* test1.drc.out is the standard output of the DRC command -* test1.drc.results is the DRC results file -* test1.lvs.err is the std err output of the LVS command -* test1.lvs.out is the standard output of the LVS command -* test1.lvs.results is the DRC results file +OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). -Depending on your DRC/LVS tools, there will also be: -* _calibreDRC.rul_ is the DRC rule file (Calibre) -* dc_runset is the command file (Calibre) -* extracted.sp (Calibre) -* run_lvs.sh is a Netgen script for LVS (Netgen) -* run_drc.sh is a Magic script for DRC (Magic) -* .spice (Magic) +# Contributors & Acknowledgment -If DRC/LVS fails, the first thing is to check if it ran in the .out and -.err file. This shows the standard output and error output from -running DRC/LVS. If there is a setup problem it will be shown here. - -If DRC/LVS runs, but doesn't pass, you then should look at the .results -file. If the DRC fails, it will typically show you the command that was used -to run Calibre or Magic+Netgen. - -To debug, you will need a layout viewer. I prefer to use Glade -on my Mac, but you can also use Calibre, Magic, etc. - -1. Calibre - - Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file: -``` - calibredrv temp.gds -``` - Select Verification->Start RVE and select the results database file in - the new form (e.g., test1.drc.db). This will start the RVE (results - viewer). Scroll through the check pane and find the DRC check with an - error. Select it and it will open some numbers to the right. Double - click on any of the errors in the result browser. These will be - labelled as numbers "1 2 3 4" for example will be 4 DRC errors. - - In the viewer ">" opens the layout down a level. - -2. Glade - - You can view errors in Glade as well. I like this because it is on my laptop. - You can get it from: http://www.peardrop.co.uk/glade/ - - To remote display over X windows, you need to disable OpenGL acceleration or use vnc - or something. You can disable by adding this to your .bashrc in bash: -``` - export GLADE_USE_OPENGL=no -``` - or in .cshrc/.tcshrc in csh/tcsh: -``` - setenv GLADE_USE_OPENGAL no -``` - To use this with the FreePDK45 or SCMOS layer views you should use the - tech files. Then create a .glade.py file in your user directory with - these commands to load the technology layers: -``` -ui().importCds("default", -"/Users/mrg/techfiles/freepdk45/display.drf", -"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1, -"/Users/mrg/techfiles/freepdk45/layers.map") -``` - Obviously, edit the paths to point to your directory. To switch - between processes, you have to change the importCds command (or you - can manually run the command each time you start glade). - - To load the errors, you simply do Verify->Import Calibre Errors select - the .results file from Calibre. - -3. Magic - - Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules - and Magic from: http://opencircuitdesign.com/ - - When running DRC or extraction, OpenRAM will load the GDS file, save - the .ext/.mag files, and export an extracted netlist (.spice). - -4. It is possible to use other viewers as well, such as: - * LayoutEditor http://www.layouteditor.net/ +- [Matthew Guthaus][Matthew Guthaus] created the OpenRAM project and is the lead architect. -# Example to output/input .gds layout files from/to Cadence - -1. To create your component layouts, you should stream them to - individual gds files using our provided layermap and flatten - cells. For example, -``` - strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds -``` -2. To stream a layout back into Cadence, do this: -``` - strmin -layerMap layers.map -attachTechFileOfLib NCSU_TechLib_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds -``` - When you import a gds file, make sure to attach the correct tech lib - or you will get incorrect layers in the resulting library. +* * * +[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg +[Github releases]: https://github.com/PrivateRAM/PrivateRAM/releases +[Github issues]: https://github.com/PrivateRAM/PrivateRAM/issues +[Github pull requests]: https://github.com/PrivateRAM/PrivateRAM/pulls +[Github projects]: https://github.com/PrivateRAM/PrivateRAM/projects +[Github insights]: https://github.com/PrivateRAM/PrivateRAM/pulse +[email me]: mailto:mrg+openram@ucsc.edu +[VLSIDA]: https://vlsida.soe.ucsc.edu +[OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/ +[Magic]: http://opencircuitdesign.com/magic/ +[Netgen]: http://opencircuitdesign.com/netgen/ +[Qflow]: http://opencircuitdesign.com/qflow/history.html +[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents +[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf diff --git a/images/license-badge.svg b/images/license-badge.svg new file mode 100644 index 00000000..bc36cde7 --- /dev/null +++ b/images/license-badge.svg @@ -0,0 +1 @@ + LicenseLicenseBSD 3-ClauseBSD 3-Clause \ No newline at end of file From f3a1acb617beeb4674b74b7cce5da3c1f250df35 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 11:08:36 -0800 Subject: [PATCH 2/9] Rename badge file --- images/{license-badge.svg => license_badge.svg} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename images/{license-badge.svg => license_badge.svg} (100%) diff --git a/images/license-badge.svg b/images/license_badge.svg similarity index 100% rename from images/license-badge.svg rename to images/license_badge.svg From 890d93d77633c4bd7a5a10267422f83162dc9f7d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 11:20:40 -0800 Subject: [PATCH 3/9] Update image paths. Add download badge. --- README.md | 42 +++++++++++++++++++++++------------------- images/download.svg | 2 ++ 2 files changed, 25 insertions(+), 19 deletions(-) create mode 100644 images/download.svg diff --git a/README.md b/README.md index 7824b9d2..7a8db7bd 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # OpenRAM [![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg)](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/commits/dev) -[![License: BSD 3-clause](./image/license_badge.svg)](./LICENSE) +[![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) +[![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) An open-source static random access memory (SRAM) compiler. @@ -10,16 +11,14 @@ An open-source static random access memory (SRAM) compiler. # Basic Setup The OpenRAM compiler has very few dependencies: -+ ngspice-26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) ++ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) + Python 3.5 and higher + Python numpy (pip3 install numpy to install) + flask_table (pip3 install flask to install) -+ a setup script for each technology you want to use -+ a technology directory for each technology with the base cells (comes with [SCMOS][SCMOS] and [FreePDK45][FreePDK45]) If you want to perform DRC and LVS, you will need either: -+ Calibre (for [FreePDK45][FreePDK45] or [SCMOS][SCMOS]) -+ Magic + Netgen (for [SCMOS][SCMOS] only) ++ Calibre (for [FreePDK45] or [SCMOS]) ++ Magic + Netgen (for [SCMOS] only) You must set two environment variables: OPENRAM\_HOME should point to the compiler source directory. OPENERAM\_TECH should point to a root @@ -35,10 +34,10 @@ For example, in csh/tcsh, add to your .cshrc/.tcshrc: setenv OPENRAM_TECH "$HOME/openram/technology" ``` -We include the tech files necessary for FreePDK and [SCMOS][SCMOS]. The [SCMOS][SCMOS] +We include the tech files necessary for [FreePDK45] and [SCMOS]. The [SCMOS] spice models, however, are generic and should be replaced with foundry models. -If you are using FreePDK, you should also have that set up and have the +If you are using [FreePDK45], you should also have that set up and have the environment variable point to the PDK. For example, in bash, add to your .bashrc: ``` @@ -48,10 +47,10 @@ For example, in csh/tcsh, add to your .tcshrc: ``` setenv FREEPDK45 "/bsoe/software/design-kits/FreePDK45" ``` -We do not distribute the PDK, but you may download [FreePDK45][FreePDK45] +We do not distribute the PDK, but you may download [FreePDK45] -If you are using [SCMOS][SCMOS], you should install [Magic][Magic] and [Netgen][Netgen]. -We have included the SCN4M design rules from [Qflow][Qflow]. +If you are using [SCMOS], you should install [Magic] and [Netgen]. +We have included the SCN4M design rules from [Qflow]. # Directory Structure @@ -66,8 +65,8 @@ We have included the SCN4M design rules from [Qflow][Qflow]. * compiler/router - router for signals and power supplies * compiler/tests - unit tests * technology - openram technology directory (pointed to by OPENRAM_TECH) - * technology/freepdk45 - example configuration library for freepdk45 technology node - * technology/scn4m_subm - example configuration library [SCMOS][SCMOS] technology node + * technology/freepdk45 - example configuration library for [FreePDK45 technology node + * technology/scn4m_subm - example configuration library [SCMOS] technology node * technology/scn3me_subm - unsupported configuration (not enough metal layers) * technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies * docs - LaTeX manual (outdated) @@ -80,17 +79,17 @@ Regression testing performs a number of tests for all modules in OpenRAM. Use the command: ``` - python regress.py + python3 regress.py ``` To run a specific test: ``` - python {unit test}.py + python3 {unit test}.py ``` The unit tests take the same arguments as openram.py itself. To increase the verbosity of the test, add one (or more) -v options: ``` - python tests/00_code_format_check_test.py -v -t freepdk45 + python3 tests/00_code_format_check_test.py -v -t freepdk45 ``` To specify a particular technology use "-t " such as "-t freepdk45" or "-t scn4m\_subm". The default for a unit test is scn4m_subm. @@ -99,15 +98,19 @@ The default for openram.py is specified in the configuration file. # Creating Custom Technologies +If you want to support a enw technology, you will need to create: ++ a setup script for each technology you want to use ++ a technology directory for each technology with the base cells + All setup scripts should be in the setup\_scripts directory under the -$OPENRAM\_TECH directory. Please look at the following file for an -example of what is needed for OpenRAM: +$OPENRAM\_TECH directory. We provide two technology examples for [SCMOS] and [FreePDK45]. +Please look at the following file for an example of what is needed for OpenRAM: ``` $OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py ``` Each setup script should be named as: setup\_openram\_{tech name}.py. -Each specific technology (e.g., freepdk45) should be a subdirectory +Each specific technology (e.g., [FreePDK45]) should be a subdirectory (e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files: 1. gds_lib folder with all the .gds (premade) library cells. At a minimum this includes: @@ -150,3 +153,4 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). [Qflow]: http://opencircuitdesign.com/qflow/history.html [FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents [SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf +[Ngspice]: http://ngspice.sourceforge.net/ diff --git a/images/download.svg b/images/download.svg new file mode 100644 index 00000000..95d978ed --- /dev/null +++ b/images/download.svg @@ -0,0 +1,2 @@ + +download download latestlatest From 487e61457be78c15c6ccafa9ba7cfe7b5ff06fba Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 11:33:15 -0800 Subject: [PATCH 4/9] Some small updates to README.md --- README.md | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 7a8db7bd..6e51f43d 100644 --- a/README.md +++ b/README.md @@ -18,7 +18,7 @@ The OpenRAM compiler has very few dependencies: If you want to perform DRC and LVS, you will need either: + Calibre (for [FreePDK45] or [SCMOS]) -+ Magic + Netgen (for [SCMOS] only) ++ [Magic] + [Netgen] (for [SCMOS] only) You must set two environment variables: OPENRAM\_HOME should point to the compiler source directory. OPENERAM\_TECH should point to a root @@ -128,6 +128,14 @@ Each specific technology (e.g., [FreePDK45]) should be a subdirectory * Layer information * etc. +# Get Involved + ++ Report bugs by submitting a [Github issue]. ++ Develop new features (see [how to contribute](./CONTRIBUTING.md)) ++ Submit code/fixes using a [Github pull request] ++ Follow our [project][Github projects]. ++ Read and cite our [ICCAD paper][OpenRAMpaper] + # License OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). @@ -140,11 +148,9 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). * * * [Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg -[Github releases]: https://github.com/PrivateRAM/PrivateRAM/releases [Github issues]: https://github.com/PrivateRAM/PrivateRAM/issues -[Github pull requests]: https://github.com/PrivateRAM/PrivateRAM/pulls +[Github pull request]: https://github.com/PrivateRAM/PrivateRAM/pulls [Github projects]: https://github.com/PrivateRAM/PrivateRAM/projects -[Github insights]: https://github.com/PrivateRAM/PrivateRAM/pulse [email me]: mailto:mrg+openram@ucsc.edu [VLSIDA]: https://vlsida.soe.ucsc.edu [OSUPDK]: https://vlsiarch.ecen.okstate.edu/flow/ @@ -154,3 +160,4 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). [FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents [SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf [Ngspice]: http://ngspice.sourceforge.net/ +[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/ From cccd815817e138d99c1fc07a8a9567cae0045b1a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 12:14:35 -0800 Subject: [PATCH 5/9] Add read-only guest token for pipeline badge access --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 6e51f43d..8da9b67f 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # OpenRAM -[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg)](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/commits/dev) +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/commits/dev) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) From 7819844269f8f0fe67e2edcddf2548dadcffe27f Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 12:42:13 -0800 Subject: [PATCH 6/9] Remove broken artifact link --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 8da9b67f..4f4f87b7 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # OpenRAM -[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/commits/dev) +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) From d3803d8c8191a5cdee581169d89be183f8fa25f7 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 12:46:19 -0800 Subject: [PATCH 7/9] Convert link to relative commits --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4f4f87b7..4f5b2e4e 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # OpenRAM -[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev) +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](./commits) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) From 89e5ce8a95de8eb050fe6703516a1b528c079222 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 12:47:47 -0800 Subject: [PATCH 8/9] Convert link to relative commits --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4f5b2e4e..427cb539 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # OpenRAM -[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](./commits) +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](commits) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) From a74baccef27f10b2344ae823f10f3d8278e0fa28 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 15 Nov 2018 12:49:10 -0800 Subject: [PATCH 9/9] Convert link to relative commits --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 427cb539..1a193703 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # OpenRAM -[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](commits) +[![pipeline status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits) [![Download](images/download.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip) [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE)