From f6302caeac85bcaf8b332cdc007363d093d60f57 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 14:17:29 +0100 Subject: [PATCH] replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names this allows us to override the bl/br/wl names of each bitcell. Signed-off-by: Bastian Koppelmann --- compiler/modules/bitcell_base_array.py | 26 ++++++++++++++ compiler/modules/replica_bitcell_array.py | 41 ++++++++++++----------- 2 files changed, 47 insertions(+), 20 deletions(-) diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 08a52c21..45bcfe0c 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -22,6 +22,32 @@ class bitcell_base_array(design.design): self.row_size = rows self.column_offset = column_offset + def get_all_bitline_names(self): + + res = list() + bitline_names = self.cell.get_all_bitline_names() + + # We have to keep the order of self.pins, otherwise we connect + # it wrong in the spice netlist + for pin in self.pins: + for bl_name in bitline_names: + if bl_name in pin: + res.append(pin) + return res + + def get_all_wordline_names(self): + + res = list() + wordline_names = self.cell.get_all_wl_names() + + # We have to keep the order of self.pins, otherwise we connect + # it wrong in the spice netlist + for pin in self.pins: + for wl_name in wordline_names: + if wl_name in pin: + res.append(pin) + return res + def add_pins(self): row_list = self.cell.get_all_wl_names() column_list = self.cell.get_all_bitline_names() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index a8b3ec30..d5865658 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -138,11 +138,10 @@ class replica_bitcell_array(design.design): def add_pins(self): + self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names() + self.bitcell_array_bl_names = self.bitcell_array.get_all_bitline_names() - self.bitcell_array_wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")] - self.bitcell_array_bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")] - - # These are the non-indexed names + # These are the non-indexed names self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.get_all_wl_names()] self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.get_all_bitline_names()] self.dummy_row_bl_names = self.bitcell_array_bl_names @@ -316,22 +315,24 @@ class replica_bitcell_array(design.design): # Main array wl and bl/br pin_names = self.bitcell_array.get_pin_names() for pin_name in pin_names: - if pin_name.startswith("wl"): - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(0,1), - width=self.width, - height=pin.height()) - elif pin_name.startswith("bl") or pin_name.startswith("br"): - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(1,0), - width=pin.width(), - height=self.height) + for wl in self.bitcell_array_wl_names: + if wl in pin_name: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(0,1), + width=self.width, + height=pin.height()) + for bitline in self.bitcell_array_bl_names: + if bitline in pin_name: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(1,0), + width=pin.width(), + height=self.height) # Replica wordlines