From f35385f42ac6c440a618828b2459d6e73ef84e83 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 24 Apr 2019 23:51:09 -0700 Subject: [PATCH] Cleaned up names, added exclusions to narrow paths for analysis. --- compiler/{characterizer => base}/graph_util.py | 8 ++++---- compiler/base/hierarchy_design.py | 2 +- compiler/modules/control_logic.py | 6 +++++- compiler/sram_1bank.py | 8 +++++++- compiler/tests/21_hspice_delay_test.py | 5 +++-- 5 files changed, 20 insertions(+), 9 deletions(-) rename compiler/{characterizer => base}/graph_util.py (89%) diff --git a/compiler/characterizer/graph_util.py b/compiler/base/graph_util.py similarity index 89% rename from compiler/characterizer/graph_util.py rename to compiler/base/graph_util.py index c20f3c91..eb40d55b 100644 --- a/compiler/characterizer/graph_util.py +++ b/compiler/base/graph_util.py @@ -29,7 +29,7 @@ class graph(): """Helper function to remove edges, useful for removing vdd/gnd""" self.graph[node] = [] - def printAllPaths(self,s, d): + def print_all_paths(self,s, d): # Mark all the vertices as not visited visited = set() @@ -39,10 +39,10 @@ class graph(): self.path_count = 0 # Call the recursive helper function to print all paths - self.printAllPathsUtil(s, d,visited, path) + self.print_all_paths_util(s, d,visited, path) debug.info(1, "Paths found={}".format(self.path_count)) - def printAllPathsUtil(self, u, d, visited, path): + def print_all_paths_util(self, u, d, visited, path): # Mark the current node as visited and store in path visited.add(u) @@ -58,7 +58,7 @@ class graph(): #Recur for all the vertices adjacent to this vertex for i in self.graph[u]: if i not in visited: - self.printAllPathsUtil(i, d, visited, path) + self.print_all_paths_util(i, d, visited, path) # Remove current vertex from path[] and mark it as unvisited path.pop() diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index a8d0f5bf..6d9de53c 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -107,7 +107,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # graph.remove_edges('vdd') # graph.remove_edges('gnd') # debug.info(1,"{}".format(graph)) - # graph.printAllPaths('A', 'Z') + # graph.print_all_paths('A', 'Z') def init_graph_params(self): """Initializes parameters relevant to the graph creation""" diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 4f654c5f..80537f2a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -965,4 +965,8 @@ class control_logic(design.design): total_cin += self.wl_en_driver.get_cin() if self.port_type == 'rw': total_cin +=self.and2.get_cin() - return total_cin \ No newline at end of file + return total_cin + + def graph_exclude_dffs(self): + """Exclude dffs from graph as they do not represent critical path""" + self.graph_inst_exclude.add(self.ctrl_dff_inst) \ No newline at end of file diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index abe08f40..ca10d827 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -320,4 +320,10 @@ class sram_1bank(sram_base): if self.col_addr_dff: for inst in self.col_addr_dff_insts: - self.graph_inst_exclude.add(inst) + self.graph_inst_exclude.add(inst) + + def graph_exclude_ctrl_dffs(self): + """Exclude dffs for CSB, WEB, etc from graph""" + #Insts located in control logic, exclusion function called here + for inst in self.control_logic_insts: + inst.mod.graph_exclude_dffs() diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index fe9c4951..7ca8c4b5 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -40,6 +40,7 @@ class timing_sram_test(openram_test): s.s.bank.graph_exclude_precharge() s.s.graph_exclude_addr_dff() s.s.graph_exclude_data_dff() + s.s.graph_exclude_ctrl_dffs() debug.info(1,'pins={}'.format(s.s.pins)) import graph_util @@ -48,8 +49,8 @@ class timing_sram_test(openram_test): s.s.build_graph(graph,"Xsram",pins) graph.remove_edges('vdd') graph.remove_edges('gnd') - debug.info(1,"{}".format(graph)) - graph.printAllPaths('clk0', 'DOUT0[0]') + #debug.info(1,"{}".format(graph)) + graph.print_all_paths('clk0', 'DOUT0[0]') tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice)