From f2c45a230ed929e1d08b7e9fee5c020490a44fe3 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Wed, 10 Jun 2020 11:00:00 -0700
Subject: [PATCH] Add new replica column test. Add more skip tests.

---
 .../tests/14_replica_column_1rw_1r_test.py    | 46 +++++++++++++++++++
 compiler/tests/skip_tests_s8.txt              | 17 +++++++
 2 files changed, 63 insertions(+)
 create mode 100755 compiler/tests/14_replica_column_1rw_1r_test.py

diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py
new file mode 100755
index 00000000..3c1a0e1e
--- /dev/null
+++ b/compiler/tests/14_replica_column_1rw_1r_test.py
@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California 
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class replica_column_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1)
+        self.local_check(a)
+
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6)
+        self.local_check(a)
+        
+        debug.info(2, "Testing replica column for 6t_cell")
+        a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2)
+        self.local_check(a)
+        
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_s8.txt
index 9f60d65e..68a6549b 100644
--- a/compiler/tests/skip_tests_s8.txt
+++ b/compiler/tests/skip_tests_s8.txt
@@ -16,18 +16,35 @@
 06_hierarchical_predecode4x16_test.py
 07_single_level_column_mux_array_pbitcell_test.py
 08_wordline_driver_array_pbitcell_test.py
+08_wordline_driver_array_test.py
 09_sense_amp_array_test_pbitcell.py
+09_sense_amp_array_test.py
 10_write_driver_array_pbitcell_test.py
 10_write_driver_array_test.py
 10_write_driver_array_wmask_pbitcell_test.py
 10_write_driver_array_wmask_test.py
 10_write_mask_and_array_pbitcell_test.py
 10_write_mask_and_array_test.py
+12_tri_gate_array_test.py
 14_replica_pbitcell_array_test.py
+14_replica_bitcell_array_test.py
+14_replica_column_test.py
+14_replica_column_1rw_1r_test.py
 18_port_address_test.py
 18_port_data_test.py
 18_port_data_wmask_test.py
 19_bank_select_pbitcell_test.py
+19_bank_select_test.py
+19_psingle_bank_test.py
+19_bank_select_pbitcell_test.py
+19_pmulti_bank_test.py
+19_multi_bank_test.py
+19_psingle_bank_test.py
+19_single_bank_1w_1r_test.py
+19_single_bank_wmask_1rw_1r_test.py
+19_single_bank_1rw_1r_test.py
+19_single_bank_test.py
+19_single_bank_wmask_test.py
 20_psram_1bank_2mux_1rw_1w_test.py
 20_psram_1bank_2mux_1rw_1w_wmask_test.py
 20_psram_1bank_2mux_1w_1r_test.py