diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 57b3f383..545f394b 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -703,7 +703,6 @@ class bank(design.design):
         inst1 = self.bitcell_array_inst
         inst1_bl_name = [x for x in self.bitcell_array.get_bitline_names(port) if "bl" in x]
         inst1_br_name = [x for x in self.bitcell_array.get_bitline_names(port) if "br" in x]
-
         inst2_bl_name = []
         inst2_br_name = []
         for col in range(self.num_cols):
@@ -722,8 +721,7 @@ class bank(design.design):
         
 
         # Connect the replica bitlines
-        rbl_bl_names = self.bitcell_array.get_rbl_bitline_names(port)[2 * port: 2 * port + 2]
-        for (array_name, data_name) in zip(rbl_bl_names, ["rbl_bl", "rbl_br"]):
+        for (array_name, data_name) in zip(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)], ["rbl_bl", "rbl_br"]):
             self.connect_bitline(inst1, inst2, array_name, data_name)
         
     def route_port_data_out(self, port):
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index f2095530..40341639 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -111,7 +111,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
                 # We will always have self.rbl[0] rows of replica wordlines below
                 # the array.
                 # These go from the bottom up
-                replica_bit = self.rbl[0] + self.row_size + 1 + port
+                replica_bit = self.rbl[0] + self.row_size + port
             else:
                 continue
             
@@ -406,7 +406,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         # Replica bitlines
         if len(self.rbls) > 0:
             for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
-                for (bl_name, pin_name) in zip(names, self.replica_columns[self.rbls[0]].all_bitline_names):
+                pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
+                for (bl_name, pin_name) in zip(names, pin_names):
                     pin = inst.get_pin(pin_name)
                     self.add_layout_pin(text=bl_name,
                                         layer=pin.layer,
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 26a21455..e7b938e7 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -4,14 +4,14 @@
 # All rights reserved.
 #
 import debug
-import design
+from bitcell_base_array import bitcell_base_array
 from tech import cell_properties
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
 
 
-class replica_column(design.design):
+class replica_column(bitcell_base_array):
     """
     Generate a replica bitline column for the replica array.
     Rows is the total number of rows i the main array.
@@ -21,7 +21,7 @@ class replica_column(design.design):
     """
 
     def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
-        super().__init__(name)
+        super().__init__(rows=sum(rbl) + rows + 2, cols=1, column_offset=column_offset, name=name)
 
         self.rows = rows
         self.left_rbl = rbl[0]
@@ -60,19 +60,9 @@ class replica_column(design.design):
 
     def add_pins(self):
 
-        self.bitline_names = [[] for port in self.all_ports]
-        col = 0
-        for port in self.all_ports:
-            self.bitline_names[port].append("bl_{0}_{1}".format(port, col))
-            self.bitline_names[port].append("br_{0}_{1}".format(port, col))
-        self.all_bitline_names = [x for sl in self.bitline_names for x in sl]
+        self.create_all_bitline_names()
+        self.create_all_wordline_names()
         self.add_pin_list(self.all_bitline_names, "OUTPUT")
-
-        self.wordline_names = [[] for port in self.all_ports]
-        for row in range(self.total_size):
-            for port in self.all_ports:
-                self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
-        self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
         self.add_pin_list(self.all_wordline_names, "INPUT")
 
         self.add_pin("vdd", "POWER")