From f21ff38cae6babd09c0d95f3d7baf84baa513a32 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Feb 2018 10:22:38 -0800 Subject: [PATCH] Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working. --- compiler/control_logic.py | 26 +++++++++++++------- compiler/hierarchy_layout.py | 4 +++- compiler/replica_bitline.py | 46 +++++++++++++++++------------------- compiler/tests/testutils.py | 5 ++-- 4 files changed, 45 insertions(+), 36 deletions(-) diff --git a/compiler/control_logic.py b/compiler/control_logic.py index 325d92e9..7a1e3851 100644 --- a/compiler/control_logic.py +++ b/compiler/control_logic.py @@ -77,8 +77,6 @@ class control_logic(design.design): # These aren't for instantiating, but we use them to get the dimensions self.poly_contact_offset = vector(0.5*contact.poly.width,0.5*contact.poly.height) - # For different layer width vias - self.m1m2_offset_fix = vector(0,0.5*(drc["minwidth_metal2"]-drc["minwidth_metal1"])) # M1/M2 routing pitch is based on contacted pitch self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(drc["metal1_to_metal1"],drc["metal2_to_metal2"]) self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(drc["metal2_to_metal2"],drc["metal3_to_metal3"]) @@ -87,10 +85,6 @@ class control_logic(design.design): # Some cells may have pwell/nwell spacing problems too when the wells are different heights. self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"]) - # Amount to shift a 90 degree rotated via from center-line path routing to it's offset - self.m1m2_via_offset = vector(contact.m1m2.first_layer_height,-0.5*drc["minwidth_metal2"]) - self.m2m3_via_offset = vector(contact.m2m3.first_layer_height,-0.5*drc["minwidth_metal3"]) - # First RAIL Parameters: gnd, oe, oebar, cs, we, clk_buf, clk_bar self.rail_1_start_x = 0 self.num_rails_1 = 8 @@ -513,11 +507,25 @@ class control_logic(design.design): offset=clk_buf_rail_position, rotate=90) - # clk_bar - self.connect_rail_from_left_m2m3(self.clk_bar,"Z","clk_bar") + # clk_bar, routes over the clock buffer vdd rail + clk_pin = self.clk_bar.get_pin("Z") + vdd_pin = self.clk_bar.get_pin("vdd") + # move the output pin up to metal2 self.add_via_center(layers=("metal1","via1","metal2"), - offset=self.clk_bar.get_pin("Z").rc(), + offset=clk_pin.rc(), rotate=90) + # route to a position over the supply rail + in_pos = vector(clk_pin.rx(), vdd_pin.cy()) + self.add_path("metal2",[clk_pin.rc(), in_pos]) + # connect that position to the control bus + rail_pos = vector(self.rail_1_x_offsets["clk_bar"], in_pos.y) + self.add_wire(("metal3","via2","metal2"),[in_pos, rail_pos]) + self.add_via_center(layers=("metal2","via2","metal3"), + offset=in_pos, + rotate=90) + self.add_via_center(layers=("metal2","via2","metal3"), + offset=rail_pos, + rotate=90) # clk_buf to msf control flops msf_clk_pos = self.msf_inst.get_pin("clk").bc() diff --git a/compiler/hierarchy_layout.py b/compiler/hierarchy_layout.py index 60a9b24a..12edb1d9 100644 --- a/compiler/hierarchy_layout.py +++ b/compiler/hierarchy_layout.py @@ -166,9 +166,11 @@ class layout(lef.lef): debug.error("Nonrectilinear center rect!",-1) elif start.x!=end.x: offset = vector(0,0.5*minwidth_layer) + return self.add_rect(layer,start-offset,end.x-start.x,minwidth_layer) else: offset = vector(0.5*minwidth_layer,0) - return self.add_rect(layer,start-offset,end.x-start.x,minwidth_layer) + return self.add_rect(layer,start-offset,minwidth_layer,end.y-start.y) + def get_pin(self, text): diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index 7fa9544a..fb8ede4c 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -240,39 +240,37 @@ class replica_bitline(design.design): """ Route all signals connected to gnd """ # Add a rail in M1 from bottom to two along delay chain - gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix - - self.add_rect(layer="metal2", - offset=gnd_start, - width=self.m2_width, - height=self.rbl_inst.uy()+2*self.m2_pitch - gnd_start.y) - self.add_layout_pin(text="gnd", - layer="metal1", - offset=gnd_start.scale(1,0), - width=self.m1_width, - height=gnd_start.y) + gnd_start = self.rbl_inv_inst.get_pin("gnd").bc() + gnd_end = vector(gnd_start.x, self.rbl_inst.uy()+2*self.m2_pitch) + self.add_segment_center(layer="metal2", + start=gnd_start, + end=gnd_end) + self.add_layout_pin_center_segment(text="gnd", + layer="metal1", + start=gnd_start.scale(1,0), + end=gnd_start) # Connect the WL pins directly to gnd + gnd_pin = self.get_pin("gnd").rc() for row in range(self.rows): wl = "wl[{}]".format(row) pin = self.rbl_inst.get_pin(wl) - offset = vector(gnd_start.x,pin.by()) - self.add_rect(layer="metal1", - offset=offset, - width=self.rbl_offset.x-gnd_start.x, - height=self.m1_width) - self.add_via(layers=("metal1", "via1", "metal2"), - offset=offset) + start = vector(gnd_pin.x,pin.cy()) + self.add_segment_center(layer="metal1", + start=start, + end=pin.lc()) + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=start) # Add via for the delay chain - offset = self.delay_chain_offset - vector(0.5*self.m1_width,0) - self.offset_fix - self.add_via(layers=("metal1", "via1", "metal2"), - offset=offset) + offset = self.dc_inst.get_pins("gnd")[0].bc() + vector(0.5*contact.m1m2.width,0.5*contact.m1m2.height) + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=offset) # Add via for the inverter - offset = self.rbl_inv_offset - vector(0.5*self.m1_width,contact.m1m2.height) - self.offset_fix - self.add_via(layers=("metal1", "via1", "metal2"), - offset=offset) + offset = self.rbl_inv_inst.get_pin("gnd").bc() - vector(0,0.5*contact.m1m2.height) + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=offset) # Connect the bitcell gnd pins to the rail gnd_pins = self.get_pins("gnd") diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 6db5c60d..f7c61a65 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -1,8 +1,9 @@ -import unittest +import unittest,warnings import sys,os,glob sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +import debug class openram_test(unittest.TestCase): """ Base unit test that we have some shared classes in. """ @@ -18,7 +19,7 @@ class openram_test(unittest.TestCase): os.remove(f) def local_check(self, a): - + tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds"