From f62016ad9fff6157c3a8e818a8403b95cbfec7f5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 3 Mar 2020 12:40:08 +0000 Subject: [PATCH 1/4] revert dff_buf for no body contact --- compiler/modules/dff_buf.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 6f06b778..8f581606 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,8 +91,8 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(props.dff_buff.buf_ports) - #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) + #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) From 6e2a5d7a1a29118a1a3d9620118876d5538f3112 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 1 Apr 2020 04:24:43 -0700 Subject: [PATCH 2/4] set sram output cap in characterizer to be 4x dff input cap --- compiler/characterizer/lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6d6c6ce5..d429bcd5 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -45,7 +45,7 @@ class lib: """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8]) - self.load_scales = np.array([0.25, 1, 8]) + self.load_scales = np.array([0.25, 1, 4]) #self.load_scales = np.array([0.25, 1]) self.load = tech.spice["dff_in_cap"] self.loads = self.load_scales*self.load From beef9441b72dc8ac045f806bbeb4c2711310be61 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 02:55:15 -0700 Subject: [PATCH 3/4] fix pin check debug typo --- compiler/base/hierarchy_spice.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index beb79ded..7adfb4f7 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -226,7 +226,7 @@ class spice(): subckt_line = list(filter(subckt.search, self.lvs))[0] # parses line into ports and remove subckt lvs_pins = subckt_line.split(" ")[2:] - debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1) + debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.") def check_net_in_spice(self, net_name): """Checks if a net name exists in the current. Intended to be check nets in hand-made cells.""" From b59c789dec692cee9843277f188486d621d3b35b Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 5 Apr 2020 03:58:26 -0700 Subject: [PATCH 4/4] remove whitespace --- compiler/modules/dff_buf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 8f581606..e42c01c0 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -91,7 +91,7 @@ class dff_buf(design.design): def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - #self.connect_inst(props.dff_buff.buf_ports) + self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1",