From 788d7e5474e610a580c5967e03cb7d726efca95a Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 31 Oct 2023 18:07:35 -0700 Subject: [PATCH 01/61] fix VPB/VNB pins not being found --- Makefile | 2 +- technology/sky130/tech/tech.py | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index dc07a5b1..99e4ce22 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git # Use this for development #SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git -SRAM_LIB_GIT_COMMIT ?= 9fcf3a78398037583b6d6c1ebac71957343c4bd8 +SRAM_LIB_GIT_COMMIT ?= dd64256961317205343a3fd446908b42bafba388 # Open PDKs OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index 9c491013..c8c642a8 100755 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -114,15 +114,15 @@ cell_properties.bitcell_2port.vdd_dir = "H" cell_properties.bitcell_2port.gnd_layer = "m2" cell_properties.bitcell_2port.gnd_dir = "H" -cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'], - ['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'], +cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb', 'gate'], + ['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS', 'INPUT'], {'bl': 'bl', 'br': 'br', 'vdd': 'vdd', 'gnd': 'gnd', - 'gate': 'gate', 'vnb': 'vnb', - 'vpb': 'vpb'}) + 'vpb': 'vpb', + 'gate': 'gate'}) cell_properties.col_cap_1port_bitcell.boundary_layer = "mem" cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'], @@ -415,8 +415,8 @@ label_purpose = 5 # pin_read purposes special_purposes = {layer["nwell"][0]: [layer["nwell"][1], 5, 59, 16]} #layer_override = {"VNB\x00": ["pwell",122]} -layer_override = {"VNB": layer["pwellp"]} -layer_override_name = {"VNB": "pwellp"} +layer_override = {"vnb": layer["pwellp"], "VNB": layer["pwellp"]} +layer_override_name = {"vnb": "pwellp", "VNB": "pwellp"} layer_override_purpose = {122: (64, 59)} # Layer names for external PDKs layer_names = {} From decfd7ff4f0af249af84a6d7ae23e41230d7d85c Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Wed, 1 Nov 2023 02:31:22 +0000 Subject: [PATCH 02/61] Bump version: 1.2.40 -> 1.2.41 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index a39cbb3c..50e400b7 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.40 +1.2.41 From 06058e1b87cc9e45c9d856406aa04ee003c5c0ce Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 9 Jan 2023 16:02:25 -0800 Subject: [PATCH 03/61] Initial files for gf180 --- Makefile | 17 +- setpaths.sh | 1 + technology/gf180/__init__.py | 52 ++++ technology/gf180/tech/tech.py | 454 ++++++++++++++++++++++++++++++++++ 4 files changed, 523 insertions(+), 1 deletion(-) create mode 100644 technology/gf180/__init__.py create mode 100644 technology/gf180/tech/tech.py diff --git a/Makefile b/Makefile index 99e4ce22..aa165640 100644 --- a/Makefile +++ b/Makefile @@ -21,12 +21,18 @@ OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git OPEN_PDKS_GIT_COMMIT ?= 1.0.311 #OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608 SKY130_PDK ?= $(PDK_ROOT)/sky130A +GF180_PDK ?= $(PDK_ROOT)/gf180 # Skywater PDK SKY130_PDKS_DIR ?= $(PDK_ROOT)/skywater-pdk SKY130_PDKS_GIT_REPO ?= https://github.com/google/skywater-pdk.git SKY130_PDKS_GIT_COMMIT ?= f70d8ca46961ff92719d8870a18a076370b85f6c +# GF180 PDK +GF180_PDKS_DIR ?= $(PDK_ROOT)/gf180mcu-pdk +GF180_PDKS_GIT_REPO ?= https://github.com/google/gf180mcu-pdk.git +GF180_PDKS_GIT_COMMIT ?= main + # Create lists of all the files to copy/link GDS_FILES := $(sort $(wildcard $(SRAM_LIB_DIR)/cells/*/*.gds)) GDS_FILES := $(GDS_FILES) $(PDK_ROOT)/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.gds @@ -67,7 +73,16 @@ $(SKY130_PDKS_DIR): check-pdk-root @git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \ git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest -$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR) +$(GF180_PDKS_DIR): check-pdk-root + @echo "Cloning gf PDK..." + @[ -d $(PDK_ROOT)/gf180mcu-pdk ] || \ + git clone https://github.com/google/gf180mcu-pdk.git $(PDK_ROOT)/gf180mcu-pdk + @cd $(SKY130_PDKS_DIR) && \ + git checkout main && git pull && \ + git checkout -qf $(GF180_PDKS_GIT_COMMIT) && \ + git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest + +$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR) $(GF180_PDKS_DIR) @echo "Cloning open_pdks..." @[ -d $(OPEN_PDKS_DIR) ] || \ git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR) diff --git a/setpaths.sh b/setpaths.sh index efceed78..79c2ff1a 100755 --- a/setpaths.sh +++ b/setpaths.sh @@ -6,4 +6,5 @@ export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology" +export PDK_ROOT="$HOME/gf/pdk" export PYTHONPATH=$OPENRAM_HOME diff --git a/technology/gf180/__init__.py b/technology/gf180/__init__.py new file mode 100644 index 00000000..45e04451 --- /dev/null +++ b/technology/gf180/__init__.py @@ -0,0 +1,52 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +#!/usr/bin/python +""" +This type of setup script should be placed in the setup_scripts directory in the trunk +""" + +import sys +import os + +TECHNOLOGY = "gf180" + +os.environ["MGC_TMPDIR"] = "/tmp" + +########################### +# OpenRAM Paths + +# OpenPDK needed for magicrc, tech file and spice models of transistors +if 'PDK_ROOT' in os.environ: + open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180', 'libs.tech') +else: + raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.") + +# The ngspice models work with Xyce too now +spice_model_dir = os.path.join(open_pdks, "ngspice") +gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "gf180.lib.spice") +if not os.path.exists(gf180_lib_ngspice): + raise SystemError("Did not find {} under {}".format(gf180_lib_ngspice, open_pdks)) +os.environ["SPICE_MODEL_DIR"] = spice_model_dir + +open_pdks = os.path.abspath(open_pdks) +gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180A.magicrc") +if not os.path.exists(gf180_magicrc): + raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks)) +os.environ["OPENRAM_MAGICRC"] = gf180_magicrc +gf180_netgenrc = os.path.join(open_pdks, 'netgen', "setup.tcl") +if not os.path.exists(gf180_netgenrc): + raise SystemError("Did not find {} under {}".format(gf180_netgenrc, open_pdks)) +os.environ["OPENRAM_NETGENRC"] = gf180_netgenrc + +try: + DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) +except: + DRCLVS_HOME= "not-found" +os.environ["DRCLVS_HOME"] = DRCLVS_HOME + + diff --git a/technology/gf180/tech/tech.py b/technology/gf180/tech/tech.py new file mode 100644 index 00000000..9c946aee --- /dev/null +++ b/technology/gf180/tech/tech.py @@ -0,0 +1,454 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import os +import drc as d +#from drc.design_rules import design_rules +#from drc.module_type import module_type +#from drc.custom_cell_properties import cell_properties +#from drc.custom_layer_properties import layer_properties + +""" +File containing the process technology parameters for SCMOS 4m, 0.35um +""" + +################################################### +# Custom modules +################################################### + +# This uses the default classes to instantiate module from +# '$OPENRAM_HOME/compiler/modules'. +# Using tech_modules['cellname'] you can override each class by providing a custom +# implementation in '$OPENRAM_TECHDIR/modules/' +# For example: tech_modules['contact'] = 'contact_scn4m' +tech_modules = d.module_type() + +################################################### +# Custom cell properties +################################################### +cell_properties = d.cell_properties() + +################################################### +# Custom cell properties +################################################### +layer_properties = d.layer_properties() + +################################################### +# GDS file info +################################################### +GDS={} +# gds units +# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first +#is the size of a database unit in user units. The second is the size +#of a database unit in meters. For example, if your library was +#created with the default units (user unit = 1 m and 1000 database +#units per user unit), then the first number would be 0.001 and the +#second number would be 10-9. Typically, the first number is less than +#1, since you use more than 1 database unit per user unit. To +#calculate the size of a user unit in meters, divide the second number +#by the first." +GDS["unit"]=(0.001,1e-6) +# default label zoom +GDS["zoom"] = 0.5 + +################################################### +# Interconnect stacks +################################################### + +poly_stack = ("poly", "contact", "m1") +active_stack = ("active", "contact", "m1") +m1_stack = ("m1", "via1", "m2") +m2_stack = ("m2", "via2", "m3") +m3_stack = ("m3", "via3", "m4") + +layer_indices = {"poly": 0, + "active": 0, + "m1": 1, + "m2": 2, + "m3": 3, + "m4": 4} + +# The FEOL stacks get us up to m1 +feol_stacks = [poly_stack, + active_stack] + +# The BEOL stacks are m1 and up +beol_stacks = [m1_stack, + m2_stack, + m3_stack] + +layer_stacks = feol_stacks + beol_stacks + +preferred_directions = {"poly": "V", + "active": "V", + "m1": "H", + "m2": "V", + "m3": "H", + "m4": "V"} + +################################################### +# Power grid +################################################### +# Use M3/M4 +power_grid = m3_stack + +################################################### +##GDS Layer Map +################################################### + +# create the GDS layer map +layer={} +layer["pwell"] = (204, 0) +layer["nwell"] = (21, 0) +layer["dnwell"] = (12, 0) +layer["active"] = (22, 0) +layer["pimplant"] = (31, 0) +layer["nimplant"] = (32, 0) +layer["poly"] = (30, 0) +layer["contact"] = (33, 0) +layer["m1"] = (34, 0) +layer["via1"] = (35, 0) +layer["m2"] = (36, 0) +layer["via2"] = (38, 0) +layer["m3"] = (42, 0) +layer["via3"] = (40, 0) +layer["m4"] = (46, 0) +layer["via4"] = (41, 0) +layer["m5"] = (81, 0) +# Not an official layer +layer["text"] = (234, 5) +layer["mem"] = (108, 5) +layer["boundary"] = (0, 0) + +label_purpose = 10 +#use_purpose = {} + +# Layer names for external PDKs +layer_names = {} +layer_names["active"] = "active" +layer_names["pwell"] = "pwell" +layer_names["nwell"] = "nwell" +layer_names["nimplant"]= "nimplant" +layer_names["pimplant"]= "pimplant" +layer_names["poly"] = "poly" +layer_names["contact"] = "contact" +layer_names["m1"] = "metal1" +layer_names["via1"] = "via1" +layer_names["m2"] = "metal2" +layer_names["via2"] = "via2" +layer_names["m3"] = "metal3" +layer_names["via3"] = "via3" +layer_names["m4"] = "metal4" +layer_names["text"] = "text" +layer_names["mem"] = "SramCore" +layer_names["boundary"]= "boundary" + +################################################### +# DRC/LVS Rules Setup +################################################### + +# technology parameter +parameter={} +# difftap.2b +parameter["min_tx_size"] = 0.250 +parameter["beta"] = 3 + +parameter["6T_inv_nmos_size"] = 0.205 +parameter["6T_inv_pmos_size"] = 0.09 +parameter["6T_access_size"] = 0.135 + +drc = d.design_rules("gf180") + +# grid size +drc["grid"] = 0.005 + +# minwidth_tx with contact (no dog bone transistors) +# difftap.2b +drc["minwidth_tx"] = 0.360 +drc["minlength_channel"] = 0.150 + +drc["pwell_to_nwell"] = 0 +# nwell.1 Minimum width of nwell/pwell +drc.add_layer("nwell", + width=0.840, + spacing=1.270) + +# poly.1a Minimum width of poly +# poly.2 Minimum spacing of poly AND active +drc.add_layer("poly", + width=0.150, + spacing=0.210) +# poly.8 +drc["poly_extend_active"] = 0.13 +# Not a rule +drc["poly_to_contact"] = 0 +# poly.7 Minimum enclosure of active around gate +drc["active_enclose_gate"] = 0.075 +# poly.4 Minimum spacing of field poly to active +drc["poly_to_active"] = 0.075 +# poly.2 Minimum spacing of field poly +drc["poly_to_field_poly"] = 0.210 + +# difftap.1 Minimum width of active +# difftap.3 Minimum spacing of active +drc.add_layer("active", + width=0.150, + spacing=0.270) +# difftap.8 +drc.add_enclosure("nwell", + layer="active", + enclosure=0.18, + extension=0.18) + +# nsd/psd.5a +drc.add_enclosure("implant", + layer="active", + enclosure=0.125) + +# Same as active enclosure? +drc["implant_to_contact"] = 0.070 +# nsd/psd.1 nsd/psd.2 +drc.add_layer("implant", + width=0.380, + spacing=0.380, + area=0.265) + +# licon.1, licon.2 +drc.add_layer("contact", + width=0.170, + spacing=0.170) +# licon.5c (0.06 extension), (licon.7 for extension) +drc.add_enclosure("active", + layer="contact", + enclosure=0.040, + extension=0.060) +# licon.7 +drc["tap_extend_contact"] = 0.120 + +# licon.8 Minimum enclosure of poly around contact +drc.add_enclosure("poly", + layer="contact", + enclosure=0.08, + extension=0.08) +# licon.11a +drc["active_contact_to_gate"] = 0.050 +# npc.4 > licon.14 0.19 > licon.11a +drc["poly_contact_to_gate"] = 0.270 +# licon.15 +drc["npc_enclose_poly"] = 0.1 + +# li.1, li.3 +drc.add_layer("li", + width=0.170, + spacing=0.170) + +# licon.5 +drc.add_enclosure("li", + layer="contact", + enclosure=0, + extension=0.080) + +drc.add_enclosure("li", + layer="mcon", + enclosure=0, + extension=0.080) +# mcon.1, mcon.2 +drc.add_layer("mcon", + width=0.170, + spacing=0.210) + +# m1.1 Minimum width of metal1 +# m1.2 Minimum spacing of metal1 +# m1.6 Minimum area of metal1 +drc.add_layer("m1", + width=0.140, + spacing=0.140, + area=0.083) +# m1.4 Minimum enclosure of metal1 +# m1.5 Minimum enclosure around contact on two opposite sides +drc.add_enclosure("m1", + layer="mcon", + enclosure=0.030, + extension=0.060) +# via.4a Minimum enclosure around via1 +# via.5a Minimum enclosure around via1 on two opposite sides +drc.add_enclosure("m1", + layer="via1", + enclosure=0.055, + extension=0.085) + +# via.1a Minimum width of via1 +# via.2 Minimum spacing of via1 +drc.add_layer("via1", + width=0.150, + spacing=0.170) + +# m2.1 Minimum width of intermediate metal +# m2.2 Minimum spacing of intermediate metal +# m2.6 Minimum area of metal2 +drc.add_layer("m2", + width=0.140, + spacing=0.140, + area=0.0676) +# m2.4 Minimum enclosure around via1 +# m2.5 Minimum enclosure around via1 on two opposite sides +drc.add_enclosure("m2", + layer="via1", + enclosure=0.055, + extension=0.085) +# via2.4 Minimum enclosure around via2 +# via2.5 Minimum enclosure around via2 on two opposite sides +drc.add_enclosure("m2", + layer="via2", + enclosure=0.040, + extension=0.085) + +# via2.1a Minimum width of Via2 +# via2.2 Minimum spacing of Via2 +drc.add_layer("via2", + width=0.200, + spacing=0.200) + +# m3.1 Minimum width of metal3 +# m3.2 Minimum spacing of metal3 +# m3.6 Minimum area of metal3 +drc.add_layer("m3", + width=0.300, + spacing=0.300, + area=0.240) +# m3.4 Minimum enclosure around via2 +drc.add_enclosure("m3", + layer="via2", + enclosure=0.065) +# via3.4 Minimum enclosure around via3 +# via3.5 Minimum enclosure around via3 on two opposite sides +drc.add_enclosure("m3", + layer="via3", + enclosure=0.060, + extension=0.090) + +# via3.1 Minimum width of Via3 +# via3.2 Minimum spacing of Via3 +drc.add_layer("via3", + width=0.200, + spacing=0.200) + +# m4.1 Minimum width of metal4 +# m4.2 Minimum spacing of metal4 +# m4.7 Minimum area of metal4 +drc.add_layer("m4", + width=0.300, + spacing=0.300, + area=0.240) +# m4.3 Minimum enclosure around via3 +drc.add_enclosure("m4", + layer="via3", + enclosure=0.065) +# FIXME: Wrong rule m4.3 Minimum enclosure around via3 +drc.add_enclosure("m4", + layer="via4", + enclosure=0.060) + + +# via4.1 Minimum width of Via4 +# via4.2 Minimum spacing of Via4 +drc.add_layer("via4", + width=0.800, + spacing=0.800) + +# FIXME: Wrong rules +# m5.1 Minimum width of metal5 +# m5.2 Minimum spacing of metal5 +# m5.7 Minimum area of metal5 +drc.add_layer("m5", + width=1.600, + spacing=1.600, + area=4.000) +# m5.3 Minimum enclosure around via4 +drc.add_enclosure("m5", + layer="via4", + enclosure=0.310) + + + +# Metal 5-10 are ommitted + +################################################### +# Spice Simulation Parameters +################################################### + +# spice info +spice = {} +spice["nmos"] = "sky130_fd_pr__nfet_01v8" +spice["pmos"] = "sky130_fd_pr__pfet_01v8" +spice["power"]="vccd1" +spice["ground"]="vssd1" + +# whether or not the device model is actually a subckt +spice["device_prefix"] = "X" + +spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]]} + +# spice stimulus related variables +spice["feasible_period"] = 10 # estimated feasible period in ns +spice["supply_voltages"] = [1.7, 1.8, 1.9] # Supply voltage corners in [Volts] +spice["nom_supply_voltage"] = 1.8 # Nominal supply voltage in [Volts] +spice["rise_time"] = 0.005 # rise time in [Nano-seconds] +spice["fall_time"] = 0.005 # fall time in [Nano-seconds] +spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius) +spice["nom_temperature"] = 25 # Nominal temperature (celcius) + +# analytical delay parameters +spice["nom_threshold"] = 0.49 # Typical Threshold voltage in Volts +spice["wire_unit_r"] = 0.125 # Unit wire resistance in ohms/square +spice["wire_unit_c"] = 0.134 # Unit wire capacitance ff/um^2 +spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff +spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff +spice["dff_setup"] = 102.5391 # DFF setup time in ps +spice["dff_hold"] = -56 # DFF hold time in ps +spice["dff_in_cap"] = 6.89 # Input capacitance (D) [Femto-farad] +spice["dff_out_cap"] = 6.89 # Output capacitance (Q) [Femto-farad] + +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["dff_leakage"] = 1 # Leakage power of flop in nW + +spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz + +# Parameters related to sense amp enable timing and delay chain/RBL sizing +parameter["le_tau"] = 2.25 # In pico-seconds. +parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad +parameter["dff_clk_cin"] = 30.6 # relative capacitance +parameter["6tcell_wl_cin"] = 3 # relative capacitance +parameter["min_inv_para_delay"] = 2.4 # Tau delay units +parameter["sa_en_pmos_size"] = 0.72 # micro-meters +parameter["sa_en_nmos_size"] = 0.27 # micro-meters +parameter["sa_inv_pmos_size"] = 0.54 # micro-meters +parameter["sa_inv_nmos_size"] = 0.27 # micro-meters +parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance + +################################################### +# Technology Tool Preferences +################################################### + +if use_calibre: + drc_name = "calibre" + lvs_name = "calibre" + pex_name = "calibre" +elif use_klayout: + drc_name = "klayout" + lvs_name = "klayout" + pex_name = "klayout" +else: + drc_name = "magic" + lvs_name = "netgen" + pex_name = "magic" + From a18d62c4306646012bcbe95b322b4674970817c3 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 16 Jan 2023 11:14:44 -0800 Subject: [PATCH 04/61] rename gf180 to gf180mcu --- technology/{gf180 => gf180mcu}/__init__.py | 8 +- technology/gf180mcu/mag_lib/.magicrc | 69 + technology/gf180mcu/tech/.magicrc | 69 + technology/gf180mcu/tech/__init__.py | 12 + technology/gf180mcu/tech/gf180mcu.lym | 49 + technology/gf180mcu/tech/gf180mcu.lyp | 2008 +++++++++++++++++++ technology/gf180mcu/tech/gf180mcu.lyt | 233 +++ technology/{gf180 => gf180mcu}/tech/tech.py | 298 ++- 8 files changed, 2590 insertions(+), 156 deletions(-) rename technology/{gf180 => gf180mcu}/__init__.py (86%) create mode 100644 technology/gf180mcu/mag_lib/.magicrc create mode 100644 technology/gf180mcu/tech/.magicrc create mode 100644 technology/gf180mcu/tech/__init__.py create mode 100644 technology/gf180mcu/tech/gf180mcu.lym create mode 100644 technology/gf180mcu/tech/gf180mcu.lyp create mode 100644 technology/gf180mcu/tech/gf180mcu.lyt rename technology/{gf180 => gf180mcu}/tech/tech.py (68%) diff --git a/technology/gf180/__init__.py b/technology/gf180mcu/__init__.py similarity index 86% rename from technology/gf180/__init__.py rename to technology/gf180mcu/__init__.py index 45e04451..10a3899a 100644 --- a/technology/gf180/__init__.py +++ b/technology/gf180mcu/__init__.py @@ -13,7 +13,7 @@ This type of setup script should be placed in the setup_scripts directory in the import sys import os -TECHNOLOGY = "gf180" +TECHNOLOGY = "gf180mcu" os.environ["MGC_TMPDIR"] = "/tmp" @@ -22,19 +22,19 @@ os.environ["MGC_TMPDIR"] = "/tmp" # OpenPDK needed for magicrc, tech file and spice models of transistors if 'PDK_ROOT' in os.environ: - open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180', 'libs.tech') + open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuA', 'libs.tech') else: raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.") # The ngspice models work with Xyce too now spice_model_dir = os.path.join(open_pdks, "ngspice") -gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "gf180.lib.spice") +gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "sm141064.ngspice") if not os.path.exists(gf180_lib_ngspice): raise SystemError("Did not find {} under {}".format(gf180_lib_ngspice, open_pdks)) os.environ["SPICE_MODEL_DIR"] = spice_model_dir open_pdks = os.path.abspath(open_pdks) -gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180A.magicrc") +gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuA.magicrc") if not os.path.exists(gf180_magicrc): raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks)) os.environ["OPENRAM_MAGICRC"] = gf180_magicrc diff --git a/technology/gf180mcu/mag_lib/.magicrc b/technology/gf180mcu/mag_lib/.magicrc new file mode 100644 index 00000000..1fa2e18d --- /dev/null +++ b/technology/gf180mcu/mag_lib/.magicrc @@ -0,0 +1,69 @@ +### +### Source file TECHNAME.magicrc +### Process this file with the m4 processor +### +puts stdout "Sourcing design .magicrc for technology TECHNAME ..." + +# Put internal grid on 0.005 pitch. This is important to match vendor file +# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 10} { + scalegrid 1 10 +} + +# drc off +drc euclidean on +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +# Allow override of PDK path from environment variable PDK_ROOT +# "file nativename" guards against a local PDK_ROOT with "~" in the name +if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} { + set PDK_ROOT STAGING_PATH +} + +# loading technology +tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech + +# load device generator +source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl + +# load bind keys +# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys + +# set units to lambda grid +snap lambda + +# set gf180mcu standard power, ground, and substrate names +set VDD VDD +set GND VSS +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram +} else { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE} +} + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects} diff --git a/technology/gf180mcu/tech/.magicrc b/technology/gf180mcu/tech/.magicrc new file mode 100644 index 00000000..1fa2e18d --- /dev/null +++ b/technology/gf180mcu/tech/.magicrc @@ -0,0 +1,69 @@ +### +### Source file TECHNAME.magicrc +### Process this file with the m4 processor +### +puts stdout "Sourcing design .magicrc for technology TECHNAME ..." + +# Put internal grid on 0.005 pitch. This is important to match vendor file +# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 10} { + scalegrid 1 10 +} + +# drc off +drc euclidean on +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +# Allow override of PDK path from environment variable PDK_ROOT +# "file nativename" guards against a local PDK_ROOT with "~" in the name +if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} { + set PDK_ROOT STAGING_PATH +} + +# loading technology +tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech + +# load device generator +source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl + +# load bind keys +# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys + +# set units to lambda grid +snap lambda + +# set gf180mcu standard power, ground, and substrate names +set VDD VDD +set GND VSS +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram +} else { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE} +} + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects} diff --git a/technology/gf180mcu/tech/__init__.py b/technology/gf180mcu/tech/__init__.py new file mode 100644 index 00000000..c6bd5798 --- /dev/null +++ b/technology/gf180mcu/tech/__init__.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California +# All rights reserved. +# + +""" +Import tech specific modules. +""" + +from .tech import * diff --git a/technology/gf180mcu/tech/gf180mcu.lym b/technology/gf180mcu/tech/gf180mcu.lym new file mode 100644 index 00000000..c819e2ea --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lym @@ -0,0 +1,49 @@ + + + + + + pymacros + + + + true + false + + false + + + python + + + +import sys +import os + +technology_macros_path = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, technology_macros_path) + +from cells import gf180mcu + +# Instantiate and register the library +gf180mcu() + +print("## gf180mcu PDK Pcells loaded.") +print(sys.path) + + + diff --git a/technology/gf180mcu/tech/gf180mcu.lyp b/technology/gf180mcu/tech/gf180mcu.lyp new file mode 100644 index 00000000..1b996571 --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lyp @@ -0,0 +1,2008 @@ + + + + + #55ce57 + #55ce57 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + 1/222@1 + + + #661a48 + #661a48 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + pass_mk 2/222@1 + + + #7c6078 + #7c6078 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + fail_mk 3/222@1 + + + #f26f6c + #f26f6c + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + polygon_mk 4/222@1 + + + #324416 + #324416 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + 5/222@1 + + + #3acb88 + #3acb88 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + violation_mk 6/222@1 + + + #5a68c2 + #5a68c2 + 0 + 0 + I3 + + true + false + false + 1 + false + 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+ false + 0 + + GUARD_RING_MK 167/5@1 + + + #2aa0fb + #2aa0fb + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + OTP_MK 173/5@1 + + + #7b407b + #7b407b + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + MTPMARK 122/5@1 + + + #f894c4 + #f894c4 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + NEO_EE_MK 88/17@1 + + + #d69c01 + #d69c01 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + SramCore 108/5@1 + + + #c80a86 + #c80a86 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + LVS_RF 100/5@1 + + + #fa898a + #fa898a + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + LVS_Drain 100/7@1 + + + #5a305a + #5a305a + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + IND_MK 151/5@1 + + + #c2bf6d + #c2bf6d + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + HVPOLYRS 123/5@1 + + + #9f3b8a + #9f3b8a + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + LVS_IO 119/5@1 + + + #5aac8a + #5aac8a + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + PROBE_MK 13/17@1 + + + #5de533 + #5de533 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + ESD_MK 24/5@1 + + + #b654a3 + #b654a3 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + LVS_Source 100/8@1 + + + #9beaaf + #9beaaf + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + WELL_DIODE_MK 153/51@1 + + + #b0eb32 + #b0eb32 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + LDMOS_XTOR 226/0@1 + + + #2507df + #2507df + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + PLFUSE 125/5@1 + + + #7791b3 + #7791b3 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + EFUSE_MK 80/5@1 + + + #ac9801 + #ac9801 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + MCELL_FEOL_MK 11/17@1 + + + #ae438e + #ae438e + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + YMTP_MK 86/17@1 + + + #5779b7 + #5779b7 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + DEV_WF_MK 128/17@1 + + + #8e3415 + #8e3415 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal1_BLK 34/5@1 + + + #47649f + #47649f + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal2_BLK 36/5@1 + + + #3bf37a + #3bf37a + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal3_BLK 42/5@1 + + + #678619 + #678619 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal4_BLK 46/5@1 + + + #44fa82 + #44fa82 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal5_BLK 81/5@1 + + + #614b6a + #614b6a + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + MetalT_BLK 53/5@1 + + + #d9f817 + #d9f817 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + PR_bndry 0/0@1 + + + #0bdfb7 + #0bdfb7 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + MDIODE 116/5@1 + + + #658af3 + #658af3 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal1_Res 110/11@1 + + + #e9465c + #e9465c + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal2_Res 110/12@1 + + + #ba3263 + #ba3263 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal3_Res 110/13@1 + + + #ddeef3 + #ddeef3 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal4_Res 110/14@1 + + + #004676 + #004676 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal5_Res 110/15@1 + + + #e4b00d + #e4b00d + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal6_Res 110/16@1 + + + #edeb06 + #edeb06 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Border 63/0@1 + + + diff --git a/technology/gf180mcu/tech/gf180mcu.lyt b/technology/gf180mcu/tech/gf180mcu.lyt new file mode 100644 index 00000000..c5959dcd --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lyt @@ -0,0 +1,233 @@ + + + + gf180mcu + GLOBALFOUNDRIES 0.18UM 3.3V/(5V)6V MCU TECHNOLOGY + + 0.001 + + $PDK_ROOT/$PDK/libs.tech/klayout + gf180mcu.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + # Provide z stack information here +# +# Each line is one layer. The specification consists of a layer specification, a colon and arguments. +# The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks. +# Named arguments are: +# +# zstart The lower z position of the extruded layer in µm +# zstop The upper z position of the extruded layer in µm +# height The height of the extruded layer in µm +# +# 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart', +# the upper level of the previous layer will be used. +# +# If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to +# 'zstart' and 'zstop'. +# +# Examples: +# 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically +# 1/0: 0.5 1.5 # same with explicit datatype +# 1: zstop=1.5, zstart=0.5 # same with named parameters +# 1: height=1.0, zstop=1.5 # same with z stop minus height +# 1: 1.0 zstop=1.5 # same with height as unnamed parameter +# +# VARIABLES +# +# You can declare variables with: +# var name = value +# +# You can use variables inside numeric expressions. +# Example: +# var hmetal = 0.48 +# 7/0: 0.5 0.5+hmetal*2 # 2x thick metal +# +# You cannot use variables inside layer specifications currently. +# +# CONDITIONALS +# +# You can enable or disable branches of the table using 'if', 'else', 'elseif' and 'end': +# Example: +# var thick_m1 = true +# if thickm1 +# 1: 0.5 1.5 +# else +# 1: 0.5 1.2 +# end + + + + + 30/0,33/0,Metal1 + Metal1,35/0,Metal2 + Metal2,38/0,Metal3 + Metal3,40/0,Metal4 + Metal4,41/0,Metal5 + Metal5,82/0,53/0 + + Metal1='34/0+34/10' + Metal2='36/0+36/10' + Metal3='42/0+42/10' + Metal4='46/0+46/10' + Metal5='81/0+81/10' + + diff --git a/technology/gf180/tech/tech.py b/technology/gf180mcu/tech/tech.py similarity index 68% rename from technology/gf180/tech/tech.py rename to technology/gf180mcu/tech/tech.py index 9c946aee..66e9d3a0 100644 --- a/technology/gf180/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -132,6 +132,7 @@ layer_names = {} layer_names["active"] = "active" layer_names["pwell"] = "pwell" layer_names["nwell"] = "nwell" +layer_names["dnwell"] = "dnwell" layer_names["nimplant"]= "nimplant" layer_names["pimplant"]= "pimplant" layer_names["poly"] = "poly" @@ -153,225 +154,218 @@ layer_names["boundary"]= "boundary" # technology parameter parameter={} -# difftap.2b + parameter["min_tx_size"] = 0.250 parameter["beta"] = 3 -parameter["6T_inv_nmos_size"] = 0.205 -parameter["6T_inv_pmos_size"] = 0.09 -parameter["6T_access_size"] = 0.135 - +parameter["6T_inv_nmos_size"] = 0.6 +parameter["6T_inv_pmos_size"] = 0.95 +parameter["6T_access_size"] = 0.6 drc = d.design_rules("gf180") # grid size drc["grid"] = 0.005 -# minwidth_tx with contact (no dog bone transistors) -# difftap.2b -drc["minwidth_tx"] = 0.360 -drc["minlength_channel"] = 0.150 +drc["minwidth_tx"] = 0.28 +#drc["minlength_channel"] = 0.150 + +drc["pwell_to_nwell"] = 0 # assuming same potential -drc["pwell_to_nwell"] = 0 -# nwell.1 Minimum width of nwell/pwell drc.add_layer("nwell", - width=0.840, - spacing=1.270) + width=0.86, + spacing=0.6) + +drc.add_layer("pwell", + width=0.74, # 0.6 for 1.5v + spacing=0.86) # equal potential 1.7 otherwise -# poly.1a Minimum width of poly -# poly.2 Minimum spacing of poly AND active drc.add_layer("poly", - width=0.150, - spacing=0.210) + width=0.18, + spacing=0.24) # poly.8 -drc["poly_extend_active"] = 0.13 +#drc["poly_extend_active"] = 0.13 # Not a rule -drc["poly_to_contact"] = 0 +#drc["poly_to_contact"] = 0 # poly.7 Minimum enclosure of active around gate -drc["active_enclose_gate"] = 0.075 +#drc["active_enclose_gate"] = 0.075 # poly.4 Minimum spacing of field poly to active -drc["poly_to_active"] = 0.075 +#drc["poly_to_active"] = 0.075 # poly.2 Minimum spacing of field poly -drc["poly_to_field_poly"] = 0.210 +#drc["poly_to_field_poly"] = 0.210 -# difftap.1 Minimum width of active -# difftap.3 Minimum spacing of active drc.add_layer("active", - width=0.150, - spacing=0.270) -# difftap.8 + width=0.22, + spacing=0.280) + +drc.add_enclosure("dnwell", + layer="pwell", + enclosure=2.5, + extension=2.5) + drc.add_enclosure("nwell", layer="active", - enclosure=0.18, - extension=0.18) + enclosure=0.43, + extension=0.6) -# nsd/psd.5a -drc.add_enclosure("implant", +drc.add_enclosure("pwell", layer="active", - enclosure=0.125) + enclosure=0.43, + extension=0.6) +# nsd/psd.5a +#drc.add_enclosure("implant", +# layer="active", +# enclosure=0.125) # Same as active enclosure? -drc["implant_to_contact"] = 0.070 +#drc["implant_to_contact"] = 0.070 # nsd/psd.1 nsd/psd.2 -drc.add_layer("implant", - width=0.380, - spacing=0.380, - area=0.265) +#drc.add_layer("implant", +# width=0.380, +# spacing=0.380, +# area=0.265) # licon.1, licon.2 -drc.add_layer("contact", - width=0.170, - spacing=0.170) +#drc.add_layer("contact", +# width=0.170, +# spacing=0.170) # licon.5c (0.06 extension), (licon.7 for extension) -drc.add_enclosure("active", - layer="contact", - enclosure=0.040, - extension=0.060) +#drc.add_enclosure("active", +# layer="contact", +# enclosure=0.040, +# extension=0.060) # licon.7 -drc["tap_extend_contact"] = 0.120 +#drc["tap_extend_contact"] = 0.120 # licon.8 Minimum enclosure of poly around contact -drc.add_enclosure("poly", - layer="contact", - enclosure=0.08, - extension=0.08) +#drc.add_enclosure("poly", +# layer="contact", +# enclosure=0.08, +# extension=0.08) # licon.11a -drc["active_contact_to_gate"] = 0.050 +#drc["active_contact_to_gate"] = 0.050 # npc.4 > licon.14 0.19 > licon.11a -drc["poly_contact_to_gate"] = 0.270 +#drc["poly_contact_to_gate"] = 0.270 # licon.15 -drc["npc_enclose_poly"] = 0.1 +#drc["npc_enclose_poly"] = 0.1 # li.1, li.3 -drc.add_layer("li", - width=0.170, - spacing=0.170) +#drc.add_layer("li", +# width=0.170, +# spacing=0.170) # licon.5 -drc.add_enclosure("li", - layer="contact", - enclosure=0, - extension=0.080) +#drc.add_enclosure("li", +# layer="contact", +# enclosure=0, +# extension=0.080) -drc.add_enclosure("li", - layer="mcon", - enclosure=0, - extension=0.080) +#drc.add_enclosure("li", +# layer="mcon", +# enclosure=0, +# extension=0.080) # mcon.1, mcon.2 -drc.add_layer("mcon", - width=0.170, - spacing=0.210) +#drc.add_layer("mcon", +# width=0.170, +# spacing=0.210) -# m1.1 Minimum width of metal1 -# m1.2 Minimum spacing of metal1 -# m1.6 Minimum area of metal1 drc.add_layer("m1", - width=0.140, - spacing=0.140, - area=0.083) + width=0.23, + spacing=0.23, + area=0.1444) # m1.4 Minimum enclosure of metal1 # m1.5 Minimum enclosure around contact on two opposite sides -drc.add_enclosure("m1", - layer="mcon", - enclosure=0.030, - extension=0.060) +#drc.add_enclosure("m1", +# layer="mcon", +# enclosure=0.030, +# extension=0.060) # via.4a Minimum enclosure around via1 # via.5a Minimum enclosure around via1 on two opposite sides -drc.add_enclosure("m1", - layer="via1", - enclosure=0.055, - extension=0.085) +#drc.add_enclosure("m1", +# layer="via1", +# enclosure=0.055, +# extension=0.085) # via.1a Minimum width of via1 # via.2 Minimum spacing of via1 -drc.add_layer("via1", - width=0.150, - spacing=0.170) +#drc.add_layer("via1", +# width=0.150, +# spacing=0.170) -# m2.1 Minimum width of intermediate metal -# m2.2 Minimum spacing of intermediate metal -# m2.6 Minimum area of metal2 drc.add_layer("m2", - width=0.140, - spacing=0.140, - area=0.0676) + width=0.28, + spacing=0.28, + area=0.1444) # m2.4 Minimum enclosure around via1 # m2.5 Minimum enclosure around via1 on two opposite sides -drc.add_enclosure("m2", - layer="via1", - enclosure=0.055, - extension=0.085) +#drc.add_enclosure("m2", +# layer="via1", +# enclosure=0.055, +# extension=0.085) # via2.4 Minimum enclosure around via2 # via2.5 Minimum enclosure around via2 on two opposite sides -drc.add_enclosure("m2", - layer="via2", - enclosure=0.040, - extension=0.085) +#drc.add_enclosure("m2", +# layer="via2", +# enclosure=0.040, +# extension=0.085) # via2.1a Minimum width of Via2 # via2.2 Minimum spacing of Via2 -drc.add_layer("via2", - width=0.200, - spacing=0.200) +#drc.add_layer("via2", +# width=0.200, +# spacing=0.200) -# m3.1 Minimum width of metal3 -# m3.2 Minimum spacing of metal3 -# m3.6 Minimum area of metal3 drc.add_layer("m3", - width=0.300, - spacing=0.300, - area=0.240) + width=0.28, + spacing=0.28, + area=0.1444) # m3.4 Minimum enclosure around via2 -drc.add_enclosure("m3", - layer="via2", - enclosure=0.065) +#drc.add_enclosure("m3", +# layer="via2", +# enclosure=0.065) # via3.4 Minimum enclosure around via3 # via3.5 Minimum enclosure around via3 on two opposite sides -drc.add_enclosure("m3", - layer="via3", - enclosure=0.060, - extension=0.090) +#drc.add_enclosure("m3", +# layer="via3", +# enclosure=0.060, +# extension=0.090) # via3.1 Minimum width of Via3 # via3.2 Minimum spacing of Via3 -drc.add_layer("via3", - width=0.200, - spacing=0.200) +#drc.add_layer("via3", +# width=0.200, +# spacing=0.200) -# m4.1 Minimum width of metal4 -# m4.2 Minimum spacing of metal4 -# m4.7 Minimum area of metal4 drc.add_layer("m4", - width=0.300, - spacing=0.300, - area=0.240) + width=0.28, + spacing=0.28, + area=0.1444) # m4.3 Minimum enclosure around via3 -drc.add_enclosure("m4", - layer="via3", - enclosure=0.065) -# FIXME: Wrong rule m4.3 Minimum enclosure around via3 -drc.add_enclosure("m4", - layer="via4", - enclosure=0.060) +#drc.add_enclosure("m4", +# layer="via3", +# enclosure=0.065) + +#drc.add_enclosure("m4", +# layer="via4", +# enclosure=0.060) # via4.1 Minimum width of Via4 # via4.2 Minimum spacing of Via4 -drc.add_layer("via4", - width=0.800, - spacing=0.800) +#drc.add_layer("via4", +# width=0.800, +# spacing=0.800) -# FIXME: Wrong rules # m5.1 Minimum width of metal5 # m5.2 Minimum spacing of metal5 # m5.7 Minimum area of metal5 -drc.add_layer("m5", - width=1.600, - spacing=1.600, - area=4.000) +#drc.add_layer("m5", +# width=1.600, +# spacing=1.600, +# area=4.000) # m5.3 Minimum enclosure around via4 -drc.add_enclosure("m5", - layer="via4", - enclosure=0.310) +#drc.add_enclosure("m5", +# layer="via4", +# enclosure=0.310) @@ -439,16 +433,16 @@ parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of d # Technology Tool Preferences ################################################### -if use_calibre: - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" -elif use_klayout: - drc_name = "klayout" - lvs_name = "klayout" - pex_name = "klayout" -else: - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" +#if use_calibre: +# drc_name = "calibre" +# lvs_name = "calibre" +# pex_name = "calibre" +#if use_klayout: +# drc_name = "klayout" +# lvs_name = "klayout" +# pex_name = "klayout" +#else: +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" From d18a4f8c7c3649d191de2c14723373250c5deecd Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 16 Jan 2023 20:27:28 -0800 Subject: [PATCH 05/61] additional tech commits --- technology/gf180mcu/tech/tech.py | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 66e9d3a0..4485ac63 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -182,14 +182,14 @@ drc.add_layer("pwell", drc.add_layer("poly", width=0.18, spacing=0.24) -# poly.8 -#drc["poly_extend_active"] = 0.13 -# Not a rule -#drc["poly_to_contact"] = 0 + +drc["poly_extend_active"] = 0.22 + +drc["poly_to_contact"] = 0 # poly.7 Minimum enclosure of active around gate #drc["active_enclose_gate"] = 0.075 -# poly.4 Minimum spacing of field poly to active -#drc["poly_to_active"] = 0.075 + +drc["poly_to_active"] = 0.1 # poly.2 Minimum spacing of field poly #drc["poly_to_field_poly"] = 0.210 @@ -224,10 +224,9 @@ drc.add_enclosure("pwell", # spacing=0.380, # area=0.265) -# licon.1, licon.2 -#drc.add_layer("contact", -# width=0.170, -# spacing=0.170) +drc.add_layer("contact", + width=0.22, + spacing=0.25) # licon.5c (0.06 extension), (licon.7 for extension) #drc.add_enclosure("active", # layer="contact", From a9048749782e68c87fd899e1929dbca29741d037 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 20 Jan 2023 14:34:27 -0800 Subject: [PATCH 06/61] passing gf180 parameterized gate tests --- docker/Dockerfile | 6 +- technology/gf180mcu/tech/tech.py | 192 +++++++++++++------------------ 2 files changed, 80 insertions(+), 118 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index fc165e19..62e0a6d5 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -130,14 +130,14 @@ RUN apt-get install --no-install-recommends -y iverilog ### Magic ### #ARG MAGIC_COMMIT=db4fa65bfc096e63954b37b188ea27b90ab31839 #ARG MAGIC_COMMIT=8.3.274 -ARG MAGIC_COMMIT=8.3.311 +ARG MAGIC_COMMIT=8.3.363 WORKDIR /root #RUN git clone https://github.com/RTimothyEdwards/magic.git magic RUN git clone git://opencircuitdesign.com/magic magic WORKDIR /root/magic RUN git checkout ${MAGIC_COMMIT} -COPY mrg.patch /root/magic -RUN git apply mrg.patch +#COPY mrg.patch /root/magic +#RUN git apply mrg.patch RUN ./configure RUN make RUN make install diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 4485ac63..3345bf53 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -31,9 +31,10 @@ tech_modules = d.module_type() # Custom cell properties ################################################### cell_properties = d.cell_properties() +cell_properties.ptx.model_is_subckt = True ################################################### -# Custom cell properties +# Custom layer properties ################################################### layer_properties = d.layer_properties() @@ -186,11 +187,11 @@ drc.add_layer("poly", drc["poly_extend_active"] = 0.22 drc["poly_to_contact"] = 0 -# poly.7 Minimum enclosure of active around gate + #drc["active_enclose_gate"] = 0.075 drc["poly_to_active"] = 0.1 -# poly.2 Minimum spacing of field poly + #drc["poly_to_field_poly"] = 0.210 drc.add_layer("active", @@ -211,148 +212,112 @@ drc.add_enclosure("pwell", layer="active", enclosure=0.43, extension=0.6) -# nsd/psd.5a -#drc.add_enclosure("implant", -# layer="active", -# enclosure=0.125) + +drc.add_enclosure("implant", + layer="active", + enclosure=0.125) # Same as active enclosure? #drc["implant_to_contact"] = 0.070 -# nsd/psd.1 nsd/psd.2 -#drc.add_layer("implant", -# width=0.380, -# spacing=0.380, -# area=0.265) + +drc.add_layer("implant", + width=0.4, + spacing=0.4, + area=0.35) drc.add_layer("contact", width=0.22, spacing=0.25) -# licon.5c (0.06 extension), (licon.7 for extension) -#drc.add_enclosure("active", -# layer="contact", -# enclosure=0.040, -# extension=0.060) -# licon.7 -#drc["tap_extend_contact"] = 0.120 -# licon.8 Minimum enclosure of poly around contact -#drc.add_enclosure("poly", -# layer="contact", -# enclosure=0.08, -# extension=0.08) -# licon.11a -#drc["active_contact_to_gate"] = 0.050 -# npc.4 > licon.14 0.19 > licon.11a -#drc["poly_contact_to_gate"] = 0.270 -# licon.15 +drc.add_enclosure("active", + layer="contact", + enclosure=0.01, + extension=0.01) +drc.add_enclosure("poly", + layer="contact", + enclosure=0.07, + extension=0.07) + +drc["active_contact_to_gate"] = 0.145 + +drc["poly_contact_to_gate"] = 0.165 + #drc["npc_enclose_poly"] = 0.1 -# li.1, li.3 -#drc.add_layer("li", -# width=0.170, -# spacing=0.170) - -# licon.5 -#drc.add_enclosure("li", -# layer="contact", -# enclosure=0, -# extension=0.080) - -#drc.add_enclosure("li", -# layer="mcon", -# enclosure=0, -# extension=0.080) -# mcon.1, mcon.2 -#drc.add_layer("mcon", -# width=0.170, -# spacing=0.210) - drc.add_layer("m1", width=0.23, spacing=0.23, area=0.1444) -# m1.4 Minimum enclosure of metal1 -# m1.5 Minimum enclosure around contact on two opposite sides -#drc.add_enclosure("m1", -# layer="mcon", -# enclosure=0.030, -# extension=0.060) -# via.4a Minimum enclosure around via1 -# via.5a Minimum enclosure around via1 on two opposite sides -#drc.add_enclosure("m1", -# layer="via1", -# enclosure=0.055, -# extension=0.085) -# via.1a Minimum width of via1 -# via.2 Minimum spacing of via1 -#drc.add_layer("via1", -# width=0.150, -# spacing=0.170) +drc.add_enclosure("m1", + layer="contact", + enclosure=0.06, + extension=0.06) + +drc.add_enclosure("m1", + layer="via1", + enclosure=0.06, + extension=0.06) + +drc.add_layer("via1", + width=0.26, + spacing=0.26) drc.add_layer("m2", width=0.28, spacing=0.28, area=0.1444) -# m2.4 Minimum enclosure around via1 -# m2.5 Minimum enclosure around via1 on two opposite sides -#drc.add_enclosure("m2", -# layer="via1", -# enclosure=0.055, -# extension=0.085) -# via2.4 Minimum enclosure around via2 -# via2.5 Minimum enclosure around via2 on two opposite sides -#drc.add_enclosure("m2", -# layer="via2", -# enclosure=0.040, -# extension=0.085) -# via2.1a Minimum width of Via2 -# via2.2 Minimum spacing of Via2 -#drc.add_layer("via2", -# width=0.200, -# spacing=0.200) +drc.add_enclosure("m2", + layer="via1", + enclosure=0.06, + extension=0.06) + +drc.add_enclosure("m2", + layer="via2", + enclosure=0.06, + extension=0.06) + +drc.add_layer("via2", + width=0.26, + spacing=0.26) drc.add_layer("m3", width=0.28, spacing=0.28, area=0.1444) -# m3.4 Minimum enclosure around via2 -#drc.add_enclosure("m3", -# layer="via2", -# enclosure=0.065) -# via3.4 Minimum enclosure around via3 -# via3.5 Minimum enclosure around via3 on two opposite sides -#drc.add_enclosure("m3", -# layer="via3", -# enclosure=0.060, -# extension=0.090) -# via3.1 Minimum width of Via3 -# via3.2 Minimum spacing of Via3 -#drc.add_layer("via3", -# width=0.200, -# spacing=0.200) +drc.add_enclosure("m3", + layer="via2", + enclosure=0.06) + + +drc.add_enclosure("m3", + layer="via3", + enclosure=0.06, + extension=0.06) + +drc.add_layer("via3", + width=0.26, + spacing=0.26) drc.add_layer("m4", width=0.28, spacing=0.28, area=0.1444) -# m4.3 Minimum enclosure around via3 -#drc.add_enclosure("m4", -# layer="via3", -# enclosure=0.065) -#drc.add_enclosure("m4", -# layer="via4", -# enclosure=0.060) +drc.add_enclosure("m4", + layer="via3", + enclosure=0.06) + +drc.add_enclosure("m4", + layer="via4", + enclosure=0.06) -# via4.1 Minimum width of Via4 -# via4.2 Minimum spacing of Via4 -#drc.add_layer("via4", -# width=0.800, -# spacing=0.800) +drc.add_layer("via5", + width=0.26, + spacing=0.26) # m5.1 Minimum width of metal5 # m5.2 Minimum spacing of metal5 @@ -376,14 +341,11 @@ drc.add_layer("m4", # spice info spice = {} -spice["nmos"] = "sky130_fd_pr__nfet_01v8" -spice["pmos"] = "sky130_fd_pr__pfet_01v8" +spice["nmos"] = "nfet_03v3" +spice["pmos"] = "pfet_03v3" spice["power"]="vccd1" spice["ground"]="vssd1" -# whether or not the device model is actually a subckt -spice["device_prefix"] = "X" - spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]]} # spice stimulus related variables From 8a5b0b4898c0b91e505ba823636b10c640a3b420 Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Sun, 26 Feb 2023 12:36:19 -0800 Subject: [PATCH 07/61] updated the open_pdks commit and added the gf180 pdk build target --- Makefile | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index aa165640..283016d2 100644 --- a/Makefile +++ b/Makefile @@ -18,7 +18,8 @@ SRAM_LIB_GIT_COMMIT ?= dd64256961317205343a3fd446908b42bafba388 # Open PDKs OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git -OPEN_PDKS_GIT_COMMIT ?= 1.0.311 +# OPEN_PDKS_GIT_COMMIT ?= 1.0.311 +OPEN_PDKS_GIT_COMMIT ?= 1.0.395 #OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608 SKY130_PDK ?= $(PDK_ROOT)/sky130A GF180_PDK ?= $(PDK_ROOT)/gf180 @@ -77,10 +78,11 @@ $(GF180_PDKS_DIR): check-pdk-root @echo "Cloning gf PDK..." @[ -d $(PDK_ROOT)/gf180mcu-pdk ] || \ git clone https://github.com/google/gf180mcu-pdk.git $(PDK_ROOT)/gf180mcu-pdk - @cd $(SKY130_PDKS_DIR) && \ + @cd $(GF180_PDKS_DIR) && \ git checkout main && git pull && \ git checkout -qf $(GF180_PDKS_GIT_COMMIT) && \ - git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest + git submodule update --init libraries/gf180mcu_fd_pr/latest libraries/gf180mcu_fd_sc_mcu7t5v0/latest libraries/gf180mcu_fd_sc_mcu9t5v0/latest + $(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR) $(GF180_PDKS_DIR) @echo "Cloning open_pdks..." @@ -108,6 +110,15 @@ else conda deactivate endif +$(GF180_PDK): $(OPEN_PDKS_DIR) $(GF180_PDKS_DIR) + @echo "Installing open_pdks..." + $(DOCKER_CMD) sh -c ". /home/cad-user/.bashrc && cd /pdk/open_pdks && \ + ./configure --enable-gf180mcu-pdk=/pdk/gf180mcu-pdk/libraries && \ + cd gf180mcu && \ + make veryclean && \ + make && \ + make SHARED_PDKS_PATH=/pdk install" + $(SRAM_LIB_DIR): check-pdk-root @echo "Cloning SRAM library..." @[ -d $(SRAM_LIB_DIR) ] || \ @@ -127,7 +138,7 @@ install: $(SRAM_LIB_DIR) @make $(INSTALL_DIRS) .PHONY: install -pdk: $(SKY130_PDK) +pdk: $(SKY130_PDK) $(GF180_PDK) @true .PHONY: pdk From 81b62ab13bbbb00e62336d4968c382220d84f1eb Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Mon, 13 Mar 2023 13:40:19 -0700 Subject: [PATCH 08/61] added gf180mcu as the test tech target --- compiler/tests/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index cdef60ca..5801a850 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -4,7 +4,8 @@ include $(TOP_DIR)/openram.mk .DEFAULT_GOAL := all ARGS ?= -TECHS ?= scn4m_subm freepdk45 sky130 +TEST_TECHS ?= scn4m_subm freepdk45 +TECHS ?= scn4m_subm freepdk45 sky130 gf180mcu TEST_DIR = $(TOP_DIR)/compiler/tests TEST_SRCS = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py))) From de7a248ff07dd1a5b578f44d17b4f575a5cb738a Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Sun, 22 Jan 2023 18:19:47 -0800 Subject: [PATCH 09/61] added the cell property definitions --- technology/gf180mcu/tech/tech.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 3345bf53..8d586f87 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -27,10 +27,28 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = d.module_type() +tech_modules["bitcell_1port"] = "gf180_bitcell" + ################################################### # Custom cell properties ################################################### cell_properties = d.cell_properties() + +cell_properties.bitcell_1port.port_order = ['BL', 'BR','GND', 'VDD', 'nwell', 'pwell', 'WL'] +cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"] +cell_properties.bitcell_1port.port_map = {'BL': 'BL', + 'BR': 'BR', + 'WL': 'WL', + 'VDD': 'VPWR', + 'pwell': 'VNB', + 'nwell': 'VPB', + 'GND': 'VGND'} + +cell_properties.bitcell_1port.wl_layer = "m3" +cell_properties.bitcell_1port.bl_layer = "m2" +cell_properties.bitcell_1port.vdd_layer = "m1" +cell_properties.bitcell_1port.gnd_layer = "m1" + cell_properties.ptx.model_is_subckt = True ################################################### From b9fd172e446ab9dd099a5dced94c8900346eff29 Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Mon, 23 Jan 2023 17:57:11 -0800 Subject: [PATCH 10/61] corrected the pin mapping --- technology/gf180mcu/tech/tech.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 8d586f87..fc1a73be 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -39,10 +39,10 @@ cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER cell_properties.bitcell_1port.port_map = {'BL': 'BL', 'BR': 'BR', 'WL': 'WL', - 'VDD': 'VPWR', - 'pwell': 'VNB', - 'nwell': 'VPB', - 'GND': 'VGND'} + 'VDD': 'VDD', + 'pwell': 'pwell', + 'nwell': 'nwell', + 'GND': 'GND'} cell_properties.bitcell_1port.wl_layer = "m3" cell_properties.bitcell_1port.bl_layer = "m2" From 7ce11eba52e9691f72598e7d91f7066f1e456258 Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Mon, 13 Mar 2023 12:52:54 -0700 Subject: [PATCH 11/61] added pwell as a non-routing layer --- compiler/base/hierarchy_layout.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index f9d3e889..7137566f 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -187,7 +187,7 @@ class layout(): pass # Skip computing the pitch for non-routing layers - if layer_id in ["active", "nwell"]: + if layer_id in ["active", "nwell", "pwell"]: continue # Add the pitch From 698020301c68d8440e9b7495a4cd7059b06c77a2 Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Mon, 13 Mar 2023 13:44:30 -0700 Subject: [PATCH 12/61] updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer --- technology/gf180mcu/tech/tech.py | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index fc1a73be..cce0f828 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -7,13 +7,9 @@ # import os import drc as d -#from drc.design_rules import design_rules -#from drc.module_type import module_type -#from drc.custom_cell_properties import cell_properties -#from drc.custom_layer_properties import layer_properties """ -File containing the process technology parameters for SCMOS 4m, 0.35um +File containing the process technology parameters for Global Foundaries 180nm """ ################################################### @@ -34,15 +30,18 @@ tech_modules["bitcell_1port"] = "gf180_bitcell" ################################################### cell_properties = d.cell_properties() -cell_properties.bitcell_1port.port_order = ['BL', 'BR','GND', 'VDD', 'nwell', 'pwell', 'WL'] +# is there a better way to tell if the user overrode the port order than this? +# this is needed to correctly create the bitcell_pins list in the bitcell_base_array +cell_properties.override_bitcell_1port_order = True +cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl'] cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"] -cell_properties.bitcell_1port.port_map = {'BL': 'BL', - 'BR': 'BR', - 'WL': 'WL', - 'VDD': 'VDD', - 'pwell': 'pwell', - 'nwell': 'nwell', - 'GND': 'GND'} +cell_properties.bitcell_1port.port_map = {'bl': 'BL', + 'br': 'BR', + 'wl': 'WL', + 'vdd': 'VDD', + 'vnb': 'pwell', + 'vpb': 'nwell', + 'gnd': 'GND'} cell_properties.bitcell_1port.wl_layer = "m3" cell_properties.bitcell_1port.bl_layer = "m2" @@ -51,6 +50,9 @@ cell_properties.bitcell_1port.gnd_layer = "m1" cell_properties.ptx.model_is_subckt = True +cell_properties.use_strap = True +cell_properties.strap_placement = 8 # this means strap cell gets placed after every 8 bitcells + ################################################### # Custom layer properties ################################################### @@ -86,6 +88,8 @@ m3_stack = ("m3", "via3", "m4") layer_indices = {"poly": 0, "active": 0, + "nwell": 0, + "pwell": 0, "m1": 1, "m2": 2, "m3": 3, @@ -425,3 +429,4 @@ drc_name = "magic" lvs_name = "netgen" pex_name = "magic" +ignore_drc_lvs_on = ["wl_strap"] From c09a98173473a84073a0383e93949997813254be Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Tue, 23 May 2023 20:02:51 -0700 Subject: [PATCH 13/61] make pdk uses conda for gf180 with configure options for local pdk sources --- Makefile | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 283016d2..6c482b7c 100644 --- a/Makefile +++ b/Makefile @@ -112,12 +112,25 @@ endif $(GF180_PDK): $(OPEN_PDKS_DIR) $(GF180_PDKS_DIR) @echo "Installing open_pdks..." - $(DOCKER_CMD) sh -c ". /home/cad-user/.bashrc && cd /pdk/open_pdks && \ - ./configure --enable-gf180mcu-pdk=/pdk/gf180mcu-pdk/libraries && \ - cd gf180mcu && \ - make veryclean && \ - make && \ - make SHARED_PDKS_PATH=/pdk install" +ifeq ($(CONDA_DIR),"") + @cd $(PDK_ROOT)/open_pdks && \ + ./configure --enable-gf180mcu-pdk=$(PDK_ROOT)/gf180mcu-pdk/libraries --enable-primitive-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_pr/latest \ + --enable-sc-7t5v0-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_sc_mcu7t5v0/latest --enable-sc-9t5v0-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_sc_mcu9t5v0/latest && \ + cd gf180mcu && \ + make veryclean && \ + make && \ + make SHARED_PDKS_PATH=$(PDK_ROOT) install +else + @source $(TOP_DIR)/miniconda/bin/activate && \ + cd $(PDK_ROOT)/open_pdks && \ + ./configure --enable-gf180mcu-pdk=$(PDK_ROOT)/gf180mcu-pdk/libraries --enable-primitive-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_pr/latest \ + --enable-sc-7t5v0-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_sc_mcu7t5v0/latest --enable-sc-9t5v0-gf180mcu=$(GF180_PDKS_DIR)/libraries/gf180mcu_fd_sc_mcu9t5v0/latest && \ + cd gf180mcu && \ + make veryclean && \ + make && \ + make SHARED_PDKS_PATH=$(PDK_ROOT) install && \ + conda deactivate +endif $(SRAM_LIB_DIR): check-pdk-root @echo "Cloning SRAM library..." @@ -138,7 +151,7 @@ install: $(SRAM_LIB_DIR) @make $(INSTALL_DIRS) .PHONY: install -pdk: $(SKY130_PDK) $(GF180_PDK) +pdk: $(GF180_PDK) $(SKY130_PDK) @true .PHONY: pdk From 1255a81487db1c2b7e3fd884a83dd87cfa6450f1 Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Mon, 3 Apr 2023 16:04:12 -0700 Subject: [PATCH 14/61] ROM binary file support --- README.md | 4 ++-- docs/source/index.md | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 45d8edae..244e41fc 100644 --- a/README.md +++ b/README.md @@ -66,12 +66,12 @@ OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE). + [H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr) - + # Contributors & Acknowledgment - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect. - [James Stine] from [VLSIARCH] co-founded the project. -- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera +- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker If I forgot to add you, please let me know! diff --git a/docs/source/index.md b/docs/source/index.md index a1f7079a..8efb19c6 100644 --- a/docs/source/index.md +++ b/docs/source/index.md @@ -110,7 +110,7 @@ Commercial tools (optional): * Michael Grimes * Jennifer Sowash * Jesse Cirimelli-Low - + https://www.youtube.com/watch?v=rd5j8mG24H4&t=0s * Many other past students: * Jeff Butera * Tom Golubev From b0a0226e870c35806943e46b39578670259dea96 Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Wed, 17 May 2023 16:07:44 -0700 Subject: [PATCH 15/61] rom array compatability changes --- compiler/modules/rom_base_array.py | 17 +++++++++++----- compiler/modules/rom_base_cell.py | 26 +++++++++++-------------- compiler/modules/rom_poly_tap.py | 18 +++++++++++------ compiler/modules/rom_precharge_array.py | 3 --- compiler/modules/rom_precharge_cell.py | 12 +++++++++--- 5 files changed, 44 insertions(+), 32 deletions(-) diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 9c380624..6907d588 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -202,8 +202,8 @@ class rom_base_array(bitcell_base_array): pitch = drc["{0}_to_{0}".format(self.wordline_layer)] drain_l = self.cell_list[self.row_size][0].get_pin("D") drain_r = self.cell_list[self.row_size][self.column_size - 1].get_pin("D") - gnd_l = drain_l.center() + vector(-0.5 * self.route_width, pitch + via_width + self.route_pitch) - gnd_r = drain_r.center() + vector(0.5 * self.route_width, pitch + via_width + self.route_pitch) + gnd_l = drain_l.center() + vector(-0.5 * self.route_width, 0.5 * pitch + via_width + self.route_pitch) + gnd_r = drain_r.center() + vector(0.5 * self.route_width, 0.5 * pitch + via_width + self.route_pitch) self.add_layout_pin_rect_ends(name="gnd", layer=self.bitline_layer, start=gnd_l, end=gnd_r) @@ -310,7 +310,7 @@ class rom_base_array(bitcell_base_array): directions="nonpref") self.add_via_stack_center(offset=tap_pos, from_layer=self.active_stack[2], - to_layer=self.wordline_layer) + to_layer=self.wordline_layer, directions="nonpref") self.gnd_taps.append(self.add_layout_pin_rect_center("gnd_tap", self.wordline_layer, tap_pos)) def place_precharge(self): @@ -326,6 +326,10 @@ class rom_base_array(bitcell_base_array): def place_bitline_contacts(self): + if "li" in layer: + output_layer = "m1" + else: + output_layer = "m3" rail_y = self.precharge_inst.get_pins("vdd")[0].cy() for bl in range(self.column_size): @@ -340,9 +344,12 @@ class rom_base_array(bitcell_base_array): output_pos = vector(corrected.x, rail_y) - self.add_segment_center(self.bitline_layer, corrected, output_pos) + if output_layer != self.bitline_layer: + self.add_via_stack_center(from_layer=self.bitline_layer, to_layer=output_layer, offset=corrected) - self.add_layout_pin_rect_center(self.bitline_names[0][bl], self.bitline_layer, output_pos ) + self.add_segment_center(output_layer, corrected, output_pos) + + self.add_layout_pin_rect_center(self.bitline_names[0][bl], output_layer, output_pos ) def route_precharge(self): for bl in range(self.column_size): diff --git a/compiler/modules/rom_base_cell.py b/compiler/modules/rom_base_cell.py index 28fc07f0..2c8bf669 100644 --- a/compiler/modules/rom_base_cell.py +++ b/compiler/modules/rom_base_cell.py @@ -15,10 +15,16 @@ from openram.tech import drc class rom_base_cell(design): - def __init__(self, name="", bitline_layer="li", bit_value=1, add_well=False): + def __init__(self, name="", bitline_layer=None, bit_value=1, add_well=False): super().__init__(name) self.bit_value = bit_value - self.bitline_layer = bitline_layer + + if bitline_layer is None and OPTS.tech_name == "sky130": + self.bitline_layer = "li" + elif bitline_layer is None: + self.bitline_layer = "m1" + else: + self.bitline_layer = bitline_layer self.add_well=add_well self.create_netlist() self.create_layout() @@ -41,6 +47,7 @@ class rom_base_cell(design): # Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules def setup_drc_offsets(self): + self.bitline_width = drc(f"minwidth_{self.bitline_layer}") self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active) def add_boundary(self): @@ -50,9 +57,7 @@ class rom_base_cell(design): #cell width with offsets applied, height becomes width when the cells are rotated width = self.cell_inst.height + 2 * self.poly_extend_active - # make the cells square so the pitch of wordlines will match bitlines - if width > height: self.width = width self.height = width @@ -62,7 +67,6 @@ class rom_base_cell(design): super().add_boundary() - def add_modules(self): self.nmos = factory.create(module_type="ptx", @@ -72,7 +76,6 @@ class rom_base_cell(design): add_drain_contact=self.bitline_layer ) - def create_tx(self): self.cell_inst = self.add_inst( name=self.name + "_nmos", mod=self.nmos, @@ -82,7 +85,6 @@ class rom_base_cell(design): else: self.connect_inst(["bl_h", "wl", "bl_l", "gnd"]) - def add_pins(self): if self.bit_value == 0 : pin_list = ["bl", "wl", "gnd"] @@ -95,10 +97,7 @@ class rom_base_cell(design): def place_tx(self): - # sizing_offset = self.cell_inst.height - drc["minwidth_tx"] tx_offset = vector(self.poly_extend_active + self.cell_inst.height + self.poly_size,- 0.5 * self.contact_width - self.active_enclose_contact) - # add rect of poly to account for offset from drc spacing - # self.add_rect_center("poly", poly_offset, self.poly_extend_active_spacing, self.poly_width) self.cell_inst.place(tx_offset, rotate=90) @@ -113,13 +112,10 @@ class rom_base_cell(design): end = poly_offset + vector(self.poly_size, 0) self.add_segment_center("poly", start, end) - def place_bitline(self): - start = self.get_pin("D").center() - end = start + vector(0, 2 * self.active_enclose_contact + 0.5 * self.contact_width + self.active_space) - self.add_segment_center(self.bitline_layer, start, end) + end = start + vector(0, 2 * self.active_enclose_contact + self.contact_width + self.active_space) + self.add_segment_center(self.bitline_layer, start, end, self.bitline_width * 2) def short_gate(self): - self.add_segment_center(self.bitline_layer, self.get_pin("D").center(), self.get_pin("S").center()) \ No newline at end of file diff --git a/compiler/modules/rom_poly_tap.py b/compiler/modules/rom_poly_tap.py index c16323b6..a9aaeb99 100644 --- a/compiler/modules/rom_poly_tap.py +++ b/compiler/modules/rom_poly_tap.py @@ -13,9 +13,9 @@ from openram.tech import drc class rom_poly_tap(design): - def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_active_tap=False, place_poly=None): + def __init__(self, name="", cell_name=None, tx_type="nmos", strap_layer="m2", add_active_tap=False, place_poly=False): super().__init__(name, cell_name) - self.strap_layer=strap_layer + self.strap_layer = strap_layer self.tx_type = tx_type self.add_tap = add_active_tap if place_poly is None: @@ -36,9 +36,10 @@ class rom_poly_tap(design): self.place_via() self.add_boundary() + self.extend_poly() + if self.add_tap or self.place_poly: self.place_active_tap() - self.extend_poly() def add_boundary(self): contact_width = self.poly_contact.width @@ -59,9 +60,14 @@ class rom_poly_tap(design): contact_x = contact_width * 0.5 + self.contact_x_offset self.contact_offset = vector(contact_x, contact_y) + if OPTS.tech_name == "sky130": + directions="pref" + else: + directions="nonpref" self.via = self.add_via_stack_center(from_layer="poly", to_layer=self.strap_layer, - offset=self.contact_offset) + offset=self.contact_offset, + directions=directions) self.add_layout_pin_rect_center("poly_tap", self.strap_layer, self.contact_offset) def extend_poly(self): @@ -69,8 +75,8 @@ class rom_poly_tap(design): if self.tx_type == "pmos": y_offset = -self.height start = self.via.center() + vector(0, y_offset) - - self.add_segment_center("poly", start, vector(self.via.cx() + self.pitch_offset, self.via.cy() + y_offset)) + if self.place_poly: + self.add_segment_center("poly", start, vector(self.via.cx() + self.pitch_offset, self.via.cy() + y_offset)) self.add_segment_center("poly", start, vector(0, self.via.cy() + y_offset)) def place_active_tap(self): diff --git a/compiler/modules/rom_precharge_array.py b/compiler/modules/rom_precharge_array.py index a450c968..819f14ed 100644 --- a/compiler/modules/rom_precharge_array.py +++ b/compiler/modules/rom_precharge_array.py @@ -125,7 +125,6 @@ class rom_precharge_array(design): # columns are bit lines cell_x = 0 - for col in range(self.cols): if col % self.strap_spacing == 0: @@ -136,7 +135,6 @@ class rom_precharge_array(design): cell_x += self.poly_tap.pitch_offset self.pmos_insts[col].place(vector(cell_x, cell_y)) - self.add_label("debug", "li", vector(cell_x, cell_y)) cell_x += self.pmos.width self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height)) @@ -150,7 +148,6 @@ class rom_precharge_array(design): self.add_layout_pin_rect_center(bl, self.bitline_layer, source_pin.center()) def route_supply(self): - self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer) def connect_taps(self): diff --git a/compiler/modules/rom_precharge_cell.py b/compiler/modules/rom_precharge_cell.py index 3d4730aa..1777e507 100644 --- a/compiler/modules/rom_precharge_cell.py +++ b/compiler/modules/rom_precharge_cell.py @@ -26,7 +26,10 @@ class rom_precharge_cell(rom_base_cell): self.extend_well() def add_modules(self): - width = pgate.nearest_bin("pmos", drc["minwidth_tx"]) + if OPTS.tech_name == "sky130": + width = pgate.nearest_bin("pmos", drc["minwidth_tx"]) + else: + width = drc("minwidth_tx") self.pmos = factory.create(module_type="ptx", module_name="pre_pmos_mod", tx_type="pmos", @@ -60,8 +63,7 @@ class rom_precharge_cell(rom_base_cell): def place_tap(self): source = self.cell_inst.get_pin("S") - - tap_y = source.cy() - self.contact_width - 2 * self.active_enclose_contact - self.active_space + tap_y = source.cy() - self.contact_width - 5 * self.active_enclose_contact - self.active_space self.tap_offset = abs(tap_y) pos = vector(source.cx(), tap_y ) @@ -83,4 +85,8 @@ class rom_precharge_cell(rom_base_cell): self.remove_layout_pin("S") def place_bitline(self): + pass + + def short_gate(self): + print("not shorting") pass \ No newline at end of file From 0040efb86f3f78aa78a5aeb2e67c4b46f1bbe46b Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Wed, 24 May 2023 14:23:50 -0700 Subject: [PATCH 16/61] workaround for magic drc in gf180 --- compiler/verify/magic.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 2c6a466e..ae58c80c 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -188,6 +188,9 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write("expand\n") f.write('puts "Finished expanding"\n') f.write("drc euclidean on\n") + # Workaround to address DRC CIF style not loading if 'drc check' is run before catchup + if OPTS.tech_name=="gf180mcu": + f.write("drc catchup\n") f.write("drc check\n") f.write('puts "Finished drc check"\n') f.write("drc catchup\n") From d6cb15c82ddabe111da1562d6b24ac87b18ce0e1 Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Tue, 25 Jul 2023 14:45:14 -0700 Subject: [PATCH 17/61] Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. --- compiler/base/contact.py | 23 +++++++++++--- compiler/base/hierarchy_layout.py | 10 +++--- compiler/modules/ptx.py | 23 +++++++++----- compiler/modules/rom_base_array.py | 4 +-- compiler/modules/rom_base_cell.py | 4 +++ compiler/modules/rom_poly_tap.py | 2 +- compiler/modules/rom_precharge_array.py | 18 ++++------- compiler/modules/rom_precharge_cell.py | 11 ++++--- compiler/tests/04_rom_precharge_test.py | 40 ++++++++++++++++++++++++ technology/gf180mcu/__init__.py | 4 +-- technology/gf180mcu/tech/tech.py | 41 +++++++++++++++++-------- 11 files changed, 129 insertions(+), 51 deletions(-) create mode 100644 compiler/tests/04_rom_precharge_test.py diff --git a/compiler/base/contact.py b/compiler/base/contact.py index 84f60d0e..ea7280a1 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -10,7 +10,7 @@ from openram.tech import drc, layer, preferred_directions from openram.tech import layer as tech_layers from .hierarchy_design import hierarchy_design from .vector import vector - +from .utils import ceil class contact(hierarchy_design): """ @@ -125,6 +125,8 @@ class contact(hierarchy_design): self.first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name)) self.first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name)) + self.first_layer_minarea = drc("minarea_{0}".format(self.first_layer_name)) + # If there's a different rule for active # FIXME: Make this more elegant if self.is_well_contact and self.first_layer_name == "active" and "tap_extend_contact" in drc.keys(): @@ -135,7 +137,7 @@ class contact(hierarchy_design): self.second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name)) self.second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name)) self.second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name)) - + self.second_layer_minarea = drc("minarea_{0}".format(self.second_layer_name)) # In some technologies, the minimum width may be larger # than the overlap requirement around the via, so # check this for each dimension. @@ -143,7 +145,7 @@ class contact(hierarchy_design): self.first_layer_horizontal_enclosure = max(self.first_layer_enclosure, (self.first_layer_minwidth - self.contact_array_width) / 2) self.first_layer_vertical_enclosure = max(self.first_layer_extend, - (self.first_layer_minwidth - self.contact_array_height) / 2) + (self.first_layer_minwidth - self.contact_array_height) / 2) elif self.directions[0] == "H": self.first_layer_horizontal_enclosure = max(self.first_layer_extend, (self.first_layer_minwidth - self.contact_array_width) / 2) @@ -166,7 +168,7 @@ class contact(hierarchy_design): self.second_layer_vertical_enclosure = max(self.second_layer_enclosure, (self.second_layer_minwidth - self.contact_array_width) / 2) else: - debug.error("Invalid secon layer direction: ".format(self.directions[1]), -1) + debug.error("Invalid second layer direction: ".format(self.directions[1]), -1) def create_contact_array(self): """ Create the contact array at the origin""" @@ -221,6 +223,18 @@ class contact(hierarchy_design): first_layer_name = "tap" else: first_layer_name = self.first_layer_name + + area = self.first_layer_width * self.first_layer_height + if area < self.first_layer_minarea and self.is_well_contact: + if self.directions[0] == "V": + area_extend = (self.first_layer_minarea / self.first_layer_width) - self.first_layer_height + self.first_layer_height = ceil(self.first_layer_height + area_extend) + self.first_layer_position = self.first_layer_position - vector(0, area_extend / 2) + elif self.directions[0] == "H": + area_extend = (self.first_layer_minarea / self.first_layer_height) - self.first_layer_width + self.first_layer_width = ceil(self.first_layer_height + area_extend) + self.first_layer_position = self.first_layer_position - vector(area_extend / 2, 0) + self.add_rect(layer=first_layer_name, offset=self.first_layer_position, width=self.first_layer_width, @@ -236,6 +250,7 @@ class contact(hierarchy_design): self.second_layer_minwidth) self.second_layer_height = max(self.contact_array_height + 2 * self.second_layer_vertical_enclosure, self.second_layer_minwidth) + self.add_rect(layer=self.second_layer_name, offset=self.second_layer_position, width=self.second_layer_width, diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7137566f..504cf6a9 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -22,7 +22,7 @@ from openram.sram_factory import factory from openram import OPTS from .vector import vector from .pin_layout import pin_layout -from .utils import round_to_grid +from .utils import round_to_grid, ceil from . import geometry try: @@ -838,8 +838,7 @@ class layout(): from_id = tech_layer_indices[from_layer] to_id = tech_layer_indices[to_layer] - - layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] >= from_id and tech_layer_indices[x] < to_id] + layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] > from_id and tech_layer_indices[x] < to_id] return layer_list @@ -1368,12 +1367,11 @@ class layout(): min_width = drc("minwidth_{}".format(layer)) if preferred_directions[layer] == "V": - new_height = max(min_area / width, min_width) + new_height = ceil(max(min_area / width, min_width)) new_width = width else: - new_width = max(min_area / height, min_width) + new_width = ceil(max(min_area / height, min_width)) new_height = height - debug.check(min_area <= round_to_grid(new_height*new_width), "Min area violated.") self.add_rect_center(layer=layer, diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py index 250cd3f6..995bef1f 100644 --- a/compiler/modules/ptx.py +++ b/compiler/modules/ptx.py @@ -129,12 +129,15 @@ class ptx(design): # be decided in the layout later. area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width + + # self.channel_length = drc("minlength_channel") if OPTS.tech_name != "gf180mcu" else drc("minlength_channel_" + self.tx_type) + self.channel_length = drc("minlength_channel") if cell_props.ptx.model_is_subckt: # sky130 main_str = "X{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], self.mults, self.tx_width, - drc("minwidth_poly")) + self.channel_length) # Perimeters are in microns # Area is in u since it is microns square area_str = "pd={0:.2f} ps={0:.2f} as={1:.2f}u ad={1:.2f}u".format(perimeter_sd, @@ -143,7 +146,7 @@ class ptx(design): main_str = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], self.mults, self.tx_width, - drc("minwidth_poly")) + self.channel_length) area_str = "pd={0:.2f}u ps={0:.2f}u as={1:.2f}p ad={1:.2f}p".format(perimeter_sd, area_sd) self.spice_device = main_str + area_str @@ -160,17 +163,17 @@ class ptx(design): self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult=1".format("nshort" if self.tx_type == "nmos" else "pshort", self.mults, self.tx_width, - drc("minwidth_poly")) + self.channel_length) elif cell_props.ptx.model_is_subckt: self.lvs_device = "X{{0}} {{1}} {0} m={1} w={2}u l={3}u".format(spice[self.tx_type], self.mults, self.tx_width, - drc("minwidth_poly")) + self.channel_length) else: self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2}u l={3}u ".format(spice[self.tx_type], self.mults, self.tx_width, - drc("minwidth_poly")) + self.channel_length) def setup_layout_constants(self): """ @@ -196,6 +199,9 @@ class ptx(design): directions=("V", "V"), dimensions=(1, self.num_contacts)) + if OPTS.tech_name == "gf180mcu": + self.poly_width = self.channel_length + # This is the extra poly spacing due to the poly contact to poly contact pitch # of contacted gates extra_poly_contact_width = self.poly_contact.width - self.poly_width @@ -216,11 +222,12 @@ class ptx(design): self.active_width = 2 * self.end_to_contact + self.active_contact.width \ + 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch - # Active height is just the transistor width - self.active_height = self.tx_width + # Active height is either the transistor width or the wide enough to enclose the active contact + self.active_height = max(self.tx_width, self.active_contact.width + 2 * self.active_enclose_contact) # Poly height must include poly extension over active - self.poly_height = self.tx_width + 2 * self.poly_extend_active + self.poly_height = self.active_height + 2 * self.poly_extend_active + self.active_offset = vector([self.well_enclose_active] * 2) diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 6907d588..804ce70a 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -10,7 +10,7 @@ import math from .bitcell_base_array import bitcell_base_array from openram.base import vector -from openram import OPTS, debug +from openram import debug from openram.sram_factory import factory from openram.tech import drc, layer @@ -156,7 +156,7 @@ class rom_base_array(bitcell_base_array): name = "bit_r{0}_c{1}".format(row, col) # when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection - # when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection + # when col = col_size - 1 connected to gnd otherwise create new bl connection # debug.info(1, "Create cell: r{0}, c{1}".format(row, col)) if row == self.row_size: diff --git a/compiler/modules/rom_base_cell.py b/compiler/modules/rom_base_cell.py index 2c8bf669..1f47b88f 100644 --- a/compiler/modules/rom_base_cell.py +++ b/compiler/modules/rom_base_cell.py @@ -80,6 +80,8 @@ class rom_base_cell(design): self.cell_inst = self.add_inst( name=self.name + "_nmos", mod=self.nmos, ) + print("bitmos", self.cell_inst.height, self.cell_inst.width) + if self.bit_value == 0: self.connect_inst(["bl", "wl", "bl", "gnd"]) else: @@ -103,6 +105,8 @@ class rom_base_cell(design): self.copy_layout_pin(self.cell_inst, "S", "S") self.copy_layout_pin(self.cell_inst, "D", "D") + self.copy_layout_pin(self.cell_inst, "G", "G") + self.source_pos = self.cell_inst.get_pin("S").center() def place_poly(self): diff --git a/compiler/modules/rom_poly_tap.py b/compiler/modules/rom_poly_tap.py index a9aaeb99..2bbbe18f 100644 --- a/compiler/modules/rom_poly_tap.py +++ b/compiler/modules/rom_poly_tap.py @@ -36,7 +36,7 @@ class rom_poly_tap(design): self.place_via() self.add_boundary() - self.extend_poly() + # self.extend_poly() if self.add_tap or self.place_poly: self.place_active_tap() diff --git a/compiler/modules/rom_precharge_array.py b/compiler/modules/rom_precharge_array.py index 819f14ed..995f2ef9 100644 --- a/compiler/modules/rom_precharge_array.py +++ b/compiler/modules/rom_precharge_array.py @@ -17,9 +17,10 @@ class rom_precharge_array(design): """ An array of inverters to create the inverted address lines for the rom decoder """ - def __init__(self, cols, name="", bitline_layer=None, strap_spacing=None, strap_layer="m2", tap_direction="row"): + def __init__(self, cols, name="", bitline_layer="m2", strap_spacing=None, strap_layer="m3", tap_direction="row"): self.cols = cols self.strap_layer = strap_layer + self.bitline_layer = bitline_layer self.tap_direction = tap_direction if "li" in layer: @@ -27,14 +28,6 @@ class rom_precharge_array(design): else: self.supply_layer = "m1" - if bitline_layer is not None: - self.bitline_layer = bitline_layer - else: - self.bitline_layer = self.supply_layer - - - if name=="": - name = "rom_inv_array_{0}".format(cols) if strap_spacing != None: self.strap_spacing = strap_spacing @@ -128,7 +121,7 @@ class rom_precharge_array(design): for col in range(self.cols): if col % self.strap_spacing == 0: - self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height)) + self.tap_insts[strap_num].place(vector(cell_x + self.poly_space, cell_y + self.poly_tap.height)) strap_num += 1 if self.tap_direction == "col": @@ -137,7 +130,7 @@ class rom_precharge_array(design): self.pmos_insts[col].place(vector(cell_x, cell_y)) cell_x += self.pmos.width - self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height)) + self.tap_insts[strap_num].place(vector(cell_x + self.poly_space, cell_y + self.poly_tap.height)) def create_layout_pins(self): self.copy_layout_pin(self.tap_insts[0], "poly_tap", "gate") @@ -158,11 +151,12 @@ class rom_precharge_array(design): for tap in self.tap_insts: tap_pin = tap.get_pin("poly_tap") start = vector(tap_pin.cx(), tap_pin.by()) - end = vector(start.x, tap.mod.get_pin("poly_tap").cy()) + end = vector(start.x, self.pmos_insts[0].get_pin("G").cy()) self.add_segment_center(layer="poly", start=start, end=end) offset_start = vector(end.x - self.poly_tap.width + self.poly_extend_active, end.y) offset_end = end + vector(0.5*self.poly_width, 0) self.add_segment_center(layer="poly", start=offset_start, end=offset_end) + self.add_segment_center(layer="poly", start=self.pmos_insts[-1].get_pin("G").center(), end=offset_end) def extend_well(self): self.well_offset = self.pmos.tap_offset diff --git a/compiler/modules/rom_precharge_cell.py b/compiler/modules/rom_precharge_cell.py index 1777e507..6a2f4ac7 100644 --- a/compiler/modules/rom_precharge_cell.py +++ b/compiler/modules/rom_precharge_cell.py @@ -24,6 +24,8 @@ class rom_precharge_cell(rom_base_cell): self.place_tap() self.extend_well() + print("precharge", self.height, self.width) + def add_modules(self): if OPTS.tech_name == "sky130": @@ -42,6 +44,7 @@ class rom_precharge_cell(rom_base_cell): self.cell_inst = self.add_inst( name="precharge_pmos", mod=self.pmos, ) + print("premos", self.cell_inst.height, self.cell_inst.width) self.connect_inst(["bitline", "gate", "vdd", "vdd"]) def add_pins(self): @@ -55,10 +58,10 @@ class rom_precharge_cell(rom_base_cell): self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active) def extend_well(self): - - well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width + print(self.nwell_enclose_active) + well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active well_ll = vector(0, well_y) - height = self.get_pin("D").cy() + 0.5 * self.nwell_width - well_y + height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y self.add_rect("nwell", well_ll, self.width , height) def place_tap(self): @@ -67,7 +70,7 @@ class rom_precharge_cell(rom_base_cell): self.tap_offset = abs(tap_y) pos = vector(source.cx(), tap_y ) - self.add_via_center(layers=self.active_stack, + self.tap = self.add_via_center(layers=self.active_stack, offset=pos, implant_type="n", well_type="n", diff --git a/compiler/tests/04_rom_precharge_test.py b/compiler/tests/04_rom_precharge_test.py new file mode 100644 index 00000000..aa0c443b --- /dev/null +++ b/compiler/tests/04_rom_precharge_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class precharge_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + # check precharge in single port + debug.info(2, "Testing rom precharge bitcell") + + + tx = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", bitline_layer="m2", supply_layer="m1") + self.local_check(tx) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/technology/gf180mcu/__init__.py b/technology/gf180mcu/__init__.py index 10a3899a..48aedd88 100644 --- a/technology/gf180mcu/__init__.py +++ b/technology/gf180mcu/__init__.py @@ -22,7 +22,7 @@ os.environ["MGC_TMPDIR"] = "/tmp" # OpenPDK needed for magicrc, tech file and spice models of transistors if 'PDK_ROOT' in os.environ: - open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuA', 'libs.tech') + open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuD', 'libs.tech') else: raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.") @@ -34,7 +34,7 @@ if not os.path.exists(gf180_lib_ngspice): os.environ["SPICE_MODEL_DIR"] = spice_model_dir open_pdks = os.path.abspath(open_pdks) -gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuA.magicrc") +gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuD.magicrc") if not os.path.exists(gf180_magicrc): raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks)) os.environ["OPENRAM_MAGICRC"] = gf180_magicrc diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index cce0f828..4d1ed4e8 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -31,7 +31,7 @@ tech_modules["bitcell_1port"] = "gf180_bitcell" cell_properties = d.cell_properties() # is there a better way to tell if the user overrode the port order than this? -# this is needed to correctly create the bitcell_pins list in the bitcell_base_array +# this is needed to correctly create the bitcell_pins list in the bitcell_base_array cell_properties.override_bitcell_1port_order = True cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl'] cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"] @@ -189,8 +189,13 @@ drc = d.design_rules("gf180") # grid size drc["grid"] = 0.005 -drc["minwidth_tx"] = 0.28 -#drc["minlength_channel"] = 0.150 +# minwidth_tx with contact (no dog bone transistors) +drc["minwidth_tx"] = 0.5 +# PL.2 Min gate width/channel length for 6V pmos (0.7 for 6V nmos) +drc["minlength_channel"] = 0.7 + +drc["minlength_channel_pmos"] = 0.55 +drc["minlength_channel_nmos"] = 0.7 drc["pwell_to_nwell"] = 0 # assuming same potential @@ -199,11 +204,13 @@ drc.add_layer("nwell", spacing=0.6) drc.add_layer("pwell", - width=0.74, # 0.6 for 1.5v - spacing=0.86) # equal potential 1.7 otherwise + width=0.74, # 0.6 for 3.3v + spacing=0.86) # equal potential +# PL.1 minwidth of interconnect poly 5/6V +# PL.3a poly spacing 5/6V drc.add_layer("poly", - width=0.18, + width=0.2, spacing=0.24) drc["poly_extend_active"] = 0.22 @@ -216,9 +223,14 @@ drc["poly_to_active"] = 0.1 #drc["poly_to_field_poly"] = 0.210 +# +# DF.1a - minwidth of active (5/6V) +# DF.3a - minspacing of active of the same type (5/6V) +# DF.9 - minarea of active area=0.2025 (5/6V) drc.add_layer("active", - width=0.22, - spacing=0.280) + width=0.3, + spacing=0.36, + area=0.2025) drc.add_enclosure("dnwell", layer="pwell", @@ -250,22 +262,27 @@ drc.add_layer("implant", drc.add_layer("contact", width=0.22, spacing=0.25) - +# CO.4 - active enclosure of contact +# extension is not a true drc rule, used to extend active to reach active min area drc.add_enclosure("active", layer="contact", - enclosure=0.01, - extension=0.01) + enclosure=0.07, + extension=0.07) + drc.add_enclosure("poly", layer="contact", enclosure=0.07, extension=0.07) -drc["active_contact_to_gate"] = 0.145 +drc["active_contact_to_gate"] = 0.15 drc["poly_contact_to_gate"] = 0.165 #drc["npc_enclose_poly"] = 0.1 +# M1.1 - width +# M1.2a - space +# M1.3 - area drc.add_layer("m1", width=0.23, spacing=0.23, From 4bb586c949906216e8e24593948fcb03afc049f3 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 15:50:42 -0700 Subject: [PATCH 18/61] decoder nand custom cell --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 0 -> 4632 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 159 ++++++++++++++++++ .../sp_lib/gf180mcu_3v3__nand2_1_dec.sp | 6 + technology/gf180mcu/tech/tech.py | 2 + 4 files changed, 167 insertions(+) create mode 100644 technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds create mode 100644 technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag create mode 100644 technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds new file mode 100644 index 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zZ+j%;=@+GgnZM)a2l@TPwm(MQk6JpJJhZY>p2l(<`qH?}xV!IDTPx# literal 0 HcmV?d00001 diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag new file mode 100644 index 00000000..b7e44ef3 --- /dev/null +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -0,0 +1,159 @@ +magic +tech gf180mcuD +magscale 1 10 +timestamp 1694471735 +<< nwell >> +rect 0 674 620 1392 +<< nmos >> +rect 220 210 280 380 +rect 330 210 390 380 +<< pmos >> +rect 190 764 250 1104 +rect 360 764 420 1104 +<< ndiff >> +rect 120 318 220 380 +rect 120 272 142 318 +rect 188 272 220 318 +rect 120 210 220 272 +rect 280 210 330 380 +rect 390 318 490 380 +rect 390 272 422 318 +rect 468 272 490 318 +rect 390 210 490 272 +<< pdiff >> +rect 90 1051 190 1104 +rect 90 817 112 1051 +rect 158 817 190 1051 +rect 90 764 190 817 +rect 250 1051 360 1104 +rect 250 817 282 1051 +rect 328 817 360 1051 +rect 250 764 360 817 +rect 420 1051 520 1104 +rect 420 817 452 1051 +rect 498 817 520 1051 +rect 420 764 520 817 +<< ndiffc >> +rect 142 272 188 318 +rect 422 272 468 318 +<< pdiffc >> +rect 112 817 158 1051 +rect 282 817 328 1051 +rect 452 817 498 1051 +<< psubdiff >> +rect 540 159 620 180 +rect 540 113 557 159 +rect 603 113 620 159 +rect 540 73 620 113 +<< nsubdiff >> +rect 436 1233 543 1250 +rect 436 1187 473 1233 +rect 519 1187 543 1233 +rect 436 1170 543 1187 +<< psubdiffcont >> +rect 557 113 603 159 +<< nsubdiffcont >> +rect 473 1187 519 1233 +<< polysilicon >> +rect 190 1104 250 1154 +rect 360 1104 420 1154 +rect 190 470 250 764 +rect 360 470 420 764 +rect 190 430 280 470 +rect 220 380 280 430 +rect 330 430 420 470 +rect 330 380 390 430 +rect 220 170 280 210 +rect 180 149 280 170 +rect 180 103 207 149 +rect 253 103 280 149 +rect 180 87 280 103 +rect 330 170 390 210 +rect 330 149 430 170 +rect 330 103 346 149 +rect 392 103 430 149 +rect 330 87 430 103 +<< polycontact >> +rect 207 103 253 149 +rect 346 103 392 149 +<< metal1 >> +rect 470 1236 522 1248 +rect 112 1164 330 1210 +rect 112 1051 158 1062 +rect 280 1051 330 1164 +rect 470 1137 522 1184 +rect 158 966 164 978 +rect 158 902 164 914 +rect 112 806 158 817 +rect 280 817 282 1051 +rect 328 817 330 1051 +rect 452 1051 498 1062 +rect 446 966 452 978 +rect 446 902 452 914 +rect 280 450 330 817 +rect 452 806 498 817 +rect 140 400 330 450 +rect 140 318 190 400 +rect 140 272 142 318 +rect 188 272 190 318 +rect 140 210 190 272 +rect 422 324 480 347 +rect 474 272 480 324 +rect 422 240 480 272 +rect 544 162 614 178 +rect 155 149 267 152 +rect 155 103 207 149 +rect 253 103 267 149 +rect 155 100 267 103 +rect 332 149 451 152 +rect 332 103 346 149 +rect 392 103 451 149 +rect 332 100 451 103 +rect 544 110 554 162 +rect 606 110 614 162 +rect 544 79 614 110 +<< via1 >> +rect 470 1233 522 1236 +rect 470 1187 473 1233 +rect 473 1187 519 1233 +rect 519 1187 522 1233 +rect 470 1184 522 1187 +rect 112 914 158 966 +rect 158 914 164 966 +rect 446 914 452 966 +rect 452 914 498 966 +rect 422 318 474 324 +rect 422 272 468 318 +rect 468 272 474 318 +rect 554 159 606 162 +rect 554 113 557 159 +rect 557 113 603 159 +rect 603 113 606 159 +rect 554 110 606 113 +<< metal2 >> +rect 468 1236 524 1248 +rect 468 1184 470 1236 +rect 522 1184 524 1236 +rect 468 968 524 1184 +rect 60 966 572 968 +rect 60 914 112 966 +rect 164 914 446 966 +rect 498 914 572 966 +rect 60 912 572 914 +rect 60 324 608 326 +rect 60 272 422 324 +rect 474 272 608 324 +rect 60 270 608 272 +rect 552 162 608 270 +rect 552 110 554 162 +rect 606 110 608 162 +rect 552 88 608 110 +<< labels >> +rlabel metal1 s 230 126 230 126 4 B +rlabel metal1 s 369 126 369 126 4 A +rlabel metal1 s 135 1187 135 1187 4 Y +rlabel metal2 s 547 940 547 940 4 VDD +rlabel metal2 s 524 298 524 298 4 GND +<< properties >> +string FIXED_BBOX 0 0 620 1392 +<< end >> diff --git a/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp new file mode 100644 index 00000000..f2e114c0 --- /dev/null +++ b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp @@ -0,0 +1,6 @@ +.subckt gf180mcu_3v3__nand2_1_dec A B Y VDD VSS +X0 VDD B Y VDD pfet_03p3 w=1.7u l=0.3u +X1 Y A VDD VDD pfet_03p3 w=1.7u l=0.3u +X2 a_28_21# A Y VSS nfet_03p3 w=0.85u l=0.3u +X3 VSS B a_28_21# VSS nfet_03p3 w=0.85u l=0.3u +.ends \ No newline at end of file diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 4d1ed4e8..6edf199f 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -53,6 +53,8 @@ cell_properties.ptx.model_is_subckt = True cell_properties.use_strap = True cell_properties.strap_placement = 8 # this means strap cell gets placed after every 8 bitcells +cell_properties.names["nand2_dec"] = ["gf180mcu_3v3__nand2_1_dec"] + ################################################### # Custom layer properties ################################################### From 88782b0a58d3be5ae1b17e0f68917869908639ca Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 16:24:22 -0700 Subject: [PATCH 19/61] rotated nand2_dec --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4632 -> 4722 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 277 +++++++++--------- 2 files changed, 140 insertions(+), 137 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index c2f670bea8ad0c2d9a4795c8c0682ac7a162d5de..82a49d38a3e25d62434525b8a2b4095b7fbde61a 100644 GIT binary patch literal 4722 zcma)=TWB0r9L7&J$zEo5cXpE)NeMMx5frtp*FM;b0TGKrDN>6PrL}@!?1NUYMnaIH zf<=gkU?03ZRJ0FLi}sU9}&i|Y_ z=j?1;*_BGW-Dpp#a^BTk>{@QvjpToK>r3UQ_iwoSwrBUgFtO?2riqEkCnxu9oY*k2 z@2S1c4fXclyY2P69-KS2aL@RuTi<_g&n`FGU(i~)sI|VTbLB?KUE#{jl5_6nRwVjhcocEK*ovU5x92wu@T~{&NT-! zDhC68nl2x8E*dko_oQk17kp3U(OB4D{F~!XQ?hmg+9_vLzGD1i`SG`LfAvN5N$)rC z&5X*yeEr>ikN3gooV6o%e7hd>lLyQv;lj@Wu3TRX5Szt70^FADOsM}fUBY^)Oc`rid^?`XD^p>A@n`FwWWQ`rWdC-(%U_?L z|DMkgd$vb6gMjSZ`SG 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zcmaKwPiP%g6voe+d2imlm)HDj`trw+)>uSJu`g*P8YR#gbfJhy6(eGl)(T>aCdTGk@H+a_+$CQ;!_6=|;tBN!4og)GXN%*)B^4BQx7S9OFB_cI0r>`ehaxzATJnW58S^f9W46y6!+iy7W;h_dBMrH*}(0d(!roV{SN*O z^pC_k^!F)!qr(3z`hO9Akn3droYKL{{N3{|KjZ1|Q~LR^pZo4Ex&3pU%r8n`3j5>Z z$lXED$p`Qc_n=Sdov^=l4&Ik=4?(Wep7)dv2KUdr@q)|Gc;@d@`a;RSyLkVjE$qLC z`6JiShp7Uk_rm_#Eav}S)DLo<_E(F5{ETP*KBXsNfBQx3cN2NZcQOB{ zp-<_X75?W@`z826uG6{2Q#u%|pLuJmE0mH_9rrB8+>?x#kCYAu{XDB`pCXoX zi*@89rGr6#@|?>{vTp8QWIg%yN`h)Y6 z^tC?oq(8qN^t0}fEm!~ON3MQRIvDh`KE{#sv3^l{m7n!7j--$Ei_)w7tbgclSO4%8 zSHCD7tgN4Lte-yCFG{cSvu?(b^s#5fqGT{xIX(tGM;`>dR6}-^sKps{)6ln`zJ~VgZ0ywy(i@B@N=9# zQu?;{htm9}%ZU2~IYB-vE!+c9IvC6!H}U!RC-Q;OUzmeMPw8OLpSjAk5b4ja z2mS5S@V|+<0r`9Hz(1bS!OY*ma(I8l{=1RkS2eyr);ExE-IB@VFn-`$;{Qc8F`+K% zP(@UPvuFGO*ILb^cmN^e4aF0KlRmx&o#w>v%_lymbg;PNl0SP=uc972v7fVVl2bYu^tUgg_8YNpFy4ndcEwXVSoH5L z^$)!o{T+G1?8LakQ#u&**Y@KH#S=m@exN|<+dlD2`RQxi<^0KG@c)GU=adcx^Yaaf zZ+j%;=@+GgnZM)a2l@TPwm(MQk6JpJJhZY>p2l(<`qH?}xV!IDTPx# diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index b7e44ef3..3f18a270 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,159 +1,162 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694471735 +timestamp 1694474583 << nwell >> -rect 0 674 620 1392 +rect 290 388 1009 1008 << nmos >> -rect 220 210 280 380 -rect 330 210 390 380 +rect -174 728 -4 788 +rect -174 618 -4 678 << pmos >> -rect 190 764 250 1104 -rect 360 764 420 1104 +rect 380 758 721 818 +rect 380 588 721 648 << ndiff >> -rect 120 318 220 380 -rect 120 272 142 318 -rect 188 272 220 318 -rect 120 210 220 272 -rect 280 210 330 380 -rect 390 318 490 380 -rect 390 272 422 318 -rect 468 272 490 318 -rect 390 210 490 272 +rect -174 866 -4 888 +rect -174 820 -112 866 +rect -66 820 -4 866 +rect -174 788 -4 820 +rect -174 678 -4 728 +rect -174 586 -4 618 +rect -174 540 -112 586 +rect -66 540 -4 586 +rect -174 518 -4 540 << pdiff >> -rect 90 1051 190 1104 -rect 90 817 112 1051 -rect 158 817 190 1051 -rect 90 764 190 817 -rect 250 1051 360 1104 -rect 250 817 282 1051 -rect 328 817 360 1051 -rect 250 764 360 817 -rect 420 1051 520 1104 -rect 420 817 452 1051 -rect 498 817 520 1051 -rect 420 764 520 817 +rect 380 896 721 918 +rect 380 850 433 896 +rect 668 850 721 896 +rect 380 818 721 850 +rect 380 726 721 758 +rect 380 680 433 726 +rect 668 680 721 726 +rect 380 648 721 680 +rect 380 556 721 588 +rect 380 510 433 556 +rect 668 510 721 556 +rect 380 488 721 510 << ndiffc >> -rect 142 272 188 318 -rect 422 272 468 318 +rect -112 820 -66 866 +rect -112 540 -66 586 << pdiffc >> -rect 112 817 158 1051 -rect 282 817 328 1051 -rect 452 817 498 1051 +rect 433 850 668 896 +rect 433 680 668 726 +rect 433 510 668 556 << psubdiff >> -rect 540 159 620 180 -rect 540 113 557 159 -rect 603 113 620 159 -rect 540 73 620 113 +rect -311 451 -204 468 +rect -311 405 -271 451 +rect -225 405 -204 451 +rect -311 388 -204 405 << nsubdiff >> -rect 436 1233 543 1250 -rect 436 1187 473 1233 -rect 519 1187 543 1233 -rect 436 1170 543 1187 +rect 787 535 867 572 +rect 787 489 804 535 +rect 850 489 867 535 +rect 787 465 867 489 << psubdiffcont >> -rect 557 113 603 159 +rect -271 405 -225 451 << nsubdiffcont >> -rect 473 1187 519 1233 +rect 804 489 850 535 << polysilicon >> -rect 190 1104 250 1154 -rect 360 1104 420 1154 -rect 190 470 250 764 -rect 360 470 420 764 -rect 190 430 280 470 -rect 220 380 280 430 -rect 330 430 420 470 -rect 330 380 390 430 -rect 220 170 280 210 -rect 180 149 280 170 -rect 180 103 207 149 -rect 253 103 280 149 -rect 180 87 280 103 -rect 330 170 390 210 -rect 330 149 430 170 -rect 330 103 346 149 -rect 392 103 430 149 -rect 330 87 430 103 +rect -297 801 -214 828 +rect -297 755 -281 801 +rect -235 788 -214 801 +rect 46 788 380 818 +rect -235 755 -174 788 +rect -297 728 -174 755 +rect -4 758 380 788 +rect 721 758 771 818 +rect -4 728 86 758 +rect -297 662 -174 678 +rect -297 616 -281 662 +rect -235 618 -174 662 +rect -4 648 86 678 +rect -4 618 380 648 +rect -235 616 -214 618 +rect -297 578 -214 616 +rect 46 588 380 618 +rect 721 588 771 648 << polycontact >> -rect 207 103 253 149 -rect 346 103 392 149 +rect -281 755 -235 801 +rect -281 616 -235 662 << metal1 >> -rect 470 1236 522 1248 -rect 112 1164 330 1210 -rect 112 1051 158 1062 -rect 280 1051 330 1164 -rect 470 1137 522 1184 -rect 158 966 164 978 -rect 158 902 164 914 -rect 112 806 158 817 -rect 280 817 282 1051 -rect 328 817 330 1051 -rect 452 1051 498 1062 -rect 446 966 452 978 -rect 446 902 452 914 -rect 280 450 330 817 -rect 452 806 498 817 -rect 140 400 330 450 -rect 140 318 190 400 -rect 140 272 142 318 -rect 188 272 190 318 -rect 140 210 190 272 -rect 422 324 480 347 -rect 474 272 480 324 -rect 422 240 480 272 -rect 544 162 614 178 -rect 155 149 267 152 -rect 155 103 207 149 -rect 253 103 267 149 -rect 155 100 267 103 -rect 332 149 451 152 -rect 332 103 346 149 -rect 392 103 451 149 -rect 332 100 451 103 -rect 544 110 554 162 -rect 606 110 614 162 -rect 544 79 614 110 +rect -174 866 66 868 +rect -284 801 -232 853 +rect -174 820 -112 866 +rect -66 820 66 866 +rect 422 850 433 896 +rect 668 850 679 896 +rect 518 844 530 850 +rect 582 844 594 850 +rect -174 818 66 820 +rect -284 755 -281 801 +rect -235 755 -232 801 +rect -284 741 -232 755 +rect 16 728 66 818 +rect 781 728 827 896 +rect 16 726 827 728 +rect 16 680 433 726 +rect 668 680 827 726 +rect 16 678 827 680 +rect -284 662 -232 676 +rect -284 616 -281 662 +rect -235 616 -232 662 +rect -284 557 -232 616 +rect -144 534 -112 586 +rect -60 534 -37 586 +rect 518 556 530 562 +rect 582 556 594 562 +rect -144 528 -37 534 +rect 422 510 433 556 +rect 668 510 679 556 +rect 754 486 801 538 +rect 853 486 865 538 +rect -305 454 -206 464 +rect -305 402 -274 454 +rect -222 402 -206 454 +rect -305 394 -206 402 << via1 >> -rect 470 1233 522 1236 -rect 470 1187 473 1233 -rect 473 1187 519 1233 -rect 519 1187 522 1233 -rect 470 1184 522 1187 -rect 112 914 158 966 -rect 158 914 164 966 -rect 446 914 452 966 -rect 452 914 498 966 -rect 422 318 474 324 -rect 422 272 468 318 -rect 468 272 474 318 -rect 554 159 606 162 -rect 554 113 557 159 -rect 557 113 603 159 -rect 603 113 606 159 -rect 554 110 606 113 +rect 530 850 582 896 +rect 530 844 582 850 +rect -112 540 -66 586 +rect -66 540 -60 586 +rect -112 534 -60 540 +rect 530 556 582 562 +rect 530 510 582 556 +rect 801 535 853 538 +rect 801 489 804 535 +rect 804 489 850 535 +rect 850 489 853 535 +rect 801 486 853 489 +rect -274 451 -222 454 +rect -274 405 -271 451 +rect -271 405 -225 451 +rect -225 405 -222 451 +rect -274 402 -222 405 << metal2 >> -rect 468 1236 524 1248 -rect 468 1184 470 1236 -rect 522 1184 524 1236 -rect 468 968 524 1184 -rect 60 966 572 968 -rect 60 914 112 966 -rect 164 914 446 966 -rect 498 914 572 966 -rect 60 912 572 914 -rect 60 324 608 326 -rect 60 272 422 324 -rect 474 272 608 324 -rect 60 270 608 272 -rect 552 162 608 270 -rect 552 110 554 162 -rect 606 110 608 162 -rect 552 88 608 110 +rect -114 586 -58 948 +rect -114 534 -112 586 +rect -60 534 -58 586 +rect -114 456 -58 534 +rect -296 454 -58 456 +rect -296 402 -274 454 +rect -222 402 -58 454 +rect 528 896 584 948 +rect 528 844 530 896 +rect 582 844 584 896 +rect 528 562 584 844 +rect 528 510 530 562 +rect 582 540 584 562 +rect 582 538 865 540 +rect 582 510 801 538 +rect 528 486 801 510 +rect 853 486 865 538 +rect 528 484 865 486 +rect 528 436 584 484 +rect -296 400 -58 402 << labels >> -rlabel metal1 s 230 126 230 126 4 B -rlabel metal1 s 369 126 369 126 4 A -rlabel metal1 s 135 1187 135 1187 4 Y -rlabel metal2 s 547 940 547 940 4 VDD -rlabel metal2 s 524 298 524 298 4 GND +rlabel metal1 s -257 778 -257 778 4 B +rlabel metal1 s -257 639 -257 639 4 A +rlabel metal1 s 803 873 803 873 4 Y +rlabel metal2 s 556 461 556 461 4 VDD +rlabel metal2 s -85 484 -85 484 4 GND << properties >> -string FIXED_BBOX 0 0 620 1392 +string FIXED_BBOX -384 388 1009 1009 << end >> From 13459cb6ddbaf56187017ab6a6de592361b6ce48 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 17:35:32 -0700 Subject: [PATCH 20/61] boundary box tweaks on dec nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4722 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 280 +++++++++--------- 2 files changed, 140 insertions(+), 140 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 82a49d38a3e25d62434525b8a2b4095b7fbde61a..f4b8961a92c3ff2b59066993ac7bfb0faf25f2f2 100644 GIT binary patch literal 4248 zcmai%PiS0K6vof{GjC>+Nt$Uh(^f-lY*E30jRmbm3e{kXu|*-)nuTL+Y&UIJwop*P zmFTJ)K@mz3MGzN)Ce=s*#e({*u zWY*Zb?~Ml+zWea{L-SwUck$h&MVo5WoUN!kTi!A&#!~B9F`k;)>_lePnZjTAko?|u zx2JS4@8Vne`=LMUn5A!;k?n7h;5kp}VAMZ$#Vq;Tj2u})$*+4#2cv!)aFzIg$$6~h ztfzD^>hJx8_}9$H>}|8nM?Iy3p?_Oge|pla^*Qo_Bg?4&rl)i;?!U|BOF_mr=RLU| z>R{ZDyvZLfKjWESlnzGyy|3Xtg!;kkW7L1fQ#u&;&!M}&!VfZjOX4XV4E=Y6{Tthh z{qh9n503nU^I-pp(!r>|a|7$eZYCMuJLM@IjQVY1b#?Vm)Ubd)zK^wIFFQ&v8TE7B z$)a07^Kt#6bTIT!hxOYBnE55-2V0ys=U-7e81*-gI6v7sj{MlmBK_6zsK3m=$K_`{ z{cDuIC!U}F0)5kYTHD}FO`ua`lVS!Kk10F^;5$~lwRj&-T66Jf8%LazbGAyuAloR z{nzcE?6TWGqI59oXaCX@u7BC1u79F*FzRRD7)R2_{)y7-{OlX!Ncz}6QF@)fe=mA= z(~L}i!Sk!>DIJWiKbb}Emv9a+c>rF#@OY$3H=Qf%%b`<)+U9N-yI6iSx*h`xnXcY{Ys*>0mT}!RrS1 zf0FCv`bFvM?*Bvm>wW6{B-h`6$CLi*cx`?@FSHK&=_93sQ9tLF9dz?+Ty*mjrGrs_ z_8#^OY9_NQ?p`2D2cv%WJv-p~pP_&3{~Dzqi2FJB^aVG6o`>@nrGwG@y;)Z?nf`_A z=NV7#ggM(wMjS}x=E@QR)IvD)zec(r#z*Dp?^o%zkE01 z7g0YraveMVNl)qP-gt-nhO5;c#usEf{i1X*n!kMF+;C4E=I>$_Vp{27tv|Wy{ERPm zd`0PCt>2KB>tH6PrL}@!?1NUYMnaIH zf<=gkU?03ZRJ0FLi}sU9}&i|Y_ z=j?1;*_BGW-Dpp#a^BTk>{@QvjpToK>r3UQ_iwoSwrBUgFtO?2riqEkCnxu9oY*k2 z@2S1c4fXclyY2P69-KS2aL@RuTi<_g&n`FGU(i~)sI|VTbLB?KUE#{jl5_6nRwVjhcocEK*ovU5x92wu@T~{&NT-! zDhC68nl2x8E*dko_oQk17kp3U(OB4D{F~!XQ?hmg+9_vLzGD1i`SG`LfAvN5N$)rC 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YdBVRzke$EF;N3!0uD?xGP(h#j4;TJEa{vGU diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index 3f18a270..3cc6678d 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,162 +1,162 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694474583 +timestamp 1694478861 << nwell >> -rect 290 388 1009 1008 +rect 620 0 1339 620 << nmos >> -rect -174 728 -4 788 -rect -174 618 -4 678 +rect 156 340 326 400 +rect 156 230 326 290 << pmos >> -rect 380 758 721 818 -rect 380 588 721 648 +rect 710 370 1051 430 +rect 710 200 1051 260 << ndiff >> -rect -174 866 -4 888 -rect -174 820 -112 866 -rect -66 820 -4 866 -rect -174 788 -4 820 -rect -174 678 -4 728 -rect -174 586 -4 618 -rect -174 540 -112 586 -rect -66 540 -4 586 -rect -174 518 -4 540 +rect 156 478 326 500 +rect 156 432 218 478 +rect 264 432 326 478 +rect 156 400 326 432 +rect 156 290 326 340 +rect 156 198 326 230 +rect 156 152 218 198 +rect 264 152 326 198 +rect 156 130 326 152 << pdiff >> -rect 380 896 721 918 -rect 380 850 433 896 -rect 668 850 721 896 -rect 380 818 721 850 -rect 380 726 721 758 -rect 380 680 433 726 -rect 668 680 721 726 -rect 380 648 721 680 -rect 380 556 721 588 -rect 380 510 433 556 -rect 668 510 721 556 -rect 380 488 721 510 +rect 710 508 1051 530 +rect 710 462 763 508 +rect 997 462 1051 508 +rect 710 430 1051 462 +rect 710 338 1051 370 +rect 710 292 763 338 +rect 997 292 1051 338 +rect 710 260 1051 292 +rect 710 168 1051 200 +rect 710 122 763 168 +rect 997 122 1051 168 +rect 710 100 1051 122 << ndiffc >> -rect -112 820 -66 866 -rect -112 540 -66 586 +rect 218 432 264 478 +rect 218 152 264 198 << pdiffc >> -rect 433 850 668 896 -rect 433 680 668 726 -rect 433 510 668 556 +rect 763 462 997 508 +rect 763 292 997 338 +rect 763 122 997 168 << psubdiff >> -rect -311 451 -204 468 -rect -311 405 -271 451 -rect -225 405 -204 451 -rect -311 388 -204 405 +rect 19 63 126 80 +rect 19 17 59 63 +rect 105 17 126 63 +rect 19 0 126 17 << nsubdiff >> -rect 787 535 867 572 -rect 787 489 804 535 -rect 850 489 867 535 -rect 787 465 867 489 +rect 1117 147 1197 184 +rect 1117 101 1134 147 +rect 1180 101 1197 147 +rect 1117 77 1197 101 << psubdiffcont >> -rect -271 405 -225 451 +rect 59 17 105 63 << nsubdiffcont >> -rect 804 489 850 535 +rect 1134 101 1180 147 << polysilicon >> -rect -297 801 -214 828 -rect -297 755 -281 801 -rect -235 788 -214 801 -rect 46 788 380 818 -rect -235 755 -174 788 -rect -297 728 -174 755 -rect -4 758 380 788 -rect 721 758 771 818 -rect -4 728 86 758 -rect -297 662 -174 678 -rect -297 616 -281 662 -rect -235 618 -174 662 -rect -4 648 86 678 -rect -4 618 380 648 -rect -235 616 -214 618 -rect -297 578 -214 616 -rect 46 588 380 618 -rect 721 588 771 648 +rect 33 413 116 440 +rect 33 367 49 413 +rect 95 400 116 413 +rect 376 400 710 430 +rect 95 367 156 400 +rect 33 340 156 367 +rect 326 370 710 400 +rect 1051 370 1101 430 +rect 326 340 416 370 +rect 33 274 156 290 +rect 33 228 49 274 +rect 95 230 156 274 +rect 326 260 416 290 +rect 326 230 710 260 +rect 95 228 116 230 +rect 33 190 116 228 +rect 376 200 710 230 +rect 1051 200 1101 260 << polycontact >> -rect -281 755 -235 801 -rect -281 616 -235 662 +rect 49 367 95 413 +rect 49 228 95 274 << metal1 >> -rect -174 866 66 868 -rect -284 801 -232 853 -rect -174 820 -112 866 -rect -66 820 66 866 -rect 422 850 433 896 -rect 668 850 679 896 -rect 518 844 530 850 -rect 582 844 594 850 -rect -174 818 66 820 -rect -284 755 -281 801 -rect -235 755 -232 801 -rect -284 741 -232 755 -rect 16 728 66 818 -rect 781 728 827 896 -rect 16 726 827 728 -rect 16 680 433 726 -rect 668 680 827 726 -rect 16 678 827 680 -rect -284 662 -232 676 -rect -284 616 -281 662 -rect -235 616 -232 662 -rect -284 557 -232 616 -rect -144 534 -112 586 -rect -60 534 -37 586 -rect 518 556 530 562 -rect 582 556 594 562 -rect -144 528 -37 534 -rect 422 510 433 556 -rect 668 510 679 556 -rect 754 486 801 538 -rect 853 486 865 538 -rect -305 454 -206 464 -rect -305 402 -274 454 -rect -222 402 -206 454 -rect -305 394 -206 402 +rect 156 478 396 480 +rect 46 413 98 465 +rect 156 432 218 478 +rect 264 432 396 478 +rect 752 462 763 508 +rect 997 462 1009 508 +rect 848 456 860 462 +rect 912 456 924 462 +rect 156 430 396 432 +rect 46 367 49 413 +rect 95 367 98 413 +rect 46 353 98 367 +rect 346 340 396 430 +rect 1111 340 1157 508 +rect 346 338 1157 340 +rect 346 292 763 338 +rect 997 292 1157 338 +rect 346 290 1157 292 +rect 46 274 98 288 +rect 46 228 49 274 +rect 95 228 98 274 +rect 46 169 98 228 +rect 186 146 218 198 +rect 270 146 293 198 +rect 848 168 860 174 +rect 912 168 924 174 +rect 186 140 293 146 +rect 752 122 763 168 +rect 997 122 1009 168 +rect 1084 98 1131 150 +rect 1183 98 1195 150 +rect 25 66 124 76 +rect 25 14 56 66 +rect 108 14 124 66 +rect 25 6 124 14 << via1 >> -rect 530 850 582 896 -rect 530 844 582 850 -rect -112 540 -66 586 -rect -66 540 -60 586 -rect -112 534 -60 540 -rect 530 556 582 562 -rect 530 510 582 556 -rect 801 535 853 538 -rect 801 489 804 535 -rect 804 489 850 535 -rect 850 489 853 535 -rect 801 486 853 489 -rect -274 451 -222 454 -rect -274 405 -271 451 -rect -271 405 -225 451 -rect -225 405 -222 451 -rect -274 402 -222 405 +rect 860 462 912 508 +rect 860 456 912 462 +rect 218 152 264 198 +rect 264 152 270 198 +rect 218 146 270 152 +rect 860 168 912 174 +rect 860 122 912 168 +rect 1131 147 1183 150 +rect 1131 101 1134 147 +rect 1134 101 1180 147 +rect 1180 101 1183 147 +rect 1131 98 1183 101 +rect 56 63 108 66 +rect 56 17 59 63 +rect 59 17 105 63 +rect 105 17 108 63 +rect 56 14 108 17 << metal2 >> -rect -114 586 -58 948 -rect -114 534 -112 586 -rect -60 534 -58 586 -rect -114 456 -58 534 -rect -296 454 -58 456 -rect -296 402 -274 454 -rect -222 402 -58 454 -rect 528 896 584 948 -rect 528 844 530 896 -rect 582 844 584 896 -rect 528 562 584 844 -rect 528 510 530 562 -rect 582 540 584 562 -rect 582 538 865 540 -rect 582 510 801 538 -rect 528 486 801 510 -rect 853 486 865 538 -rect 528 484 865 486 -rect 528 436 584 484 -rect -296 400 -58 402 +rect 216 198 272 560 +rect 216 146 218 198 +rect 270 146 272 198 +rect 216 68 272 146 +rect 34 66 272 68 +rect 34 14 56 66 +rect 108 14 272 66 +rect 858 508 914 560 +rect 858 456 860 508 +rect 912 456 914 508 +rect 858 174 914 456 +rect 858 122 860 174 +rect 912 152 914 174 +rect 912 150 1195 152 +rect 912 122 1131 150 +rect 858 98 1131 122 +rect 1183 98 1195 150 +rect 858 96 1195 98 +rect 858 48 914 96 +rect 34 12 272 14 << labels >> -rlabel metal1 s -257 778 -257 778 4 B -rlabel metal1 s -257 639 -257 639 4 A -rlabel metal1 s 803 873 803 873 4 Y -rlabel metal2 s 556 461 556 461 4 VDD -rlabel metal2 s -85 484 -85 484 4 GND +rlabel metal1 s 1133 485 1133 485 4 Y +rlabel metal1 s 73 390 73 390 4 B +rlabel metal1 s 73 251 73 251 4 A +rlabel metal2 s 886 73 886 73 4 VDD +rlabel metal2 s 245 96 245 96 4 GND << properties >> -string FIXED_BBOX -384 388 1009 1009 +string FIXED_BBOX 0 0 1339 620 << end >> From 8c56478df3e69c54bf1716001a5917ad0276ce4e Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 17:48:01 -0700 Subject: [PATCH 21/61] more nand tweaks --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4404 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 23 +++++++++++++----- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index f4b8961a92c3ff2b59066993ac7bfb0faf25f2f2..1632fca729372fcc198e231af0c98f7180a577d9 100644 GIT binary patch literal 4404 zcmai%OK4qH6o%J%+;i{E%cRXsQVp>W(SdPa-MzNE+g&}px_nP}uDkr= z5wr2Ev3K8F_bq(=!PWccKihf!oux&aZq!68>Z0W>vtl^4juj)Rnaz%7W<%4s!r!fT zc~T4iF_Mqrzw%Fn{%puBJ&nN6dA2W@Q5P{D^$%Y%Oa4ZwZ+Z?anNb%p9`#$-tvg-w zOwQmMx>&dV&i9!2hS}s{&+M!jbrIuX{;gsC>2b5xr>Osi=fE<00bRs++<&Lb)13EY zycD{Kb;SM1ll&_#^L{d4HbHgU_4O-Q>uC}Fd=IrO zh@~F&bDhbeTffNlP#2+x{+Y0Td*7^i5&3cd#TM=#brE{h-+adTI@rVXldYq;hA!6m z%lr>GUsFUJt*aW3=I3~UezmrGGLGU_&;y_LqB-7hR}cLBF1a$ zZ+!0R7mK%D{UY?JpLNp5`bGMvi*7y>z`B`WFva4TgJn8Bep-0!xeUe^B zZtNd1`_b(m5qi|meUh%Y{)yQ`u74u*sGohJkNp$rqb}C@*(dtgKaoD_Vx52DZuIU3 ze!rTY=}%_VMT|$+pUk4yOPGt78!@>Tv7n34L;v>h{Mzrh&%a?Ve}gNwJBS5cgdX+t zJ*j+7f8p7F9<@UkF&_1ge2jSo`u9n|E4Y8u#Ukz>J%hY>er@79Dl#5*5qdO#!E=J= ze-rB$Sr2s)delFD-uXJnM?cyA8SjJ8#X3Lp@OOefk#V%HYCM{s_bGeK-9NE`+|)(r zQGfO>_6}<2*%z}*hzVVU9`&=&*+JL;4WfUgE*^~gd7sl4-2E3Bhq?$on!hvaYM*@C zGyMzwgf8~IKlbkb*U+mO%suXzyozh+BF4k~JHqob`kmW%V;4QSZ>fuY`>)5J??-N& z_r}AX>^pT4rMqTXdUynbTLa(^?Y0u;l#DXqj zJY4@BVgK?yn74@fANL%%iu$38eea(=e#6+Nt$Uh(^f-lY*E30jRmbm3e{kXu|*-)nuTL+Y&UIJwop*P zmFTJ)K@mz3MGzN)Ce=s*#e({*u zWY*Zb?~Ml+zWea{L-SwUck$h&MVo5WoUN!kTi!A&#!~B9F`k;)>_lePnZjTAko?|u zx2JS4@8Vne`=LMUn5A!;k?n7h;5kp}VAMZ$#Vq;Tj2u})$*+4#2cv!)aFzIg$$6~h ztfzD^>hJx8_}9$H>}|8nM?Iy3p?_Oge|pla^*Qo_Bg?4&rl)i;?!U|BOF_mr=RLU| z>R{ZDyvZLfKjWESlnzGyy|3Xtg!;kkW7L1fQ#u&;&!M}&!VfZjOX4XV4E=Y6{Tthh z{qh9n503nU^I-pp(!r>|a|7$eZYCMuJLM@IjQVY1b#?Vm)Ubd)zK^wIFFQ&v8TE7B z$)a07^Kt#6bTIT!hxOYBnE55-2V0ys=U-7e81*-gI6v7sj{MlmBK_6zsK3m=$K_`{ z{cDuIC!U}F0)5kYTHD}FO`ua`lVS!Kk10F^;5$~lwRj&-T66Jf8%LazbGAyuAloR z{nzcE?6TWGqI59oXaCX@u7BC1u79F*FzRRD7)R2_{)y7-{OlX!Ncz}6QF@)fe=mA= z(~L}i!Sk!>DIJWiKbb}Emv9a+c>rF#@OY$3H=Qf%%b`<)+U9N-yI6iSx*h`xnXcY{Ys*>0mT}!RrS1 zf0FCv`bFvM?*Bvm>wW6{B-h`6$CLi*cx`?@FSHK&=_93sQ9tLF9dz?+Ty*mjrGrs_ z_8#^OY9_NQ?p`2D2cv%WJv-p~pP_&3{~Dzqi2FJB^aVG6o`>@nrGwG@y;)Z?nf`_A z=NV7#ggM(wMjS}x=E@QR)IvD)zec(r#z*Dp?^o%zkE01 z7g0YraveMVNl)qP-gt-nhO5;c#usEf{i1X*n!kMF+;C4E=I>$_Vp{27tv|Wy{ERPm zd`0PCt>2KB>tH> rect 620 0 1339 620 << nmos >> @@ -90,11 +90,11 @@ rect 46 367 49 413 rect 95 367 98 413 rect 46 353 98 367 rect 346 340 396 430 -rect 1111 340 1157 508 -rect 346 338 1157 340 +rect 1056 340 1104 505 +rect 346 338 1104 340 rect 346 292 763 338 -rect 997 292 1157 338 -rect 346 290 1157 292 +rect 997 292 1104 338 +rect 346 290 1104 292 rect 46 274 98 288 rect 46 228 49 274 rect 95 228 98 274 @@ -152,11 +152,22 @@ rect 858 96 1195 98 rect 858 48 914 96 rect 34 12 272 14 << labels >> -rlabel metal1 s 1133 485 1133 485 4 Y rlabel metal1 s 73 390 73 390 4 B rlabel metal1 s 73 251 73 251 4 A rlabel metal2 s 886 73 886 73 4 VDD rlabel metal2 s 245 96 245 96 4 GND +rlabel metal1 s 72 228 72 228 4 A +port 1 nsew +rlabel metal1 s 72 409 72 409 4 B +port 2 nsew +rlabel metal2 s 886 72 886 72 4 vdd +port 4 nsew +rlabel metal2 s 244 314 244 314 4 gnd +port 5 nsew +rlabel metal1 1080 483 1080 483 1 Y << properties >> string FIXED_BBOX 0 0 1339 620 +string GDS_END 11704 +string GDS_FILE sram_address_control_cell.gds +string GDS_START 6968 << end >> From 416140d04a54d1000cc6586da9b80c871aab4394 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 17:51:56 -0700 Subject: [PATCH 22/61] nand dup pin --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4404 -> 88 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 10 +--------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 1632fca729372fcc198e231af0c98f7180a577d9..e0e42b65f4068bfbe6716ea4875470cf784aa612 100644 GIT binary patch delta 45 rcmdm@6rsex#=ykD%pk+a#8Az^$-vDZ$Y9LChs2hcsASB{!omOmYM2B# literal 4404 zcmai%OK4qH6o%J%+;i{E%cRXsQVp>W(SdPa-MzNE+g&}px_nP}uDkr= z5wr2Ev3K8F_bq(=!PWccKihf!oux&aZq!68>Z0W>vtl^4juj)Rnaz%7W<%4s!r!fT zc~T4iF_Mqrzw%Fn{%puBJ&nN6dA2W@Q5P{D^$%Y%Oa4ZwZ+Z?anNb%p9`#$-tvg-w zOwQmMx>&dV&i9!2hS}s{&+M!jbrIuX{;gsC>2b5xr>Osi=fE<00bRs++<&Lb)13EY zycD{Kb;SM1ll&_#^L{d4HbHgU_4O-Q>uC}Fd=IrO zh@~F&bDhbeTffNlP#2+x{+Y0Td*7^i5&3cd#TM=#brE{h-+adTI@rVXldYq;hA!6m z%lr>GUsFUJt*aW3=I3~UezmrGGLGU_&;y_LqB-7hR}cLBF1a$ zZ+!0R7mK%D{UY?JpLNp5`bGMvi*7y>z`B`WFva4TgJn8Bep-0!xeUe^B zZtNd1`_b(m5qi|meUh%Y{)yQ`u74u*sGohJkNp$rqb}C@*(dtgKaoD_Vx52DZuIU3 ze!rTY=}%_VMT|$+pUk4yOPGt78!@>Tv7n34L;v>h{Mzrh&%a?Ve}gNwJBS5cgdX+t zJ*j+7f8p7F9<@UkF&_1ge2jSo`u9n|E4Y8u#Ukz>J%hY>er@79Dl#5*5qdO#!E=J= ze-rB$Sr2s)delFD-uXJnM?cyA8SjJ8#X3Lp@OOefk#V%HYCM{s_bGeK-9NE`+|)(r zQGfO>_6}<2*%z}*hzVVU9`&=&*+JL;4WfUgE*^~gd7sl4-2E3Bhq?$on!hvaYM*@C zGyMzwgf8~IKlbkb*U+mO%suXzyozh+BF4k~JHqob`kmW%V;4QSZ>fuY`>)5J??-N& z_r}AX>^pT4rMqTXdUynbTLa(^?Y0u;l#DXqj zJY4@BVgK?yn74@fANL%%iu$38eea(=e#6> rect 620 0 1339 620 << nmos >> @@ -156,14 +156,6 @@ rlabel metal1 s 73 390 73 390 4 B rlabel metal1 s 73 251 73 251 4 A rlabel metal2 s 886 73 886 73 4 VDD rlabel metal2 s 245 96 245 96 4 GND -rlabel metal1 s 72 228 72 228 4 A -port 1 nsew -rlabel metal1 s 72 409 72 409 4 B -port 2 nsew -rlabel metal2 s 886 72 886 72 4 vdd -port 4 nsew -rlabel metal2 s 244 314 244 314 4 gnd -port 5 nsew rlabel metal1 1080 483 1080 483 1 Y << properties >> string FIXED_BBOX 0 0 1339 620 From 8ac30f4ef5fc87666ad2d17dca3c902cd2eb9e74 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 17:53:44 -0700 Subject: [PATCH 23/61] proper gds for nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 88 -> 4248 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index e0e42b65f4068bfbe6716ea4875470cf784aa612..a1b8a23560846a6c2a8ef62029638af8a41eab24 100644 GIT binary patch literal 4248 zcmai%PiP%g6vof|dGp>&USd)+Nva`ME4naXV^FI|p*7fIY*9%4lZDUP*lyaou?6uD zxDvbSMkolSh$4s!H;RI8L`1B2=3Z2Z2t^X1<6;EsXt8@_wLbM85F z@4Oi+EVaz$lGI+Yu8rEHE!p_y^}W`!`LsBCWO3(?aSih&g*k6C) zu-R1B+O_+w`&YjC;OYa*pWS`_owZe)Yc)hGnxf?$vtlf@(u(oa%oZjxv)&x8@ORUl zp47sBjO3H}ul>`ZKkJ#LrxEyB&+gY|)J2R({bLu+lD|>vo1PrPL3 zCTDOBU2Ix^`2*&?VK#HfGdpWWUBq~pe_L38dd#fzDeAxOIkJvkKo>C{_ut|2w3j^@ zFNH2*9dSSMB!9a6BG=9QBJ`-g{1S5yp#GDd*+-}!x`^?(e-YjN&1^RDWV{l(i1E;W zOW41$UDzj&VLtYsIPwqfKXeg#)Ze>?bz(P{$2}Q`x`^?p-&Qs@Hm+c;r$zMhJ=C%y zR(jOWbtbEB{UX;xU4$O`=fnE#eY5rjTL659L2528~v>*=ilUq&fgNJ;`K9r{<>Sg$T-wR=#BX^ zo;RMqnvA2kB=o4Cea`-H`9=Dvi_k;=t>OL8_o8;3z1DWm?i27r7cn07k7Mt4N6l{d zHsEEmN*71t{)w-gZ}MC~_$pm&@NYTmd^f%n5WY$m8~lc|-rj*T^rL5|hyFtsG2U2z z>vLDXSiJ4(7okV}tdl<0FVaU{Z1S^C`dGh6A9bSB|heWH*36X~NaHu%gqyDM$&Q~HI{bctSybnSboBYhf-wFCe#?iX!@o0YDr)1J6S@dJ>Sv#`eXjqTME@#X+!y!rKBv#S`!6yMbrE_rf4SglpLxnN z{R{nsE)Kmv4(|Wg(5rdOJ?5Fbifia1#>4#E!}Bxoz1w$_7d*Ldsf$DVZ@{1LL2jJ) z)+3(mJ9QD`jrrL(<`*;e9r?wf{te`xo~iqGvnTsTT^#D)fIpctH1|MH!fw~G27_Z+#3`k{+M@1FyH!`ZQioL^)->LT=L{_6RE4gJGCNNX}LbrE`_ zKlv5UZ|=XEjH9?D^hUoSAM=ZhQ~N4H5B+#J`0ro1s=wjyUyAxR#%1O2!HMr@?EmSM z!~A|u@ZHfqXT{cH&;QKIFLT!J!CAN$KGr0@n-H(FwRmzFucKkkfqD6NRZlQ)?}4Ft V18Xa1afV)G)@SNy_>s(W`wtO1t2+Py delta 16 XcmbQC7%@Sf*_c6MqLMK)3kw4PA=Co^ From 0aa9c47f89353b7267c4b65b3a8797b51b9d6092 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 18:01:29 -0700 Subject: [PATCH 24/61] more nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 13 ++++++------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index a1b8a23560846a6c2a8ef62029638af8a41eab24..9454cf3b5745e98feb5a539a8a7b403197e164fd 100644 GIT binary patch delta 142 zcmbQCI73m1fsKKQftf*uk%^(2fs=uoL5P6?NFvw@6P0WQF$6ajY~fN8> rect 620 0 1339 620 << nmos >> @@ -90,11 +90,11 @@ rect 46 367 49 413 rect 95 367 98 413 rect 46 353 98 367 rect 346 340 396 430 -rect 1056 340 1104 505 -rect 346 338 1104 340 +rect 1077 340 1125 503 +rect 346 338 1125 340 rect 346 292 763 338 -rect 997 292 1104 338 -rect 346 290 1104 292 +rect 997 292 1125 338 +rect 346 290 1125 292 rect 46 274 98 288 rect 46 228 49 274 rect 95 228 98 274 @@ -156,10 +156,9 @@ rlabel metal1 s 73 390 73 390 4 B rlabel metal1 s 73 251 73 251 4 A rlabel metal2 s 886 73 886 73 4 VDD rlabel metal2 s 245 96 245 96 4 GND -rlabel metal1 1080 483 1080 483 1 Y +rlabel metal1 1101 479 1101 479 1 Y << properties >> string FIXED_BBOX 0 0 1339 620 string GDS_END 11704 -string GDS_FILE sram_address_control_cell.gds string GDS_START 6968 << end >> From 9ac94d17440ca1916ec4e135675decfab692beeb Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 18:12:12 -0700 Subject: [PATCH 25/61] even more nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 12 ++++++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 9454cf3b5745e98feb5a539a8a7b403197e164fd..80935f9b50c273a7a7bb9d3da3a0094d2d19e8ff 100644 GIT binary patch delta 170 zcmbQCI73m1fsKKQftf*uk%^(2fs=uoK?sPYkl3mdmF)S^g$iuA#P2bHf%v_R+uk!O zPGDeQ@?&6-U_{U?77PrcKye7Y`503ihmy#D1_rhz3=Cq-2%7UU0|Q7LLQi(%R^tLm Ov#tUu+g!%2#0mhgz8T~I delta 170 zcmbQCI73m1fsKKQftf*uk%^(2fs=uoL5P6?NFvw@6P4`w(S-_ZxTMs93V}dMedD(G zjEZ|17?}JR7{p5vH1iq;22r3mgx-9NDUL%)l#_vhZ3$5PCxYg@4CDjFA@pQ7ZZ$5D OH0vsmvdv}ON~{2(?;CIc diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index d3af1866..9bebf2bb 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,9 +1,9 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694480451 +timestamp 1694481086 << nwell >> -rect 620 0 1339 620 +rect 620 0 1222 620 << nmos >> rect 156 340 326 400 rect 156 230 326 290 @@ -90,11 +90,11 @@ rect 46 367 49 413 rect 95 367 98 413 rect 46 353 98 367 rect 346 340 396 430 -rect 1077 340 1125 503 -rect 346 338 1125 340 +rect 1075 340 1127 503 +rect 346 338 1127 340 rect 346 292 763 338 -rect 997 292 1125 338 -rect 346 290 1125 292 +rect 997 292 1127 338 +rect 346 290 1127 292 rect 46 274 98 288 rect 46 228 49 274 rect 95 228 98 274 From dba75fc57c41b1463d3d0892b2c577409bf62010 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 18:31:22 -0700 Subject: [PATCH 26/61] boundary and alignment of nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 282 +++++++++--------- 2 files changed, 140 insertions(+), 142 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 80935f9b50c273a7a7bb9d3da3a0094d2d19e8ff..f597caccfdde516fc23b4e32d5f9812659553b39 100644 GIT binary patch literal 4248 zcmaKvPiS0K6vof{GjC>^NzA03Ne0t)Op6KzY+BUlB2W!>ky^SawYqR9jeizR5YcX= zQpG=1DwMhr6&0Zf1wlbY!IcYXL7{Gnh;-pXK|~Z>h=}p~-hJQPH-Y;K<=1}ieD~aQ z&V7HzGK=G5HXFtDU#w|kHf7swuKaJ?5oeD-wy?No?Zh*KeW&&f2J6SySN9GU2CI*r zFx!^YmiC{$Yvt)|6dTdPm}TR!bu62R&1`-$F>B3kY-}u& zW@AUpdaI)JoN3!k{%+Zyw9KNf%*e*SNbrcKbTH^2zYhPr8QHvml3($Z4hH=;aQn0Y zD!ObIpAw~4@4xdM;=eE>WS4F9sQ3 zU-smFsDoiY@o_*mG3PHzZ-o8zW6q!R9prx={}f4e)cy(%{k#$-kj3=BmSGp^G^@J`yuuWHqM&Wc6mw%%lSwA6Tcz;J~Ohp)9i-J zp3=dfe-h7b#*y^5adt%MRsN|roS&p`>(id}7uSRN?H`<%C(wV8&%WrIr*tsrXWi+a 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z7okV})9cRH%RJjZ<9QIeSm$RR{!h>^avfS%H6G2+eaa5F{SzA(-TsNtqyFqeoE_B8 zYhTQ+ASQGXdeqN8XZv0M?-2bfb#Z^(&wWl`ar-Ya4s{WFG=F#A)jo6BGrfWTGw9;b z^W)(8e+#{u!`u^|$(#5MUBq~pe`|RCO#JB1-Q*=to?GhT(D@ti=X;SG*L&khPxhU< zi1FI|>>Klo8T*d>;!ytv^7m${zTM-=zEKy4`ZwTDHlSBr`>bd36kA#$xaP%*wBF)}Fyx*b5(P67Nlj*V> -rect 620 0 1222 620 +rect 620 -40 1300 580 << nmos >> -rect 156 340 326 400 -rect 156 230 326 290 +rect 156 300 326 360 +rect 156 190 326 250 << pmos >> -rect 710 370 1051 430 -rect 710 200 1051 260 +rect 710 330 1051 390 +rect 710 160 1051 220 << ndiff >> -rect 156 478 326 500 -rect 156 432 218 478 -rect 264 432 326 478 -rect 156 400 326 432 -rect 156 290 326 340 -rect 156 198 326 230 -rect 156 152 218 198 -rect 264 152 326 198 -rect 156 130 326 152 +rect 156 438 326 460 +rect 156 392 218 438 +rect 264 392 326 438 +rect 156 360 326 392 +rect 156 250 326 300 +rect 156 158 326 190 +rect 156 112 218 158 +rect 264 112 326 158 +rect 156 90 326 112 << pdiff >> -rect 710 508 1051 530 -rect 710 462 763 508 -rect 997 462 1051 508 -rect 710 430 1051 462 -rect 710 338 1051 370 -rect 710 292 763 338 -rect 997 292 1051 338 -rect 710 260 1051 292 -rect 710 168 1051 200 -rect 710 122 763 168 -rect 997 122 1051 168 -rect 710 100 1051 122 +rect 710 468 1051 490 +rect 710 422 763 468 +rect 997 422 1051 468 +rect 710 390 1051 422 +rect 710 298 1051 330 +rect 710 252 763 298 +rect 997 252 1051 298 +rect 710 220 1051 252 +rect 710 128 1051 160 +rect 710 82 763 128 +rect 997 82 1051 128 +rect 710 60 1051 82 << ndiffc >> -rect 218 432 264 478 -rect 218 152 264 198 +rect 218 392 264 438 +rect 218 112 264 158 << pdiffc >> -rect 763 462 997 508 -rect 763 292 997 338 -rect 763 122 997 168 +rect 763 422 997 468 +rect 763 252 997 298 +rect 763 82 997 128 << psubdiff >> -rect 19 63 126 80 -rect 19 17 59 63 -rect 105 17 126 63 -rect 19 0 126 17 +rect 19 23 126 40 +rect 19 -23 59 23 +rect 105 -23 126 23 +rect 19 -40 126 -23 << nsubdiff >> -rect 1117 147 1197 184 -rect 1117 101 1134 147 -rect 1180 101 1197 147 -rect 1117 77 1197 101 +rect 1117 107 1197 144 +rect 1117 61 1134 107 +rect 1180 61 1197 107 +rect 1117 37 1197 61 << psubdiffcont >> -rect 59 17 105 63 +rect 59 -23 105 23 << nsubdiffcont >> -rect 1134 101 1180 147 +rect 1134 61 1180 107 << polysilicon >> -rect 33 413 116 440 -rect 33 367 49 413 -rect 95 400 116 413 -rect 376 400 710 430 -rect 95 367 156 400 -rect 33 340 156 367 -rect 326 370 710 400 -rect 1051 370 1101 430 -rect 326 340 416 370 -rect 33 274 156 290 -rect 33 228 49 274 -rect 95 230 156 274 -rect 326 260 416 290 -rect 326 230 710 260 -rect 95 228 116 230 -rect 33 190 116 228 -rect 376 200 710 230 -rect 1051 200 1101 260 +rect 33 373 116 400 +rect 33 327 49 373 +rect 95 360 116 373 +rect 376 360 710 390 +rect 95 327 156 360 +rect 33 300 156 327 +rect 326 330 710 360 +rect 1051 330 1101 390 +rect 326 300 416 330 +rect 33 234 156 250 +rect 33 188 49 234 +rect 95 190 156 234 +rect 326 220 416 250 +rect 326 190 710 220 +rect 95 188 116 190 +rect 33 150 116 188 +rect 376 160 710 190 +rect 1051 160 1101 220 << polycontact >> -rect 49 367 95 413 -rect 49 228 95 274 +rect 49 327 95 373 +rect 49 188 95 234 << metal1 >> -rect 156 478 396 480 -rect 46 413 98 465 -rect 156 432 218 478 -rect 264 432 396 478 -rect 752 462 763 508 -rect 997 462 1009 508 -rect 848 456 860 462 -rect 912 456 924 462 -rect 156 430 396 432 -rect 46 367 49 413 -rect 95 367 98 413 -rect 46 353 98 367 -rect 346 340 396 430 -rect 1075 340 1127 503 -rect 346 338 1127 340 -rect 346 292 763 338 -rect 997 292 1127 338 -rect 346 290 1127 292 -rect 46 274 98 288 -rect 46 228 49 274 -rect 95 228 98 274 -rect 46 169 98 228 -rect 186 146 218 198 -rect 270 146 293 198 -rect 848 168 860 174 -rect 912 168 924 174 -rect 186 140 293 146 -rect 752 122 763 168 -rect 997 122 1009 168 -rect 1084 98 1131 150 -rect 1183 98 1195 150 -rect 25 66 124 76 -rect 25 14 56 66 -rect 108 14 124 66 -rect 25 6 124 14 +rect 156 438 396 440 +rect 46 373 98 425 +rect 156 392 218 438 +rect 264 392 396 438 +rect 752 422 763 468 +rect 997 422 1009 468 +rect 848 416 860 422 +rect 912 416 924 422 +rect 156 390 396 392 +rect 46 327 49 373 +rect 95 327 98 373 +rect 46 313 98 327 +rect 346 300 396 390 +rect 1075 300 1127 463 +rect 346 298 1127 300 +rect 346 252 763 298 +rect 997 252 1127 298 +rect 346 250 1127 252 +rect 46 234 98 248 +rect 46 188 49 234 +rect 95 188 98 234 +rect 46 129 98 188 +rect 186 106 218 158 +rect 270 106 293 158 +rect 848 128 860 134 +rect 912 128 924 134 +rect 186 100 293 106 +rect 752 82 763 128 +rect 997 82 1009 128 +rect 1084 58 1131 110 +rect 1183 58 1195 110 +rect 25 26 124 36 +rect 25 -26 56 26 +rect 108 -26 124 26 +rect 25 -34 124 -26 << via1 >> -rect 860 462 912 508 -rect 860 456 912 462 -rect 218 152 264 198 -rect 264 152 270 198 -rect 218 146 270 152 -rect 860 168 912 174 -rect 860 122 912 168 -rect 1131 147 1183 150 -rect 1131 101 1134 147 -rect 1134 101 1180 147 -rect 1180 101 1183 147 -rect 1131 98 1183 101 -rect 56 63 108 66 -rect 56 17 59 63 -rect 59 17 105 63 -rect 105 17 108 63 -rect 56 14 108 17 +rect 860 422 912 468 +rect 860 416 912 422 +rect 218 112 264 158 +rect 264 112 270 158 +rect 218 106 270 112 +rect 860 128 912 134 +rect 860 82 912 128 +rect 1131 107 1183 110 +rect 1131 61 1134 107 +rect 1134 61 1180 107 +rect 1180 61 1183 107 +rect 1131 58 1183 61 +rect 56 23 108 26 +rect 56 -23 59 23 +rect 59 -23 105 23 +rect 105 -23 108 23 +rect 56 -26 108 -23 << metal2 >> -rect 216 198 272 560 -rect 216 146 218 198 -rect 270 146 272 198 -rect 216 68 272 146 -rect 34 66 272 68 -rect 34 14 56 66 -rect 108 14 272 66 -rect 858 508 914 560 -rect 858 456 860 508 -rect 912 456 914 508 -rect 858 174 914 456 -rect 858 122 860 174 -rect 912 152 914 174 -rect 912 150 1195 152 -rect 912 122 1131 150 -rect 858 98 1131 122 -rect 1183 98 1195 150 -rect 858 96 1195 98 -rect 858 48 914 96 -rect 34 12 272 14 +rect 216 158 272 520 +rect 216 106 218 158 +rect 270 106 272 158 +rect 216 28 272 106 +rect 34 26 272 28 +rect 34 -26 56 26 +rect 108 -26 272 26 +rect 858 468 914 520 +rect 858 416 860 468 +rect 912 416 914 468 +rect 858 134 914 416 +rect 858 82 860 134 +rect 912 112 914 134 +rect 912 110 1195 112 +rect 912 82 1131 110 +rect 858 58 1131 82 +rect 1183 58 1195 110 +rect 858 56 1195 58 +rect 858 8 914 56 +rect 34 -28 272 -26 << labels >> -rlabel metal1 s 73 390 73 390 4 B -rlabel metal1 s 73 251 73 251 4 A -rlabel metal2 s 886 73 886 73 4 VDD -rlabel metal2 s 245 96 245 96 4 GND -rlabel metal1 1101 479 1101 479 1 Y +rlabel metal1 s 73 350 73 350 4 B +rlabel metal1 s 73 211 73 211 4 A +rlabel metal1 s 1101 439 1101 439 4 Y +rlabel metal2 s 886 33 886 33 4 VDD +rlabel metal2 s 245 56 245 56 4 GND << properties >> -string FIXED_BBOX 0 0 1339 620 -string GDS_END 11704 -string GDS_START 6968 +string FIXED_BBOX 0 0 1300 522 << end >> From 07fa78e00c82cd76b271c27fcf1d98bbb45674bd Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 18:52:40 -0700 Subject: [PATCH 27/61] boundary shift for implant spacing --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 280 +++++++++--------- 2 files changed, 140 insertions(+), 140 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index f597caccfdde516fc23b4e32d5f9812659553b39..51937dedbb672789438659e85085a07cdb0fb86c 100644 GIT binary patch literal 4248 zcmaKvTZkM*6o$`K_w>wUcjL~+na#?YOyVj&1k7f=BqGu1E`mlu2=RuDlGT_87Zoo- zQG%!thzJpasAxb$eDFaKF9<#u5PeWYPy~HZ5YY!ODEK0*|6kSrR?k9pVEHD0pTADk zIn~|OR+w|Q*lfeKezA^?*_18VboIAwamC?#=6CPB@6f};g+~^K!# zGCMnK?%j9%vg<#6^UpntA6#_$<=YO}Y_n#xqHeUjZB|S;>shhUnc0rX%xwIU)z#JA zq}kX3vzaGE>7IGlO#Xh=pPg^k_{5BC|Az#RMoI^h{)vC#-(f~}PGZTYBc+2$za0(p zw4+$jXJ+nsQF{ISd%q$6Lo?ESWj6g-q;#;Fe^6b&d&aEwJ3L_L75tu#ln$o-SB88J zWPIz6NX~~knD!%YV>@C%#xuVt9ZdRrZ^8d8)(>X)n{7TPQaYISUx)h5zz;H>eo;DD z^>3}#Z{lX`m#5KxaKkQ)b5*2tFzv_2beF>qGQNj7h|_5SR=(vNt~pW~6z!P@)|_Z{cY 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156 112 218 158 -rect 264 112 326 158 -rect 156 90 326 112 +rect 161 438 331 460 +rect 161 392 223 438 +rect 269 392 331 438 +rect 161 360 331 392 +rect 161 250 331 300 +rect 161 158 331 190 +rect 161 112 223 158 +rect 269 112 331 158 +rect 161 90 331 112 << pdiff >> -rect 710 468 1051 490 -rect 710 422 763 468 -rect 997 422 1051 468 -rect 710 390 1051 422 -rect 710 298 1051 330 -rect 710 252 763 298 -rect 997 252 1051 298 -rect 710 220 1051 252 -rect 710 128 1051 160 -rect 710 82 763 128 -rect 997 82 1051 128 -rect 710 60 1051 82 +rect 715 468 1056 490 +rect 715 422 768 468 +rect 1002 422 1056 468 +rect 715 390 1056 422 +rect 715 298 1056 330 +rect 715 252 768 298 +rect 1002 252 1056 298 +rect 715 220 1056 252 +rect 715 128 1056 160 +rect 715 82 768 128 +rect 1002 82 1056 128 +rect 715 60 1056 82 << ndiffc >> -rect 218 392 264 438 -rect 218 112 264 158 +rect 223 392 269 438 +rect 223 112 269 158 << pdiffc >> -rect 763 422 997 468 -rect 763 252 997 298 -rect 763 82 997 128 +rect 768 422 1002 468 +rect 768 252 1002 298 +rect 768 82 1002 128 << psubdiff >> -rect 19 23 126 40 -rect 19 -23 59 23 -rect 105 -23 126 23 -rect 19 -40 126 -23 +rect 24 23 131 40 +rect 24 -23 64 23 +rect 110 -23 131 23 +rect 24 -40 131 -23 << nsubdiff >> -rect 1117 107 1197 144 -rect 1117 61 1134 107 -rect 1180 61 1197 107 -rect 1117 37 1197 61 +rect 1122 107 1202 144 +rect 1122 61 1139 107 +rect 1185 61 1202 107 +rect 1122 37 1202 61 << psubdiffcont >> -rect 59 -23 105 23 +rect 64 -23 110 23 << nsubdiffcont >> -rect 1134 61 1180 107 +rect 1139 61 1185 107 << polysilicon >> -rect 33 373 116 400 -rect 33 327 49 373 -rect 95 360 116 373 -rect 376 360 710 390 -rect 95 327 156 360 -rect 33 300 156 327 -rect 326 330 710 360 -rect 1051 330 1101 390 -rect 326 300 416 330 -rect 33 234 156 250 -rect 33 188 49 234 -rect 95 190 156 234 -rect 326 220 416 250 -rect 326 190 710 220 -rect 95 188 116 190 -rect 33 150 116 188 -rect 376 160 710 190 -rect 1051 160 1101 220 +rect 38 373 121 400 +rect 38 327 54 373 +rect 100 360 121 373 +rect 381 360 715 390 +rect 100 327 161 360 +rect 38 300 161 327 +rect 331 330 715 360 +rect 1056 330 1106 390 +rect 331 300 421 330 +rect 38 234 161 250 +rect 38 188 54 234 +rect 100 190 161 234 +rect 331 220 421 250 +rect 331 190 715 220 +rect 100 188 121 190 +rect 38 150 121 188 +rect 381 160 715 190 +rect 1056 160 1106 220 << polycontact >> -rect 49 327 95 373 -rect 49 188 95 234 +rect 54 327 100 373 +rect 54 188 100 234 << metal1 >> -rect 156 438 396 440 -rect 46 373 98 425 -rect 156 392 218 438 -rect 264 392 396 438 -rect 752 422 763 468 -rect 997 422 1009 468 -rect 848 416 860 422 -rect 912 416 924 422 -rect 156 390 396 392 -rect 46 327 49 373 -rect 95 327 98 373 -rect 46 313 98 327 -rect 346 300 396 390 -rect 1075 300 1127 463 -rect 346 298 1127 300 -rect 346 252 763 298 -rect 997 252 1127 298 -rect 346 250 1127 252 -rect 46 234 98 248 -rect 46 188 49 234 -rect 95 188 98 234 -rect 46 129 98 188 -rect 186 106 218 158 -rect 270 106 293 158 -rect 848 128 860 134 -rect 912 128 924 134 -rect 186 100 293 106 -rect 752 82 763 128 -rect 997 82 1009 128 -rect 1084 58 1131 110 -rect 1183 58 1195 110 -rect 25 26 124 36 -rect 25 -26 56 26 -rect 108 -26 124 26 -rect 25 -34 124 -26 +rect 161 438 401 440 +rect 51 373 103 425 +rect 161 392 223 438 +rect 269 392 401 438 +rect 757 422 768 468 +rect 1002 422 1014 468 +rect 853 416 865 422 +rect 917 416 929 422 +rect 161 390 401 392 +rect 51 327 54 373 +rect 100 327 103 373 +rect 51 313 103 327 +rect 351 300 401 390 +rect 1080 300 1132 463 +rect 351 298 1132 300 +rect 351 252 768 298 +rect 1002 252 1132 298 +rect 351 250 1132 252 +rect 51 234 103 248 +rect 51 188 54 234 +rect 100 188 103 234 +rect 51 129 103 188 +rect 191 106 223 158 +rect 275 106 298 158 +rect 853 128 865 134 +rect 917 128 929 134 +rect 191 100 298 106 +rect 757 82 768 128 +rect 1002 82 1014 128 +rect 1089 58 1136 110 +rect 1188 58 1200 110 +rect 30 26 129 36 +rect 30 -26 61 26 +rect 113 -26 129 26 +rect 30 -34 129 -26 << via1 >> -rect 860 422 912 468 -rect 860 416 912 422 -rect 218 112 264 158 -rect 264 112 270 158 -rect 218 106 270 112 -rect 860 128 912 134 -rect 860 82 912 128 -rect 1131 107 1183 110 -rect 1131 61 1134 107 -rect 1134 61 1180 107 -rect 1180 61 1183 107 -rect 1131 58 1183 61 -rect 56 23 108 26 -rect 56 -23 59 23 -rect 59 -23 105 23 -rect 105 -23 108 23 -rect 56 -26 108 -23 +rect 865 422 917 468 +rect 865 416 917 422 +rect 223 112 269 158 +rect 269 112 275 158 +rect 223 106 275 112 +rect 865 128 917 134 +rect 865 82 917 128 +rect 1136 107 1188 110 +rect 1136 61 1139 107 +rect 1139 61 1185 107 +rect 1185 61 1188 107 +rect 1136 58 1188 61 +rect 61 23 113 26 +rect 61 -23 64 23 +rect 64 -23 110 23 +rect 110 -23 113 23 +rect 61 -26 113 -23 << metal2 >> -rect 216 158 272 520 -rect 216 106 218 158 -rect 270 106 272 158 -rect 216 28 272 106 -rect 34 26 272 28 -rect 34 -26 56 26 -rect 108 -26 272 26 -rect 858 468 914 520 -rect 858 416 860 468 -rect 912 416 914 468 -rect 858 134 914 416 -rect 858 82 860 134 -rect 912 112 914 134 -rect 912 110 1195 112 -rect 912 82 1131 110 -rect 858 58 1131 82 -rect 1183 58 1195 110 -rect 858 56 1195 58 -rect 858 8 914 56 -rect 34 -28 272 -26 +rect 221 158 277 520 +rect 221 106 223 158 +rect 275 106 277 158 +rect 221 28 277 106 +rect 39 26 277 28 +rect 39 -26 61 26 +rect 113 -26 277 26 +rect 863 468 919 520 +rect 863 416 865 468 +rect 917 416 919 468 +rect 863 134 919 416 +rect 863 82 865 134 +rect 917 112 919 134 +rect 917 110 1200 112 +rect 917 82 1136 110 +rect 863 58 1136 82 +rect 1188 58 1200 110 +rect 863 56 1200 58 +rect 863 8 919 56 +rect 39 -28 277 -26 << labels >> -rlabel metal1 s 73 350 73 350 4 B -rlabel metal1 s 73 211 73 211 4 A -rlabel metal1 s 1101 439 1101 439 4 Y -rlabel metal2 s 886 33 886 33 4 VDD -rlabel metal2 s 245 56 245 56 4 GND +rlabel metal1 s 78 350 78 350 4 B +rlabel metal1 s 78 211 78 211 4 A +rlabel metal1 s 1106 439 1106 439 4 Y +rlabel metal2 s 891 33 891 33 4 VDD +rlabel metal2 s 250 56 250 56 4 GND << properties >> -string FIXED_BBOX 0 0 1300 522 +string FIXED_BBOX 0 0 1305 522 << end >> From ea703d124f1003e3b1fb6c3782efcbc448961cf9 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 19:05:52 -0700 Subject: [PATCH 28/61] switched input pins on nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 6 +++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 51937dedbb672789438659e85085a07cdb0fb86c..cfaea5382c5b0b6207c5f7bd2078dda07b6a42b4 100644 GIT binary patch literal 4248 zcmaKvO^6&-6oqfSs;;ii%p}t@c28Qyq!ULG446rxCL+=31VN(^2oV)&C8N=WgNi@F z5Q$=hfIko+h>8Y8#DxnX_=DiWfat;?fs)&9-udmDA2{&nVC!RB2ZN=%mln4S<_C-S z956dCZtUE3{K}g?d;5ebu#*=(aGT3Qz^$;{FTXB|sdJ2Trf8Jmq?zP!A= z-K=*+G#lGTUCi~QZ6<%W?2j)pi#|o*$33%u&8UkQ5Bewmfo~I*ddjnP!i>6z@u1%h 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zIn~|OR+w|Q*lfeKezA^?*_18VboIAwamC?#=6CPB@6f};g+~^K!# zGCMnK?%j9%vg<#6^UpntA6#_$<=YO}Y_n#xqHeUjZB|S;>shhUnc0rX%xwIU)z#JA zq}kX3vzaGE>7IGlO#Xh=pPg^k_{5BC|Az#RMoI^h{)vC#-(f~}PGZTYBc+2$za0(p zw4+$jXJ+nsQF{ISd%q$6Lo?ESWj6g-q;#;Fe^6b&d&aEwJ3L_L75tu#ln$o-SB88J zWPIz6NX~~knD!%YV>@C%#xuVt9ZdRrZ^8d8)(>X)n{7TPQaYISUx)h5zz;H>eo;DD z^>3}#Z{lX`m#5KxaKkQ)b5*2tFzv_2beF>qGQNj7h|_5SR=(vNt~pW~6z!P@)|_Z{cY zc-CK(4krCA)IS@9I@71Tp3(;+{%zI%=Xb*UHs%brkDE2Gh?EXi^N;w?Y9js`GqST4 z{4r8GnDkG6AN(Z!-S;EuFRv&4Q||;nN&lwjBIz%$C;g30*f00unE|#I!9OCUgGoQv zo&Ocq-~1x1Uz83e{ahd8Ncy;bQF@)9>th^AAJ;ERuk&-=8N6f;FV`i1=&bTH|k#CyMunt5WJDa?mHPw9iSzd+yloF_S7 z&R>+i?)g7bzuxBHCp%;4<7_1T<@MzJnV0Vi&4YgWNahY56t?={dJ^tFzILA-LX)Ahx)PZYm|O0?PuQ`c-N5}hy53&gUS58CHQfEB;5tL ze{cpArLQ|bj`Yt?;r=*?`klhxyYRA>p3*&i{&BPk-yiVz9iqnh{lT+h@vRjz#nos4 z9$HZqo9-tH9dbMIB{`_{V z5>Fb^cYGKr9ZdQ;K08CQ)66eQU)Qmb{QaGwW2EoY#gXh-c|DoGF^`Tsi81EUgQwud z+aplAXVpJftzUi<;!j}x;D!sap2__FO@p<`>u=y`qjCI>hmVvF*7^;3>1RCii_$^wFZVLmA9sBBFxLBqwP%Whi+E`z m> rect 625 -40 1305 580 << nmos >> @@ -152,11 +152,11 @@ rect 863 56 1200 58 rect 863 8 919 56 rect 39 -28 277 -26 << labels >> -rlabel metal1 s 78 350 78 350 4 B -rlabel metal1 s 78 211 78 211 4 A rlabel metal1 s 1106 439 1106 439 4 Y rlabel metal2 s 891 33 891 33 4 VDD rlabel metal2 s 250 56 250 56 4 GND +rlabel polycontact 77 211 77 211 1 B +rlabel polycontact 77 350 77 350 1 A << properties >> string FIXED_BBOX 0 0 1305 522 << end >> From e3b51360f31b820d6d4c8667e83d382e8c823f94 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 21:12:59 -0700 Subject: [PATCH 29/61] extend nwell on nand --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 8 ++++---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index cfaea5382c5b0b6207c5f7bd2078dda07b6a42b4..2c0f894d96729f783b7accb98b59897a82b79703 100644 GIT binary patch literal 4248 zcmai%ONbm*6oyaTs;=(N%*5%5-AT)sbmAy30%j5)8Ifpo20^1BNPHo!WHe^spyDGa zN)#0WQ6WMQ6%B}p3l~E0f#AY`=t2>}Am~O>L>E3#a3hTWf2;nv)q}ST3}5H3^WSsN zIk&5-EjQnE)z7xk<@@iP-MQ`VeGd$GJh)>xT)KT}arYP>sHHJX8DA}F7ma`%(hOZX5$wuFE8&T z&BlH)>pv<=_slwG^7pF#^lY=_BQvt~4-z~SC>@OYC;oe9lE`}dud>4BVrGrtwE#iF4poT^KeT%hT6Qz4b z{oJ=5DfZ8N+`lLttok=r>$eXvGkh^UId9Hil-`Q_oA(xe&sUKDMf_iczr0?XKfkZc zk9hAdDIKi!H_$ikpYg4^K^6Ac!k)p_VY9|1fzrWh{t^Fa4a8qzMz%MB z-vvqsqyEWn3O`AI=iNa1%j;49)Z2xhq<`Hrf%KQxqyA(a&dXi6XMoLl@V7weVARjL zvpRi_*cUpY<`0q>uHB((C-Jk8vb@tY4H~=V#q1ykrJ1>ldYi(f#w>I6S+_ zw1eC@KcaLn>SzCwSBw6+M~eQ5(!r>oePbL+ANwatuk*8Sj3en||3v9^{vOZFg=VCi z!t-koC>@OMKUu*2{V3L0Fta6iH;d9etNtz3@2@T6{GJI9*t!P(G*CJi_4B=n_iO+D z^a4JA1%FBDVAQ|%Q^fBwBil3R-{*nS!Ki=oP599>PpmVA{m|zreGvEOm^<(DB=^hx zi_%x!|3~`Q-B9?+_88_k9Y}w9J-UD9Sy2Gp`!l|{bS!(DE&~}&$%af){$I?^B1Lq(fr*7`0@Tox^wXT zxhGKis`tl{`PngiKlY-3$MAOoUiQ*cx~I=Sjxpi)2mC#UsB!-O;B&I|yygA;CJX>K zu8mC-lE1gDm>B6Nc77lyR$h8sv&NBnjY>)($xP8RFXPhaDJbkAsh|D-|f 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zi&^#jRs6{v$c^j0G4N#Hsf!q|&Ck9uzv$R^ zp2S?fhvh`yo<^*BG1trW&z1X^?8Q7he>U#-Ty+W74_zF2{;c@z4B|gRzgWbvGh(g> z^XK<@thN0Y)-WXVQWv4u`XgNH`S}}?aTJ%tc&*=%kNHK$8~SoWFZ*$G@bABH<$t{+ zo_z1%pNOxye;iJ{KjZv&9kg-2Kl8acd&$yXdRuiCy6k7Q4`TjXmi5y83;1CwN2|=^ n9SqfD-VL{m%&TOLo4eB2 diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index 9c70eec2..c2b90762 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,9 +1,9 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694484283 +timestamp 1694491938 << nwell >> -rect 625 -40 1305 580 +rect 625 -40 1305 610 << nmos >> rect 161 300 331 360 rect 161 190 331 250 @@ -153,10 +153,10 @@ rect 863 8 919 56 rect 39 -28 277 -26 << labels >> rlabel metal1 s 1106 439 1106 439 4 Y +rlabel metal1 s 77 211 77 211 4 B +rlabel metal1 s 77 350 77 350 4 A rlabel metal2 s 891 33 891 33 4 VDD rlabel metal2 s 250 56 250 56 4 GND -rlabel polycontact 77 211 77 211 1 B -rlabel polycontact 77 350 77 350 1 A << properties >> string FIXED_BBOX 0 0 1305 522 << end >> From 23611f8fac6564e7bef3175e755f12fb3f6e8825 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 21:16:24 -0700 Subject: [PATCH 30/61] little more nwell --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 2c0f894d96729f783b7accb98b59897a82b79703..60c97a59a35e20d37b42bf401f2cadeb17311f36 100644 GIT binary patch delta 76 zcmbQCI73m1fsKKQDS|> -rect 625 -40 1305 610 +rect 625 -40 1305 640 << nmos >> rect 161 300 331 360 rect 161 190 331 250 From d940c0e03d8a32b14ccfe145561ae943e5324ccf Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 21:25:03 -0700 Subject: [PATCH 31/61] little more boundary --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 280 +++++++++--------- 2 files changed, 140 insertions(+), 140 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 60c97a59a35e20d37b42bf401f2cadeb17311f36..552a6a2b223c3326cb30ea842782807869bfc3d9 100644 GIT binary patch literal 4248 zcmai%ONbm*6oyaTuCDIRJd*BAIx{h5#u!9QFpoh^TqHyXTqFvDM$IBknD{_(zz}sI zm_d96B82Ed;uAz%hzmg_F0xUOEEL@+f`XuexKIqZ5tQ-&@2!7s_24Z7;Y&)c2SHwGuyVNVK%mXX=!OU zX*RlOw&8J6x@X=slfPf}=hJ4{C%6c<|2Atq5-A-_`o}N9zs-#7oHbi_E>b#}^k>Jz zKC|Pf=%QKUlqkJ^|NWm4|FIeAzA~FU5h)$4=AWt7-#Ceye@9-h^D1gbqeSUo+P^2{ zYk-Vz-xbOIPzTd~d4}awqVakP{;S^<7=XH z&!nIGw$ow%%*XwU(!r{KQ?>r=Jm!sq>B)I>{-X4D+TVUC_&r}o{+IB75&rUeZTv9 zc=lhE4krEVZ(}C(nLg$9ls+@$zoI(-=3&h1Ju|Y6XIF83q;#;Ff5^Xj3Gp|Zk)3I? zHQz-_2b2Ep*TGNH-+Moj{_=X#zxLhWC+VMfE|UK8deZO4Q1b&gGhhqP5cg}ObTH{> z-T9?ZfAfn_zbG9{`dJ_2Ncvd6D80_l`WQ#j$NEL-b$-^}Ku$7$A=EEQ2b25fedDe} zPO#Ap_m3zYO#0cs?2XVr_eAKQC>>1t**C_K^s#@U^g2KL#yFBb_D_^v=U=}Uew-Q7 z_3-}M5Gfr@?%(ah^ZhJ5`|uoJKo2hyrF&NWo2%zH`wKn49D4xUw_=@tBBg^#Kfjy! zy!PKuFT?vK{+5&uCjF~FMLcRJJ9v*xT#S?sCjH&F;Ky^y6YH$Se(3X*K9lyhcy93g zC%IqlUzEP$`9IXZK4!)^vNM7?_9La&`I(pR3+;n``bg?PtZ~N7K0xg!Md_YC|0vpn-yiVz9im40`-AVv_KQ|b75AWt zc!1^q6~!k4P6(oI`k$!c8%FIfqwpcaj8|4qZ1;!qjt6;SdOt<_lMt>~J2vER-iZ$J zt_A(Xv2js4nDjG0Cqr`5%r8n`F|nci>#qqDBmKm#jpW42>&g6XD<<+JJX7*njPVd z!~DJ9LVnVfI#}z^CWD{x{*Esx9jx^m^7=O))?r@yNa>*Wm-jO2k9U0UDB|9>_Ed3b q4j(+pI6lR&F5+&vO>yP@jAq4O@K|m64}U@N7reN9q0G|)bNd&Q*3nA< literal 4248 zcmai%TZkM*6oyY%_w>vpyUEVRnPkG6OyVj&1k5I05|L4@AKEG zI;Xn2$8vM-Mw?1p^CxTDYU|os+gSZ>n_PbI&Y4}??>_LraOZX8lJ+=>@Znnf$$~KRw$l`N)iH{euJ#1xg2_{_(%z-)2U(k73Ct0;Pjdza94T zw8L1@CuZ(BQF{ISyT2g*eKXR1VYdF^KNNQrGs(*Rj6Mdevt7SHU>%u ztNzW^`iork& z!Kk0}wxfRj%*XkQ(!r{KQ+56JA$o=zvmpD;{)^IEaewn(?=ScY^1q1xMfl6>wfXb= z%KV5g{3WG>wf+X`#`!b8wL4HcSnJRBd4Kl3_b*fWzIuQ9PU%NH=g;v->0oVshx?B6 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1 10 -timestamp 1694492161 +timestamp 1694492671 << nwell >> -rect 625 -40 1305 640 +rect 675 -40 1355 640 << nmos >> -rect 161 300 331 360 -rect 161 190 331 250 +rect 211 300 381 360 +rect 211 190 381 250 << pmos >> -rect 715 330 1056 390 -rect 715 160 1056 220 +rect 765 330 1106 390 +rect 765 160 1106 220 << ndiff >> -rect 161 438 331 460 -rect 161 392 223 438 -rect 269 392 331 438 -rect 161 360 331 392 -rect 161 250 331 300 -rect 161 158 331 190 -rect 161 112 223 158 -rect 269 112 331 158 -rect 161 90 331 112 +rect 211 438 381 460 +rect 211 392 273 438 +rect 319 392 381 438 +rect 211 360 381 392 +rect 211 250 381 300 +rect 211 158 381 190 +rect 211 112 273 158 +rect 319 112 381 158 +rect 211 90 381 112 << pdiff >> -rect 715 468 1056 490 -rect 715 422 768 468 -rect 1002 422 1056 468 -rect 715 390 1056 422 -rect 715 298 1056 330 -rect 715 252 768 298 -rect 1002 252 1056 298 -rect 715 220 1056 252 -rect 715 128 1056 160 -rect 715 82 768 128 -rect 1002 82 1056 128 -rect 715 60 1056 82 +rect 765 468 1106 490 +rect 765 422 818 468 +rect 1052 422 1106 468 +rect 765 390 1106 422 +rect 765 298 1106 330 +rect 765 252 818 298 +rect 1052 252 1106 298 +rect 765 220 1106 252 +rect 765 128 1106 160 +rect 765 82 818 128 +rect 1052 82 1106 128 +rect 765 60 1106 82 << ndiffc >> -rect 223 392 269 438 -rect 223 112 269 158 +rect 273 392 319 438 +rect 273 112 319 158 << pdiffc >> -rect 768 422 1002 468 -rect 768 252 1002 298 -rect 768 82 1002 128 +rect 818 422 1052 468 +rect 818 252 1052 298 +rect 818 82 1052 128 << psubdiff >> -rect 24 23 131 40 -rect 24 -23 64 23 -rect 110 -23 131 23 -rect 24 -40 131 -23 +rect 74 23 181 40 +rect 74 -23 114 23 +rect 160 -23 181 23 +rect 74 -40 181 -23 << nsubdiff >> -rect 1122 107 1202 144 -rect 1122 61 1139 107 -rect 1185 61 1202 107 -rect 1122 37 1202 61 +rect 1172 107 1252 144 +rect 1172 61 1189 107 +rect 1235 61 1252 107 +rect 1172 37 1252 61 << psubdiffcont >> -rect 64 -23 110 23 +rect 114 -23 160 23 << nsubdiffcont >> -rect 1139 61 1185 107 +rect 1189 61 1235 107 << polysilicon >> -rect 38 373 121 400 -rect 38 327 54 373 -rect 100 360 121 373 -rect 381 360 715 390 -rect 100 327 161 360 -rect 38 300 161 327 -rect 331 330 715 360 -rect 1056 330 1106 390 -rect 331 300 421 330 -rect 38 234 161 250 -rect 38 188 54 234 -rect 100 190 161 234 -rect 331 220 421 250 -rect 331 190 715 220 -rect 100 188 121 190 -rect 38 150 121 188 -rect 381 160 715 190 -rect 1056 160 1106 220 +rect 88 373 171 400 +rect 88 327 104 373 +rect 150 360 171 373 +rect 431 360 765 390 +rect 150 327 211 360 +rect 88 300 211 327 +rect 381 330 765 360 +rect 1106 330 1156 390 +rect 381 300 471 330 +rect 88 234 211 250 +rect 88 188 104 234 +rect 150 190 211 234 +rect 381 220 471 250 +rect 381 190 765 220 +rect 150 188 171 190 +rect 88 150 171 188 +rect 431 160 765 190 +rect 1106 160 1156 220 << polycontact >> -rect 54 327 100 373 -rect 54 188 100 234 +rect 104 327 150 373 +rect 104 188 150 234 << metal1 >> -rect 161 438 401 440 -rect 51 373 103 425 -rect 161 392 223 438 -rect 269 392 401 438 -rect 757 422 768 468 -rect 1002 422 1014 468 -rect 853 416 865 422 -rect 917 416 929 422 -rect 161 390 401 392 -rect 51 327 54 373 -rect 100 327 103 373 -rect 51 313 103 327 -rect 351 300 401 390 -rect 1080 300 1132 463 -rect 351 298 1132 300 -rect 351 252 768 298 -rect 1002 252 1132 298 -rect 351 250 1132 252 -rect 51 234 103 248 -rect 51 188 54 234 -rect 100 188 103 234 -rect 51 129 103 188 -rect 191 106 223 158 -rect 275 106 298 158 -rect 853 128 865 134 -rect 917 128 929 134 -rect 191 100 298 106 -rect 757 82 768 128 -rect 1002 82 1014 128 -rect 1089 58 1136 110 -rect 1188 58 1200 110 -rect 30 26 129 36 -rect 30 -26 61 26 -rect 113 -26 129 26 -rect 30 -34 129 -26 +rect 211 438 451 440 +rect 101 373 153 425 +rect 211 392 273 438 +rect 319 392 451 438 +rect 807 422 818 468 +rect 1052 422 1064 468 +rect 903 416 915 422 +rect 967 416 979 422 +rect 211 390 451 392 +rect 101 327 104 373 +rect 150 327 153 373 +rect 101 313 153 327 +rect 401 300 451 390 +rect 1130 300 1182 463 +rect 401 298 1182 300 +rect 401 252 818 298 +rect 1052 252 1182 298 +rect 401 250 1182 252 +rect 101 234 153 248 +rect 101 188 104 234 +rect 150 188 153 234 +rect 101 129 153 188 +rect 241 106 273 158 +rect 325 106 348 158 +rect 903 128 915 134 +rect 967 128 979 134 +rect 241 100 348 106 +rect 807 82 818 128 +rect 1052 82 1064 128 +rect 1139 58 1186 110 +rect 1238 58 1250 110 +rect 80 26 179 36 +rect 80 -26 111 26 +rect 163 -26 179 26 +rect 80 -34 179 -26 << via1 >> -rect 865 422 917 468 -rect 865 416 917 422 -rect 223 112 269 158 -rect 269 112 275 158 -rect 223 106 275 112 -rect 865 128 917 134 -rect 865 82 917 128 -rect 1136 107 1188 110 -rect 1136 61 1139 107 -rect 1139 61 1185 107 -rect 1185 61 1188 107 -rect 1136 58 1188 61 -rect 61 23 113 26 -rect 61 -23 64 23 -rect 64 -23 110 23 -rect 110 -23 113 23 -rect 61 -26 113 -23 +rect 915 422 967 468 +rect 915 416 967 422 +rect 273 112 319 158 +rect 319 112 325 158 +rect 273 106 325 112 +rect 915 128 967 134 +rect 915 82 967 128 +rect 1186 107 1238 110 +rect 1186 61 1189 107 +rect 1189 61 1235 107 +rect 1235 61 1238 107 +rect 1186 58 1238 61 +rect 111 23 163 26 +rect 111 -23 114 23 +rect 114 -23 160 23 +rect 160 -23 163 23 +rect 111 -26 163 -23 << metal2 >> -rect 221 158 277 520 -rect 221 106 223 158 -rect 275 106 277 158 -rect 221 28 277 106 -rect 39 26 277 28 -rect 39 -26 61 26 -rect 113 -26 277 26 -rect 863 468 919 520 -rect 863 416 865 468 -rect 917 416 919 468 -rect 863 134 919 416 -rect 863 82 865 134 -rect 917 112 919 134 -rect 917 110 1200 112 -rect 917 82 1136 110 -rect 863 58 1136 82 -rect 1188 58 1200 110 -rect 863 56 1200 58 -rect 863 8 919 56 -rect 39 -28 277 -26 +rect 271 158 327 520 +rect 271 106 273 158 +rect 325 106 327 158 +rect 271 28 327 106 +rect 89 26 327 28 +rect 89 -26 111 26 +rect 163 -26 327 26 +rect 913 468 969 520 +rect 913 416 915 468 +rect 967 416 969 468 +rect 913 134 969 416 +rect 913 82 915 134 +rect 967 112 969 134 +rect 967 110 1250 112 +rect 967 82 1186 110 +rect 913 58 1186 82 +rect 1238 58 1250 110 +rect 913 56 1250 58 +rect 913 8 969 56 +rect 89 -28 327 -26 << labels >> -rlabel metal1 s 1106 439 1106 439 4 Y -rlabel metal1 s 77 211 77 211 4 B -rlabel metal1 s 77 350 77 350 4 A -rlabel metal2 s 891 33 891 33 4 VDD -rlabel metal2 s 250 56 250 56 4 GND +rlabel metal1 s 1156 439 1156 439 4 Y +rlabel metal1 s 127 211 127 211 4 B +rlabel metal1 s 127 350 127 350 4 A +rlabel metal2 s 941 33 941 33 4 VDD +rlabel metal2 s 300 56 300 56 4 GND << properties >> -string FIXED_BBOX 0 0 1305 522 +string FIXED_BBOX 0 0 1355 522 << end >> From cb8567c66f8daa6dc6356d503dc8ffa5bab3f9a7 Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Mon, 11 Sep 2023 21:40:20 -0700 Subject: [PATCH 32/61] spacing tweaks for gf180 address control gate --- compiler/modules/pinv_dec.py | 6 ++-- compiler/modules/rom_address_control_array.py | 5 +-- compiler/modules/rom_address_control_buf.py | 33 +++++++++++-------- .../sp_lib/gf180mcu_3v3__nand2_1_dec.sp | 6 ++-- technology/gf180mcu/tech/tech.py | 31 ++++++++++------- 5 files changed, 50 insertions(+), 31 deletions(-) diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py index 1ee75266..193fe6b1 100644 --- a/compiler/modules/pinv_dec.py +++ b/compiler/modules/pinv_dec.py @@ -242,10 +242,12 @@ class pinv_dec(pinv): source_pos = self.nmos_inst.get_pin("S").center() self.add_via_stack_center(offset=source_pos, from_layer=self.route_layer, - to_layer=self.supply_layer) + to_layer=self.supply_layer, + min_area=True) source_pos = self.pmos_inst.get_pin("S").center() self.add_via_stack_center(offset=source_pos, from_layer=self.route_layer, - to_layer=self.supply_layer) + to_layer=self.supply_layer, + min_area=True) diff --git a/compiler/modules/rom_address_control_array.py b/compiler/modules/rom_address_control_array.py index 9f59ca71..dc4cbf2e 100644 --- a/compiler/modules/rom_address_control_array.py +++ b/compiler/modules/rom_address_control_array.py @@ -21,11 +21,11 @@ class rom_address_control_array(design): self.size=inv_size self.cols = cols self.route_layer = route_layer - dff = factory.create(module_type="dff") if name=="": name = "rom_inv_array_{0}".format(cols) if inv_height == None: - self.inv_height = dff.height * 0.5 + + self.inv_height = drc("minwidth_{}".format(route_layer)) * 14 else: self.inv_height = inv_height @@ -34,6 +34,7 @@ class rom_address_control_array(design): self.inv_layer = "li" else: self.inv_layer = "m1" + self.route_layer = "m2" super().__init__(name) self.create_netlist() self.create_layout() diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py index 9e092ff0..b9cbbf44 100644 --- a/compiler/modules/rom_address_control_buf.py +++ b/compiler/modules/rom_address_control_buf.py @@ -25,8 +25,11 @@ class rom_address_control_buf(design): self.size = size if "li" in layer: self.inv_layer = "li" + self.non_inverting_layer = "m2" else: self.inv_layer = "m1" + self.route_layer = "m2" + self.non_inverting_layer = "m3" super().__init__(name) self.create_netlist() self.create_layout() @@ -47,11 +50,11 @@ class rom_address_control_buf(design): def create_modules(self): - self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size) - self.nand = factory.create(module_type="nand2_dec", height=self.inv.height) # For layout constants self.cell = factory.create(module_type="rom_base_cell") + self.nand = factory.create(module_type="nand2_dec") + self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size, height=self.nand.height) def add_pins(self): self.add_pin("A_in", "INPUT") @@ -129,18 +132,18 @@ class rom_address_control_buf(design): # Route first NAND output to second NAND input start = A_out.center() end = Aint_in.center() - self.add_path("m2", [start, end]) - self.add_via_stack_center(Aint_in.center(), self.inv_layer, "m2") - self.add_via_stack_center(A_out.center(), self.inv_layer, "m2") + self.add_path(self.non_inverting_layer, [start, end]) + self.add_via_stack_center(Aint_in.center(), self.inv_layer, self.non_inverting_layer) + self.add_via_stack_center(A_out.center(), self.inv_layer, self.non_inverting_layer) # Route first NAND to output pin - self.add_segment_center("m2", end, vector(end.x, self.addr_bar_nand.uy())) - self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2") + self.add_segment_center(self.non_inverting_layer, end, vector(end.x, self.addr_bar_nand.uy())) + self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer=self.non_inverting_layer) # Route second NAND to output pin - self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2") - self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy())) - self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2") + self.add_via_stack_center(Abar_out.center(), self.inv_layer, self.non_inverting_layer) + self.add_segment_center(self.non_inverting_layer, Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy())) + self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer=self.non_inverting_layer) # Route inverter output to NAND end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width) @@ -166,14 +169,17 @@ class rom_address_control_buf(design): left_edge = self.inv_inst.get_pin("Z").cx() - 2 * self.contact_width - 2 * self.active_contact_to_gate - 4 * self.active_enclose_contact - self.poly_width - self.active_space contact_pos = vector(left_edge, source_pin.cy()) - + self.add_layout_pin_rect_center("left_edge", offset=contact_pos, layer="m1") self.add_via_center(layers=self.active_stack, offset=contact_pos, implant_type="n", well_type="n") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], - to_layer=self.route_layer) + to_layer=self.route_layer, + min_area=True) + + # self.add_segment_center(layer=self.) contact_pos = vector(left_edge, gnd_pin.cy()) self.add_via_center(layers=self.active_stack, @@ -182,4 +188,5 @@ class rom_address_control_buf(design): well_type="p") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], - to_layer=self.route_layer) \ No newline at end of file + to_layer=self.route_layer, + min_area=True) \ No newline at end of file diff --git a/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp index f2e114c0..bba3f127 100644 --- a/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp +++ b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp @@ -1,6 +1,6 @@ -.subckt gf180mcu_3v3__nand2_1_dec A B Y VDD VSS +.subckt gf180mcu_3v3__nand2_1_dec A B Y VDD GND X0 VDD B Y VDD pfet_03p3 w=1.7u l=0.3u X1 Y A VDD VDD pfet_03p3 w=1.7u l=0.3u -X2 a_28_21# A Y VSS nfet_03p3 w=0.85u l=0.3u -X3 VSS B a_28_21# VSS nfet_03p3 w=0.85u l=0.3u +X2 a_28_21# A Y GND nfet_03p3 w=0.85u l=0.3u +X3 VSS B a_28_21# GND nfet_03p3 w=0.85u l=0.3u .ends \ No newline at end of file diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 6edf199f..c6f2259f 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -24,6 +24,7 @@ File containing the process technology parameters for Global Foundaries 180nm tech_modules = d.module_type() tech_modules["bitcell_1port"] = "gf180_bitcell" +tech_modules["nand2_dec"] = "nand2_dec" ################################################### # Custom cell properties @@ -48,6 +49,14 @@ cell_properties.bitcell_1port.bl_layer = "m2" cell_properties.bitcell_1port.vdd_layer = "m1" cell_properties.bitcell_1port.gnd_layer = "m1" +cell_properties.nand2_dec.port_order = ['A', 'B', 'Z', 'vdd', 'gnd'] +cell_properties.nand2_dec.port_map = {'A': 'A', + 'B': 'B', + 'Z': 'Y', + 'vdd': 'VDD', + 'gnd': 'GND'} + + cell_properties.ptx.model_is_subckt = True cell_properties.use_strap = True @@ -194,7 +203,7 @@ drc["grid"] = 0.005 # minwidth_tx with contact (no dog bone transistors) drc["minwidth_tx"] = 0.5 # PL.2 Min gate width/channel length for 6V pmos (0.7 for 6V nmos) -drc["minlength_channel"] = 0.7 +drc["minlength_channel"] = 0.28 drc["minlength_channel_pmos"] = 0.55 drc["minlength_channel_nmos"] = 0.7 @@ -209,10 +218,10 @@ drc.add_layer("pwell", width=0.74, # 0.6 for 3.3v spacing=0.86) # equal potential -# PL.1 minwidth of interconnect poly 5/6V -# PL.3a poly spacing 5/6V +# PL.1 minwidth of interconnect poly 3v3 +# PL.3a poly spacing 3v3 drc.add_layer("poly", - width=0.2, + width=0.28, spacing=0.24) drc["poly_extend_active"] = 0.22 @@ -226,12 +235,12 @@ drc["poly_to_active"] = 0.1 #drc["poly_to_field_poly"] = 0.210 # -# DF.1a - minwidth of active (5/6V) -# DF.3a - minspacing of active of the same type (5/6V) -# DF.9 - minarea of active area=0.2025 (5/6V) +# DF.1a - minwidth of active (3v3) +# min space of tap to diff across butted junction +# DF.9 - minarea of active area=0.2025 drc.add_layer("active", - width=0.3, - spacing=0.36, + width=0.22, + spacing=0.33, area=0.2025) drc.add_enclosure("dnwell", @@ -292,12 +301,12 @@ drc.add_layer("m1", drc.add_enclosure("m1", layer="contact", - enclosure=0.06, + enclosure=0, extension=0.06) drc.add_enclosure("m1", layer="via1", - enclosure=0.06, + enclosure=0, extension=0.06) drc.add_layer("via1", From 20d0df29470f831f939146c240e51b0b02e4e89c Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 21:29:54 -0700 Subject: [PATCH 33/61] more boundary on the other side --- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4248 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index 552a6a2b223c3326cb30ea842782807869bfc3d9..e562594809ea94504396920afedec55411b61c45 100644 GIT binary patch delta 111 zcmbQCI73l^fsKKQDS|q~&7yz~`7MK74 delta 111 zcmbQCI73l^fsKKQDS|Bv}L*7+BbWn1ulV1TzZa diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index 77f17589..6790f748 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,7 +1,7 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694492671 +timestamp 1694492972 << nwell >> rect 675 -40 1355 640 << nmos >> @@ -158,5 +158,5 @@ rlabel metal1 s 127 350 127 350 4 A rlabel metal2 s 941 33 941 33 4 VDD rlabel metal2 s 300 56 300 56 4 GND << properties >> -string FIXED_BBOX 0 0 1355 522 +string FIXED_BBOX -17 0 1373 522 << end >> From a544abebf75c2e830232490afb3a040d140e586f Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 11 Sep 2023 23:11:02 -0700 Subject: [PATCH 34/61] fixed contact area issue --- compiler/base/hierarchy_layout.py | 3 +-- compiler/modules/pinv_dec.py | 6 ++---- compiler/modules/rom_address_control_buf.py | 8 ++------ technology/gf180mcu/tech/tech.py | 12 +++++------- 4 files changed, 10 insertions(+), 19 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 504cf6a9..58cf1a81 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -259,8 +259,7 @@ class layout(): contact_width = contact1.first_layer_width layer_space = getattr(layout, layer1 + "_space") - #print(layer_stack) - #print(contact1) + pitch = contact_width + layer_space return round_to_grid(pitch) diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py index 193fe6b1..1ee75266 100644 --- a/compiler/modules/pinv_dec.py +++ b/compiler/modules/pinv_dec.py @@ -242,12 +242,10 @@ class pinv_dec(pinv): source_pos = self.nmos_inst.get_pin("S").center() self.add_via_stack_center(offset=source_pos, from_layer=self.route_layer, - to_layer=self.supply_layer, - min_area=True) + to_layer=self.supply_layer) source_pos = self.pmos_inst.get_pin("S").center() self.add_via_stack_center(offset=source_pos, from_layer=self.route_layer, - to_layer=self.supply_layer, - min_area=True) + to_layer=self.supply_layer) diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py index b9cbbf44..ffab3228 100644 --- a/compiler/modules/rom_address_control_buf.py +++ b/compiler/modules/rom_address_control_buf.py @@ -176,10 +176,7 @@ class rom_address_control_buf(design): well_type="n") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], - to_layer=self.route_layer, - min_area=True) - - # self.add_segment_center(layer=self.) + to_layer=self.route_layer) contact_pos = vector(left_edge, gnd_pin.cy()) self.add_via_center(layers=self.active_stack, @@ -188,5 +185,4 @@ class rom_address_control_buf(design): well_type="p") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], - to_layer=self.route_layer, - min_area=True) \ No newline at end of file + to_layer=self.route_layer) \ No newline at end of file diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index c6f2259f..c5db178a 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -240,8 +240,7 @@ drc["poly_to_active"] = 0.1 # DF.9 - minarea of active area=0.2025 drc.add_layer("active", width=0.22, - spacing=0.33, - area=0.2025) + spacing=0.33) drc.add_enclosure("dnwell", layer="pwell", @@ -278,7 +277,7 @@ drc.add_layer("contact", drc.add_enclosure("active", layer="contact", enclosure=0.07, - extension=0.07) + extension=0.175) drc.add_enclosure("poly", layer="contact", @@ -296,18 +295,17 @@ drc["poly_contact_to_gate"] = 0.165 # M1.3 - area drc.add_layer("m1", width=0.23, - spacing=0.23, - area=0.1444) + spacing=0.23) drc.add_enclosure("m1", layer="contact", enclosure=0, - extension=0.06) + extension=0.205) drc.add_enclosure("m1", layer="via1", enclosure=0, - extension=0.06) + extension=0.205) drc.add_layer("via1", width=0.26, From b2797917629ca0b5a49e715bb41dd0bd3ff5a520 Mon Sep 17 00:00:00 2001 From: Sage Walker Date: Mon, 11 Sep 2023 23:10:28 -0700 Subject: [PATCH 35/61] added control buf test --- .../tests/04_rom_address_control_buf_test.py | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 compiler/tests/04_rom_address_control_buf_test.py diff --git a/compiler/tests/04_rom_address_control_buf_test.py b/compiler/tests/04_rom_address_control_buf_test.py new file mode 100644 index 00000000..38bf0137 --- /dev/null +++ b/compiler/tests/04_rom_address_control_buf_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class precharge_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + # check precharge in single port + debug.info(2, "Testing rom address control buffer") + + + tx = factory.create(module_type="rom_address_control_buf", module_name="address_control_cell", size=6) + self.local_check(tx) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 75f7a5847f3e57170d75e1ea6094ca43f64c5095 Mon Sep 17 00:00:00 2001 From: SWalker Date: Wed, 13 Sep 2023 11:41:15 -0700 Subject: [PATCH 36/61] fixing contact placement for gf180 in rom --- compiler/modules/rom_address_control_buf.py | 15 +- compiler/modules/rom_base_array.py | 10 +- compiler/modules/rom_decoder.py | 15 +- compiler/modules/rom_poly_tap.py | 13 +- compiler/modules/rom_precharge_array.py | 21 +- compiler/modules/rom_wordline_driver_array.py | 3 +- compiler/tests/04_rom_precharge_test.py | 2 +- compiler/tests/14_rom_array_test.py | 6 +- .../gds_lib/gf180mcu_3v3__nand2_1_dec.gds | Bin 4248 -> 4266 bytes .../mag_lib/gf180mcu_3v3__nand2_1_dec.mag | 283 +++++++++--------- .../sp_lib/gf180mcu_3v3__nand2_1_dec.sp | 12 +- technology/gf180mcu/tech/tech.py | 44 ++- 12 files changed, 232 insertions(+), 192 deletions(-) diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py index ffab3228..6c7d11ea 100644 --- a/compiler/modules/rom_address_control_buf.py +++ b/compiler/modules/rom_address_control_buf.py @@ -10,6 +10,8 @@ from openram.base import design from openram.sram_factory import factory from openram.base import vector from openram.tech import layer, drc +from openram import OPTS + @@ -111,16 +113,25 @@ class rom_address_control_buf(design): Aint_in = self.addr_bar_nand.get_pin("B") A_in = self.inv_inst.get_pin("A") - + vdd_rail = self.addr_nand.get_pin("vdd") # Find the center of the pmos poly/gate poly_right = clk1_pin.cx() + self.poly_enclose_contact + 0.5 * self.contact_width ppoly_center = poly_right - 0.7 * self.poly_width + poly_y = A_out.cy() + if OPTS.tech_name == "gf180mcu": + poly_y = vdd_rail.cy() + 0.5 * drc("minwidth_tx") * 3 + self.poly_extend_active + ppoly_center = A_out.cx() + 0.5 * self.interconnect_width + 0.5 * self.poly_width + else: + ppoly_center = poly_right - 0.7 * self.poly_width + poly_y = A_out.cy() contact_offset = vector(ppoly_center, clk2_pin.cy()) + self.add_layout_pin_rect_center("cont", offset=contact_offset, layer="poly") + self.add_layout_pin_rect_center("ppoly", offset=vector(ppoly_center, poly_y), layer="poly") # Route the two shared clk inputs together by connecting poly - self.add_segment_center("poly", contact_offset, vector(ppoly_center, A_out.cy())) + self.add_segment_center("poly", contact_offset, vector(ppoly_center, poly_y)) clk_offset = vector(clk2_pin.cx(), self.addr_nand.uy()) diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 804ce70a..8ae7ea56 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -88,6 +88,8 @@ class rom_base_array(bitcell_base_array): else: self.poly_tap = factory.create(module_type="rom_poly_tap", add_active_tap=True) self.end_poly_tap = factory.create(module_type="rom_poly_tap", place_poly=True) + + print("poly tap width", self.poly_tap.width, "height", self.poly_tap.height, self.tap_direction) self.precharge_array = factory.create(module_type="rom_precharge_array", cols=self.column_size, strap_spacing=self.strap_spacing, @@ -100,6 +102,7 @@ class rom_base_array(bitcell_base_array): self.route_pitch = drc("{0}_to_{0}".format(self.bitline_layer)) def add_pins(self): + print(self.get_wordline_names()) for bl_name in self.get_bitline_names(): self.add_pin(bl_name, "OUTPUT") for wl_name in self.get_wordline_names(): @@ -215,7 +218,7 @@ class rom_base_array(bitcell_base_array): self.remove_layout_pin("gnd") active_tap_pins = [self.active_tap_list[i].get_pin("active_tap") for i in range(len(self.active_tap_list))] - self.connect_col_pins(layer=self.supply_stack[0], pins=active_tap_pins, name="gnd_tmp") + self.connect_col_pins(layer=self.supply_stack[0], pins=active_tap_pins, name="gnd_tmp", directions="nonpref") gnd_y = gnd_l.y min_x = float('inf') @@ -246,7 +249,6 @@ class rom_base_array(bitcell_base_array): self.cell_pos = {} self.strap_pos = {} pitch_offset = 0 - for row in range(self.row_size + 1): if row % self.tap_spacing == 0 and self.pitch_match and row != self.row_size: @@ -331,7 +333,7 @@ class rom_base_array(bitcell_base_array): else: output_layer = "m3" rail_y = self.precharge_inst.get_pins("vdd")[0].cy() - + print("cols ", self.bitline_names[0]) for bl in range(self.column_size): src_pin = self.cell_list[0][bl].get_pin("S") @@ -382,3 +384,5 @@ class rom_base_array(bitcell_base_array): poly_tap_pins = [self.poly_tap_list[i].get_pin("poly_tap") for i in range(len(self.poly_tap_list))] self.connect_row_pins(layer=self.wordline_layer, pins=poly_tap_pins) + self.connect_row_pins(layer="poly", pins=poly_tap_pins) + diff --git a/compiler/modules/rom_decoder.py b/compiler/modules/rom_decoder.py index 760af8c4..4540aadd 100644 --- a/compiler/modules/rom_decoder.py +++ b/compiler/modules/rom_decoder.py @@ -9,15 +9,19 @@ from math import ceil, log from openram.sram_factory import factory from openram.base import vector, design from openram import OPTS -from openram.tech import drc - +from openram.tech import drc, layer class rom_decoder(design): def __init__(self, num_outputs, fanout, strap_spacing, name="", route_layer="m1", output_layer="m1", invert_outputs=False): # word lines in the base array become the address lines/cols in the decoder # bit lines in the base array become the word lines/rows in the decoder # array gets rotated 90deg so rows/cols switch - + if "li" in layer: + self.output_layer = "m1" + self.inv_route_layer = "m2" + else: + self.output_layer = "m1" + self.inv_route_layer = "m3" self.strap_spacing=strap_spacing self.num_outputs = num_outputs self.num_inputs = ceil(log(num_outputs, 2)) @@ -28,8 +32,6 @@ class rom_decoder(design): b = factory.create(module_type=OPTS.bitcell) self.cell_height = b.height self.route_layer = route_layer - self.output_layer = output_layer - self.inv_route_layer = "m2" self.fanout=fanout self.invert_outputs=invert_outputs self.create_netlist() @@ -203,13 +205,12 @@ class rom_decoder(design): for j in range(self.num_outputs): self.copy_layout_pin(self.wordline_buf_inst, "out_{}".format(j), "wl_{}".format(j)) - offset = self.wordline_buf_inst.get_pin("out_{}".format(j)).center() array_pins = [self.array_inst.get_pin("bl_0_{}".format(bl)) for bl in range(self.num_outputs)] driver_pins = [self.wordline_buf_inst.get_pin("in_{}".format(bl)) for bl in range(self.num_outputs)] route_pins = array_pins + driver_pins - self.connect_row_pins(self.output_layer, route_pins, round=True) + self.connect_row_pins(self.inv_route_layer, route_pins, round=True) def connect_inputs(self): diff --git a/compiler/modules/rom_poly_tap.py b/compiler/modules/rom_poly_tap.py index 2bbbe18f..e5bb288c 100644 --- a/compiler/modules/rom_poly_tap.py +++ b/compiler/modules/rom_poly_tap.py @@ -35,17 +35,19 @@ class rom_poly_tap(design): def create_layout(self): self.place_via() - self.add_boundary() # self.extend_poly() if self.add_tap or self.place_poly: self.place_active_tap() + self.add_boundary() + + def add_boundary(self): contact_width = self.poly_contact.width self.height = self.dummy.height self.width = contact_width + self.pitch_offset - + print("pitch off", self.pitch_offset) super().add_boundary() def place_via(self): @@ -60,14 +62,9 @@ class rom_poly_tap(design): contact_x = contact_width * 0.5 + self.contact_x_offset self.contact_offset = vector(contact_x, contact_y) - if OPTS.tech_name == "sky130": - directions="pref" - else: - directions="nonpref" self.via = self.add_via_stack_center(from_layer="poly", to_layer=self.strap_layer, - offset=self.contact_offset, - directions=directions) + offset=self.contact_offset) self.add_layout_pin_rect_center("poly_tap", self.strap_layer, self.contact_offset) def extend_poly(self): diff --git a/compiler/modules/rom_precharge_array.py b/compiler/modules/rom_precharge_array.py index 995f2ef9..0aad55be 100644 --- a/compiler/modules/rom_precharge_array.py +++ b/compiler/modules/rom_precharge_array.py @@ -17,24 +17,17 @@ class rom_precharge_array(design): """ An array of inverters to create the inverted address lines for the rom decoder """ - def __init__(self, cols, name="", bitline_layer="m2", strap_spacing=None, strap_layer="m3", tap_direction="row"): + def __init__(self, cols, name="", bitline_layer="m2", strap_spacing=0, strap_layer="m3", tap_direction="row"): self.cols = cols self.strap_layer = strap_layer self.bitline_layer = bitline_layer self.tap_direction = tap_direction - + self.strap_spacing = strap_spacing if "li" in layer: self.supply_layer = "li" else: self.supply_layer = "m1" - - if strap_spacing != None: - self.strap_spacing = strap_spacing - else: - self.strap_spacing = 0 - - if strap_spacing != 0: self.num_straps = ceil(self.cols / self.strap_spacing) self.array_col_size = self.cols + self.num_straps @@ -158,11 +151,17 @@ class rom_precharge_array(design): self.add_segment_center(layer="poly", start=offset_start, end=offset_end) self.add_segment_center(layer="poly", start=self.pmos_insts[-1].get_pin("G").center(), end=offset_end) + + gate_y = self.pmos_insts[0].get_pin('G').cy() + start = vector( self.get_pin("gate").lx(), gate_y) + end = vector( self.get_pin("precharge_r").rx(), gate_y ) + + self.add_segment_center(layer="poly", start=start, end=end) + def extend_well(self): self.well_offset = self.pmos.tap_offset - well_y = self.pmos_insts[0].get_pin("vdd").cy() - 0.5 * self.nwell_width - well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width + well_y = self.get_pin("vdd").by() - self.nwell_enclose_active well_ll = vector(0, well_y) self.add_rect("nwell", well_ll, self.width , self.height - well_y) \ No newline at end of file diff --git a/compiler/modules/rom_wordline_driver_array.py b/compiler/modules/rom_wordline_driver_array.py index 44deac1c..c77cfdae 100644 --- a/compiler/modules/rom_wordline_driver_array.py +++ b/compiler/modules/rom_wordline_driver_array.py @@ -214,7 +214,8 @@ class rom_wordline_driver_array(design): directions="nonpref") self.add_via_stack_center(offset=offset, from_layer=self.active_stack[2], - to_layer=self.supply_layer) + to_layer=self.supply_layer, + directions="nonpref") if well_type == "p": pin = "gnd_tap" self.gnd_taps.append(self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)) diff --git a/compiler/tests/04_rom_precharge_test.py b/compiler/tests/04_rom_precharge_test.py index aa0c443b..862e6cb0 100644 --- a/compiler/tests/04_rom_precharge_test.py +++ b/compiler/tests/04_rom_precharge_test.py @@ -26,7 +26,7 @@ class precharge_test(openram_test): debug.info(2, "Testing rom precharge bitcell") - tx = factory.create(module_type="rom_precharge_cell", module_name="precharge_cell", bitline_layer="m2", supply_layer="m1") + tx = factory.create(module_type="rom_precharge_array", module_name="rom_precharge_array", cols=8, strap_spacing=2, tap_direction="col") self.local_check(tx) openram.end_openram() diff --git a/compiler/tests/14_rom_array_test.py b/compiler/tests/14_rom_array_test.py index c7a03ea1..80e188af 100755 --- a/compiler/tests/14_rom_array_test.py +++ b/compiler/tests/14_rom_array_test.py @@ -25,9 +25,11 @@ class rom_array_test(openram_test): debug.info(2, "Testing 4x4 array for rom cell") - data = [[1, 0, 0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 0, 0, 1, 0, 0], [0, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 0, 1, 0, 0, 0, 1, 0]] + # data = [[1, 0, 0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 0, 0, 1, 0, 0], [0, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 0, 1, 0, 0, 0, 1, 0]] - a = factory.create(module_type="rom_base_array", cols=9, rows=8, bitmap=data, strap_spacing=4, pitch_match=True) + + data = [[1, 0, 0], [1, 1, 1], [0,1, 0]] + a = factory.create(module_type="rom_base_array", cols=3, rows=3, bitmap=data, strap_spacing=1, pitch_match=True) self.local_check(a) a.sp_write(OPTS.openram_temp + 'simulation_file.sp') diff --git a/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds b/technology/gf180mcu/gds_lib/gf180mcu_3v3__nand2_1_dec.gds index e562594809ea94504396920afedec55411b61c45..dfafe19ca827b0b72942088b4f1d2f2affebae0b 100644 GIT binary patch literal 4266 zcmbW4Pl#1z7{=do?!D)pd*{y88TF21gQHEf$k1${(uIRHP&8zW*iRMyR&f~Yvefs9F+h)&fIrYlkJvPy(m@TWCt)81@!>O&YtecwIjVo(r!&{b@ zmmed|I;YLnJu6CgtdE$<-z)oj-(jYo&Bz*NUHeR+bTH~q4*7MGLzw4Jc#n(HtJm-T zW|r(TBU|Uq)|?EK4o26nPs0B@k^@_t&6-aKN(amS4FmblV!w09A56}ejjs-r4#xdo z`S>1K>!E(f0y!UbFzT-z#rPh0K-NFUL5b4AxPP0EuYvgn{JTGp^H2xleymF$*Kd7^ zYpgFy2h0A+a{apVsNXr9ADBLYe76Tm2c!OEANpefH9!v}UF_pkQMzN)-yQPnk@*K$ z|Aj#Arx=g>v2Xgg|MrsKzbG9n``4HA&mYI0cViCnNBCbVQTpzRTm2t`~mbFSi1u~bW5OgFzQc-5q}wTfc1~Tp8}0SBR+poI#`*1e%R;Vn)msO z(!r>oc{7frk9mvItNhHHaU^}rTa;eqXWuk0p=MzIk?$W-I#}NSwdMOaIf4807<%{w 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z8t3Q1Na@SI9|z`_oyPe%h&4`|*@vk8gecw9=O0FU@cRS)zC+Y7e}C{j*?!TAiQ*nK z5f8BZzoPg=zzIRr&Hocse8Z@{WfVSSnDMIWiS7PS-tiz$Oz)>ie-gs=YR3lr%{$Q{ z-nF2gI5sXy2a|s0=VVAun)yZP%O*CEf9){H0*lfS;PbS=-2MfJBi#W2 diff --git a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag index 6790f748..4182347f 100644 --- a/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag +++ b/technology/gf180mcu/mag_lib/gf180mcu_3v3__nand2_1_dec.mag @@ -1,162 +1,165 @@ magic tech gf180mcuD magscale 1 10 -timestamp 1694492972 +timestamp 1694553776 << nwell >> -rect 675 -40 1355 640 +rect 675 -30 1355 650 << nmos >> -rect 211 300 381 360 -rect 211 190 381 250 +rect 211 310 381 370 +rect 211 200 381 260 << pmos >> -rect 765 330 1106 390 -rect 765 160 1106 220 +rect 765 340 1106 400 +rect 765 170 1106 230 << ndiff >> -rect 211 438 381 460 -rect 211 392 273 438 -rect 319 392 381 438 -rect 211 360 381 392 -rect 211 250 381 300 -rect 211 158 381 190 -rect 211 112 273 158 -rect 319 112 381 158 -rect 211 90 381 112 +rect 211 448 381 470 +rect 211 402 273 448 +rect 319 402 381 448 +rect 211 370 381 402 +rect 211 260 381 310 +rect 211 168 381 200 +rect 211 122 273 168 +rect 319 122 381 168 +rect 211 100 381 122 << pdiff >> -rect 765 468 1106 490 -rect 765 422 818 468 -rect 1052 422 1106 468 -rect 765 390 1106 422 -rect 765 298 1106 330 -rect 765 252 818 298 -rect 1052 252 1106 298 -rect 765 220 1106 252 -rect 765 128 1106 160 -rect 765 82 818 128 -rect 1052 82 1106 128 -rect 765 60 1106 82 +rect 765 478 1106 500 +rect 765 432 818 478 +rect 1052 432 1106 478 +rect 765 400 1106 432 +rect 765 308 1106 340 +rect 765 262 818 308 +rect 1052 262 1106 308 +rect 765 230 1106 262 +rect 765 138 1106 170 +rect 765 92 818 138 +rect 1052 92 1106 138 +rect 765 70 1106 92 << ndiffc >> -rect 273 392 319 438 -rect 273 112 319 158 +rect 273 402 319 448 +rect 273 122 319 168 << pdiffc >> -rect 818 422 1052 468 -rect 818 252 1052 298 -rect 818 82 1052 128 +rect 818 432 1052 478 +rect 818 262 1052 308 +rect 818 92 1052 138 << psubdiff >> -rect 74 23 181 40 -rect 74 -23 114 23 -rect 160 -23 181 23 -rect 74 -40 181 -23 +rect 74 33 181 50 +rect 74 -13 114 33 +rect 160 -13 181 33 +rect 74 -30 181 -13 << nsubdiff >> -rect 1172 107 1252 144 -rect 1172 61 1189 107 -rect 1235 61 1252 107 -rect 1172 37 1252 61 +rect 1172 117 1252 154 +rect 1172 71 1189 117 +rect 1235 71 1252 117 +rect 1172 47 1252 71 << psubdiffcont >> -rect 114 -23 160 23 +rect 114 -13 160 33 << nsubdiffcont >> -rect 1189 61 1235 107 +rect 1189 71 1235 117 << polysilicon >> -rect 88 373 171 400 -rect 88 327 104 373 -rect 150 360 171 373 -rect 431 360 765 390 -rect 150 327 211 360 -rect 88 300 211 327 -rect 381 330 765 360 -rect 1106 330 1156 390 -rect 381 300 471 330 -rect 88 234 211 250 -rect 88 188 104 234 -rect 150 190 211 234 -rect 381 220 471 250 -rect 381 190 765 220 -rect 150 188 171 190 -rect 88 150 171 188 -rect 431 160 765 190 -rect 1106 160 1156 220 +rect 88 383 171 410 +rect 88 337 104 383 +rect 150 370 171 383 +rect 431 370 765 400 +rect 150 337 211 370 +rect 88 310 211 337 +rect 381 340 765 370 +rect 1106 340 1156 400 +rect 381 310 471 340 +rect 88 244 211 260 +rect 88 198 104 244 +rect 150 200 211 244 +rect 381 230 471 260 +rect 381 200 765 230 +rect 150 198 171 200 +rect 88 160 171 198 +rect 431 170 765 200 +rect 1106 170 1156 230 << polycontact >> -rect 104 327 150 373 -rect 104 188 150 234 +rect 104 337 150 383 +rect 104 198 150 244 << metal1 >> -rect 211 438 451 440 -rect 101 373 153 425 -rect 211 392 273 438 -rect 319 392 451 438 -rect 807 422 818 468 -rect 1052 422 1064 468 -rect 903 416 915 422 -rect 967 416 979 422 -rect 211 390 451 392 -rect 101 327 104 373 -rect 150 327 153 373 -rect 101 313 153 327 -rect 401 300 451 390 -rect 1130 300 1182 463 -rect 401 298 1182 300 -rect 401 252 818 298 -rect 1052 252 1182 298 -rect 401 250 1182 252 -rect 101 234 153 248 -rect 101 188 104 234 -rect 150 188 153 234 -rect 101 129 153 188 -rect 241 106 273 158 -rect 325 106 348 158 -rect 903 128 915 134 -rect 967 128 979 134 -rect 241 100 348 106 -rect 807 82 818 128 -rect 1052 82 1064 128 -rect 1139 58 1186 110 -rect 1238 58 1250 110 -rect 80 26 179 36 -rect 80 -26 111 26 -rect 163 -26 179 26 -rect 80 -34 179 -26 +rect 260 448 630 450 +rect 101 383 153 435 +rect 260 402 273 448 +rect 319 402 630 448 +rect 807 432 818 478 +rect 1052 432 1064 478 +rect 903 426 915 432 +rect 967 426 979 432 +rect 260 400 630 402 +rect 101 337 104 383 +rect 150 337 153 383 +rect 101 323 153 337 +rect 580 310 630 400 +rect 580 308 1182 310 +rect 580 262 818 308 +rect 1052 262 1182 308 +rect 580 260 1182 262 +rect 101 244 153 258 +rect 101 198 104 244 +rect 150 198 153 244 +rect 101 139 153 198 +rect 241 116 273 168 +rect 325 116 348 168 +rect 903 138 915 144 +rect 967 138 979 144 +rect 241 110 348 116 +rect 807 92 818 138 +rect 1052 92 1064 138 +rect 1139 68 1186 120 +rect 1238 68 1250 120 +rect 80 36 179 46 +rect 80 -16 111 36 +rect 163 -16 179 36 +rect 80 -24 179 -16 << via1 >> -rect 915 422 967 468 -rect 915 416 967 422 -rect 273 112 319 158 -rect 319 112 325 158 -rect 273 106 325 112 -rect 915 128 967 134 -rect 915 82 967 128 -rect 1186 107 1238 110 -rect 1186 61 1189 107 -rect 1189 61 1235 107 -rect 1235 61 1238 107 -rect 1186 58 1238 61 -rect 111 23 163 26 -rect 111 -23 114 23 -rect 114 -23 160 23 -rect 160 -23 163 23 -rect 111 -26 163 -23 +rect 915 432 967 478 +rect 915 426 967 432 +rect 273 122 319 168 +rect 319 122 325 168 +rect 273 116 325 122 +rect 915 138 967 144 +rect 915 92 967 138 +rect 1186 117 1238 120 +rect 1186 71 1189 117 +rect 1189 71 1235 117 +rect 1235 71 1238 117 +rect 1186 68 1238 71 +rect 111 33 163 36 +rect 111 -13 114 33 +rect 114 -13 160 33 +rect 160 -13 163 33 +rect 111 -16 163 -13 << metal2 >> -rect 271 158 327 520 -rect 271 106 273 158 -rect 325 106 327 158 -rect 271 28 327 106 -rect 89 26 327 28 -rect 89 -26 111 26 -rect 163 -26 327 26 -rect 913 468 969 520 -rect 913 416 915 468 -rect 967 416 969 468 -rect 913 134 969 416 -rect 913 82 915 134 -rect 967 112 969 134 -rect 967 110 1250 112 -rect 967 82 1186 110 -rect 913 58 1186 82 -rect 1238 58 1250 110 -rect 913 56 1250 58 -rect 913 8 969 56 -rect 89 -28 327 -26 +rect 271 168 327 530 +rect 271 116 273 168 +rect 325 116 327 168 +rect 271 38 327 116 +rect 89 36 327 38 +rect 89 -16 111 36 +rect 163 -16 327 36 +rect 913 478 969 530 +rect 913 426 915 478 +rect 967 426 969 478 +rect 913 144 969 426 +rect 913 92 915 144 +rect 967 122 969 144 +rect 967 120 1250 122 +rect 967 92 1186 120 +rect 913 68 1186 92 +rect 1238 68 1250 120 +rect 913 66 1250 68 +rect 913 18 969 66 +rect 89 -18 327 -16 << labels >> -rlabel metal1 s 1156 439 1156 439 4 Y -rlabel metal1 s 127 211 127 211 4 B -rlabel metal1 s 127 350 127 350 4 A -rlabel metal2 s 941 33 941 33 4 VDD -rlabel metal2 s 300 56 300 56 4 GND +rlabel metal2 s 271 38 327 530 4 GND +port 1 nsew +rlabel metal2 s 941 43 941 43 4 VDD +flabel metal1 s 605 425 605 425 2 FreeSans 368 0 0 0 Z +port 2 nsew +flabel metal1 s 127 360 127 360 2 FreeSans 368 0 0 0 A +port 3 nsew +flabel metal1 s 127 221 127 221 2 FreeSans 368 0 0 0 B +port 4 nsew << properties >> -string FIXED_BBOX -17 0 1373 522 +string FIXED_BBOX -17 0 1373 542 << end >> diff --git a/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp index bba3f127..69bfd9d8 100644 --- a/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp +++ b/technology/gf180mcu/sp_lib/gf180mcu_3v3__nand2_1_dec.sp @@ -1,6 +1,6 @@ -.subckt gf180mcu_3v3__nand2_1_dec A B Y VDD GND -X0 VDD B Y VDD pfet_03p3 w=1.7u l=0.3u -X1 Y A VDD VDD pfet_03p3 w=1.7u l=0.3u -X2 a_28_21# A Y GND nfet_03p3 w=0.85u l=0.3u -X3 VSS B a_28_21# GND nfet_03p3 w=0.85u l=0.3u -.ends \ No newline at end of file +.subckt gf180mcu_3v3__nand2_1_dec A B Z VDD GND +X0 VDD B Z VDD pfet_03v3 w=1.7u l=0.3u +X1 Z A VDD VDD pfet_03v3 w=1.7u l=0.3u +X2 a_28_21# A Z GND nfet_03v3 w=0.85u l=0.3u +X3 GND B a_28_21# GND nfet_03v3 w=0.85u l=0.3u +.ends diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index c5db178a..6b30590e 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -52,7 +52,7 @@ cell_properties.bitcell_1port.gnd_layer = "m1" cell_properties.nand2_dec.port_order = ['A', 'B', 'Z', 'vdd', 'gnd'] cell_properties.nand2_dec.port_map = {'A': 'A', 'B': 'B', - 'Z': 'Y', + 'Z': 'Z', 'vdd': 'VDD', 'gnd': 'GND'} @@ -96,6 +96,8 @@ active_stack = ("active", "contact", "m1") m1_stack = ("m1", "via1", "m2") m2_stack = ("m2", "via2", "m3") m3_stack = ("m3", "via3", "m4") +m4_stack = ("m4", "via4", "m5") + layer_indices = {"poly": 0, "active": 0, @@ -104,7 +106,8 @@ layer_indices = {"poly": 0, "m1": 1, "m2": 2, "m3": 3, - "m4": 4} + "m4": 4, + "m5": 5} # The FEOL stacks get us up to m1 feol_stacks = [poly_stack, @@ -113,22 +116,24 @@ feol_stacks = [poly_stack, # The BEOL stacks are m1 and up beol_stacks = [m1_stack, m2_stack, - m3_stack] + m3_stack, + m4_stack] layer_stacks = feol_stacks + beol_stacks preferred_directions = {"poly": "V", "active": "V", - "m1": "H", - "m2": "V", - "m3": "H", - "m4": "V"} + "m1": "V", + "m2": "H", + "m3": "V", + "m4": "H", + "m5": "V"} ################################################### # Power grid ################################################### # Use M3/M4 -power_grid = m3_stack +power_grid = m4_stack ################################################### ##GDS Layer Map @@ -201,8 +206,8 @@ drc = d.design_rules("gf180") drc["grid"] = 0.005 # minwidth_tx with contact (no dog bone transistors) -drc["minwidth_tx"] = 0.5 -# PL.2 Min gate width/channel length for 6V pmos (0.7 for 6V nmos) +drc["minwidth_tx"] = 0.57 +# PL.2 Min gate width/channel length for 3V3 pmos drc["minlength_channel"] = 0.28 drc["minlength_channel_pmos"] = 0.55 @@ -305,7 +310,7 @@ drc.add_enclosure("m1", drc.add_enclosure("m1", layer="via1", enclosure=0, - extension=0.205) + extension=0.15) drc.add_layer("via1", width=0.26, @@ -362,6 +367,23 @@ drc.add_enclosure("m4", layer="via4", enclosure=0.06) +drc.add_layer("via4", + width=0.26, + spacing=0.26) + +# Magic wants 0.36um width but PDK says 0.28 +drc.add_layer("m5", + width=0.36, + spacing=0.28, + area=0.1444) + +drc.add_enclosure("m5", + layer="via4", + enclosure=0.06) + +drc.add_enclosure("m5", + layer="via5", + enclosure=0.06) drc.add_layer("via5", width=0.26, From 3271c5e73c1aceee5a45f22abfccec04add288ff Mon Sep 17 00:00:00 2001 From: SWalker Date: Wed, 13 Sep 2023 21:04:35 -0700 Subject: [PATCH 37/61] fixing drc on rom bank, mostly spacing tweaks --- compiler/modules/pinv_dec.py | 6 +++++- compiler/modules/rom_bank.py | 2 +- compiler/modules/rom_base_array.py | 4 ++-- technology/gf180mcu/tech/tech.py | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py index 1ee75266..a1008c0d 100644 --- a/compiler/modules/pinv_dec.py +++ b/compiler/modules/pinv_dec.py @@ -187,7 +187,11 @@ class pinv_dec(pinv): # Pick point at right most of NMOS and connect over to PMOS nmos_drain_pos = nmos_drain_pin.lc() - right_side = vector(self.width, nmos_drain_pos.y) + + if self.flip_io: + right_side = vector(self.pmos_inst.get_pin("D").cx(), nmos_drain_pos.y) + else: + right_side = vector(self.width, nmos_drain_pos.y) self.add_layout_pin_segment_center("Z", self.route_layer, diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py index 244cbe16..9148766c 100644 --- a/compiler/modules/rom_bank.py +++ b/compiler/modules/rom_bank.py @@ -297,7 +297,7 @@ class rom_bank(design,rom_verilog): def place_bitline_inverter(self): self.bitline_inv_inst.place(offset=[0,0], rotate=90) - inv_y_offset = self.array_inst.by() - self.bitline_inv_inst.width - 2 * self.m1_pitch + inv_y_offset = self.array_inst.by() - self.bitline_inv_inst.width - 1.5 * self.m1_pitch inv_x_offset = self.array_inst.get_pin("bl_0_0").cx() - self.bitline_inv_inst.get_pin("out_0").cx() self.inv_offset = vector(inv_x_offset, inv_y_offset) diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 8ae7ea56..981375e4 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -234,12 +234,12 @@ class rom_base_array(bitcell_base_array): bottom = vector(pin.cx(), pin.by()) top = vector(pin.cx(), gnd_y) self.add_via_stack_center(offset=top, from_layer=self.bitline_layer, to_layer=self.supply_stack[0]) - self.add_via_center(offset=bottom, layers=self.supply_stack) + # self.add_via_center(offset=bottom, layers=self.supply_stack) self.add_layout_pin_rect_ends(name="gnd", layer=self.supply_stack[0], start=bottom, end=top) self.remove_layout_pin("gnd_tmp") - self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y)) + # self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y)) self.add_segment_center(layer=self.bitline_layer, start=gnd_l, end=vector(min_x, gnd_l.y)) self.add_segment_center(layer=self.bitline_layer, start=gnd_r, end=vector(max_x, gnd_r.y)) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 6b30590e..6aa1141b 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -299,7 +299,7 @@ drc["poly_contact_to_gate"] = 0.165 # M1.2a - space # M1.3 - area drc.add_layer("m1", - width=0.23, + width=0.26, spacing=0.23) drc.add_enclosure("m1", From 565e3f6814ed3e870c5bd87030e4d6eb6850219d Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:27:47 -0700 Subject: [PATCH 38/61] flatten ptx in extraction and renumber test based on importance --- compiler/tests/05_rom_array_test.py | 43 +++++++++++++++++++++++++++++ technology/gf180mcu/tech/tech.py | 5 +++- 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100755 compiler/tests/05_rom_array_test.py diff --git a/compiler/tests/05_rom_array_test.py b/compiler/tests/05_rom_array_test.py new file mode 100755 index 00000000..80e188af --- /dev/null +++ b/compiler/tests/05_rom_array_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class rom_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + debug.info(2, "Testing 4x4 array for rom cell") + + + # data = [[1, 0, 0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 0, 0, 1, 0, 0], [0, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 0, 1, 0, 0, 0, 1, 0]] + + + data = [[1, 0, 0], [1, 1, 1], [0,1, 0]] + a = factory.create(module_type="rom_base_array", cols=3, rows=3, bitmap=data, strap_spacing=1, pitch_match=True) + self.local_check(a) + a.sp_write(OPTS.openram_temp + 'simulation_file.sp') + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index 6aa1141b..fc34de2a 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -416,7 +416,7 @@ spice["pmos"] = "pfet_03v3" spice["power"]="vccd1" spice["ground"]="vssd1" -spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]]} +spice["fet_libraries"] = {"TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sm141064.ngspice", "typical"]]} # spice stimulus related variables spice["feasible_period"] = 10 # estimated feasible period in ns @@ -477,4 +477,7 @@ drc_name = "magic" lvs_name = "netgen" pex_name = "magic" + +flatglob = ["*_?mos_m*"] + ignore_drc_lvs_on = ["wl_strap"] From 4b3af3872743058776fcdc97b18d48d7a0a9c7ab Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:29:17 -0700 Subject: [PATCH 39/61] change min rail to contact spacing for long gf180 contact extend --- compiler/modules/pgate.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/compiler/modules/pgate.py b/compiler/modules/pgate.py index 8f21819a..1cfed389 100644 --- a/compiler/modules/pgate.py +++ b/compiler/modules/pgate.py @@ -48,6 +48,11 @@ class pgate(design): # This is the space from a S/D contact to the supply rail contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space + + # This is a result of the m1 extend contact drc rule being really long in comparison to sky130. + # Currently the "extend" drc rule acts to fulfil minimum metal areas on contacts and isnt reflective of an actual drc rule + if OPTS.tech_name == "gf180mcu": + contact_to_vdd_rail_space += 0.5 * self.route_layer_space # This is a poly-to-poly of a flipped cell poly_to_poly_gate_space = self.poly_extend_active + 0.5 * self.poly_space From 5c22e382b5608eb4d88585f46e485148f19eb754 Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:31:45 -0700 Subject: [PATCH 40/61] add parameter to make routing horizonal vdd rails easier --- compiler/base/hierarchy_layout.py | 28 +++++++++++++++---------- compiler/modules/rom_precharge_array.py | 11 +++++++++- 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 58cf1a81..05b8603a 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -942,14 +942,19 @@ class layout(): return (bot_rect, top_rect) - def route_horizontal_pins(self, name, insts=None, layer=None, xside="cx", yside="cy", full_width=True): + def route_horizontal_pins(self, name, insts=None, layer=None, xside="cx", yside="cy", full_width=True, new_name=None): """ Route together all of the pins of a given name that horizontally align. Uses local_insts if insts not specified. Uses center of pin by default, or top or botom if specified. + New top level pin can be renamed with new_name, otherwise the new pin will keep the same name as old pins TODO: Add equally spaced option for IR drop min, right now just 2 """ + if new_name is not None: + pin_name = new_name + else: + pin_name = name bins = {} if not insts: @@ -1009,16 +1014,17 @@ class layout(): left_pos = vector(left_x + 0.5 * via_width, y) right_pos = vector(right_x + 0.5 * via_width, y) -# self.add_layout_pin_rect_ends(name=name, -# layer=pin_layer, -# start=left_pos, -# end=right_pos, -# width=via_height) - self.add_layout_pin_segment_center(text=name, - layer=pin_layer, - start=left_pos, - end=right_pos, - width=via_height) + # self.add_layout_pin_rect_ends(name=name, + # layer=pin_layer, + # start=left_pos, + # end=right_pos, + # width=via_height) + + self.add_layout_pin_segment_center(text=pin_name, + layer=pin_layer, + start=left_pos, + end=right_pos, + width=via_height) def add_layout_end_pin_segment_center(self, text, layer, start, end): """ diff --git a/compiler/modules/rom_precharge_array.py b/compiler/modules/rom_precharge_array.py index 0aad55be..716ab807 100644 --- a/compiler/modules/rom_precharge_array.py +++ b/compiler/modules/rom_precharge_array.py @@ -134,7 +134,16 @@ class rom_precharge_array(design): self.add_layout_pin_rect_center(bl, self.bitline_layer, source_pin.center()) def route_supply(self): - self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer) + + # Hacky way to route all the vdd pins together and then create a layout pin on only one side. + self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer, new_name="vdd_tmp") + + tmp_vdd = self.get_pin("vdd_tmp") + + self.add_layout_pin_rect_center("vdd", layer=self.strap_layer, offset=tmp_vdd.lc(), height=tmp_vdd.height()) + self.add_segment_center(layer=self.strap_layer, start=tmp_vdd.lc(), end=tmp_vdd.rc(), width=tmp_vdd.height()) + self.remove_layout_pin("vdd_tmp") + def connect_taps(self): array_pins = [self.tap_insts[i].get_pin("poly_tap") for i in range(len(self.tap_insts))] From ddba3b371823848c1d87fd6b8933221b051fbecf Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:33:49 -0700 Subject: [PATCH 41/61] move vdd pins around to make routing nice --- compiler/modules/rom_address_control_array.py | 13 ++++++++++++- compiler/modules/rom_address_control_buf.py | 3 --- compiler/modules/rom_wordline_driver_array.py | 10 ++++------ 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/compiler/modules/rom_address_control_array.py b/compiler/modules/rom_address_control_array.py index dc4cbf2e..a7e45fe6 100644 --- a/compiler/modules/rom_address_control_array.py +++ b/compiler/modules/rom_address_control_array.py @@ -119,4 +119,15 @@ class rom_address_control_array(design): for pin in tmp_pins: self.copy_layout_pin(self, "vdd_edge", "vdd") - self.remove_layout_pin("vdd_edge") \ No newline at end of file + self.remove_layout_pin("vdd_edge") + + tmp_pins = [] + for pin in self.get_pins("gnd"): + edge = vector(pin.rx() + 0.5 * self.route_width, pin.cy()) + tmp_pins.append(self.add_layout_pin_rect_center("gnd_edge", layer=self.route_layer, offset=edge)) + self.copy_layout_pin_shapes("gnd") + self.remove_layout_pin("gnd") + + for pin in tmp_pins: + self.copy_layout_pin(self, "gnd_edge", "gnd") + self.remove_layout_pin("gnd_edge") \ No newline at end of file diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py index 6c7d11ea..4a413ce0 100644 --- a/compiler/modules/rom_address_control_buf.py +++ b/compiler/modules/rom_address_control_buf.py @@ -127,8 +127,6 @@ class rom_address_control_buf(design): poly_y = A_out.cy() contact_offset = vector(ppoly_center, clk2_pin.cy()) - self.add_layout_pin_rect_center("cont", offset=contact_offset, layer="poly") - self.add_layout_pin_rect_center("ppoly", offset=vector(ppoly_center, poly_y), layer="poly") # Route the two shared clk inputs together by connecting poly self.add_segment_center("poly", contact_offset, vector(ppoly_center, poly_y)) @@ -180,7 +178,6 @@ class rom_address_control_buf(design): left_edge = self.inv_inst.get_pin("Z").cx() - 2 * self.contact_width - 2 * self.active_contact_to_gate - 4 * self.active_enclose_contact - self.poly_width - self.active_space contact_pos = vector(left_edge, source_pin.cy()) - self.add_layout_pin_rect_center("left_edge", offset=contact_pos, layer="m1") self.add_via_center(layers=self.active_stack, offset=contact_pos, implant_type="n", diff --git a/compiler/modules/rom_wordline_driver_array.py b/compiler/modules/rom_wordline_driver_array.py index c77cfdae..d6b42249 100644 --- a/compiler/modules/rom_wordline_driver_array.py +++ b/compiler/modules/rom_wordline_driver_array.py @@ -88,8 +88,6 @@ class rom_wordline_driver_array(design): Add a pin for each row of vdd/gnd which are must-connects next level up. """ - # self.route_vertical_pins("vdd", self.wld_inst, xside="cx", layer=self.supply_layer) - # self.route_vertical_pins("gnd", self.wld_inst, xside="cx", layer=self.supply_layer) if not self.invert_outputs: vdd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("vdd")] gnd_pins = [pin for inst in self.wld_inst for pin in inst.get_pins("gnd")] @@ -110,13 +108,13 @@ class rom_wordline_driver_array(design): # Place the top level supply pins on the edge of the module for pin in self.get_pins("gnd_tmp"): - bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width) - top = vector(pin.cx(), pin.uy() + 0.5 * supply_width) + bottom = vector(pin.cx(), pin.by()) + top = vector(pin.cx(), pin.uy()) self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="gnd") for pin in self.get_pins("vdd_tmp"): - bottom = vector(pin.cx(), pin.by() - 0.5 * supply_width) - top = vector(pin.cx(), pin.uy() + 0.5 * supply_width) + bottom = vector(pin.cx(), pin.by()) + top = vector(pin.cx(), pin.uy()) self.add_layout_pin_rect_ends(layer=self.supply_layer, start=bottom, end=top, name="vdd") From 9b99e6c1249d36fc88eddb5a252ea9d71fdebd74 Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:36:57 -0700 Subject: [PATCH 42/61] bunch of cleanups to core rom classes --- compiler/modules/rom_bank.py | 74 +++++++++++++++----------- compiler/modules/rom_base_array.py | 9 ++-- compiler/modules/rom_base_cell.py | 1 - compiler/modules/rom_decoder.py | 8 +++ compiler/modules/rom_poly_tap.py | 9 +--- compiler/modules/rom_precharge_cell.py | 4 -- 6 files changed, 56 insertions(+), 49 deletions(-) diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py index 9148766c..56a24740 100644 --- a/compiler/modules/rom_bank.py +++ b/compiler/modules/rom_bank.py @@ -113,8 +113,7 @@ class rom_bank(design,rom_verilog): # FIXME: Somehow ROM layout behaves weird and doesn't add all the pin # shapes before routing supplies init_bbox = self.get_bbox() - if OPTS.route_supplies: - self.route_supplies(init_bbox) + self.route_supplies(init_bbox) # Route the pins to the perimeter if OPTS.perimeter_pins: # We now route the escape routes far enough out so that they will @@ -368,8 +367,11 @@ class rom_bank(design,rom_verilog): # Route precharge to col decoder start = prechrg_control.center() - mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, prechrg_control.cy()) - mid2 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, col_decode_prechrg.cy()) + + path_x = self.control_inst.rx() + 1.2 * self.route_layer_pitch + + mid1 = vector(path_x, prechrg_control.cy()) + mid2 = vector(path_x, col_decode_prechrg.cy()) end = col_decode_prechrg.center() self.add_path(self.route_stack[0], [start, mid1, mid2, end]) @@ -378,7 +380,7 @@ class rom_bank(design,rom_verilog): offset=end) start = mid1 - mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, start.y) + mid1 = vector(path_x, start.y) mid2 = vector(mid1.x, col_decode_clk.cy()) end = col_decode_clk.center() self.add_path(self.route_stack[0], [start, mid1, mid2, end]) @@ -388,6 +390,10 @@ class rom_bank(design,rom_verilog): mid = vector(col_decode_prechrg.cx(), array_prechrg.cy() ) self.add_path(self.route_stack[0], [array_prechrg.center(), mid, col_decode_prechrg.center()]) + self.add_via_stack_center(from_layer=self.route_stack[0], + to_layer=array_prechrg.layer, + offset=array_prechrg.center()) + def route_clock(self): clk_out = self.control_inst.get_pin("clk_out") @@ -409,6 +415,10 @@ class rom_bank(design,rom_verilog): to_layer=row_decode_clk.layer, offset=addr_control_clk) + self.add_via_stack_center(from_layer=self.route_stack[2], + to_layer=row_decode_prechrg.layer, + offset=row_decode_prechrg.center()) + self.add_segment_center(row_decode_clk.layer, addr_control_clk, row_decode_clk.rc()) def route_array_outputs(self): @@ -417,7 +427,7 @@ class rom_bank(design,rom_verilog): inv_out_pins = [self.bitline_inv_inst.get_pin("out_{}".format(bl)) for bl in range(self.cols)] mux_pins = [self.mux_inst.get_pin("bl_{}".format(bl)) for bl in range(self.cols)] - self.connect_col_pins(self.interconnect_layer, array_out_pins + inv_in_pins, round=True, directions="nonpref") + self.connect_col_pins(self.route_stack[2], array_out_pins + inv_in_pins, round=True, directions="nonpref") self.connect_col_pins(self.interconnect_layer, inv_out_pins + mux_pins, round=True, directions="nonpref") def route_output_buffers(self): @@ -450,34 +460,36 @@ class rom_bank(design,rom_verilog): for inst in self.insts: self.copy_power_pins(inst, pin_name) - from openram.router import supply_router as router - rtr = router(layers=self.supply_stack, - design=self, - bbox=bbox, - pin_type=OPTS.supply_pin_type) - rtr.route() + if OPTS.route_supplies: - if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]: - # Find the lowest leftest pin for vdd and gnd - for pin_name in ["vdd", "gnd"]: - # Copy the pin shape(s) to rectangles - for pin in self.get_pins(pin_name): - self.add_rect(layer=pin.layer, - offset=pin.ll(), - width=pin.width(), - height=pin.height()) + from openram.router import supply_router as router + rtr = router(layers=self.supply_stack, + design=self, + bbox=bbox, + pin_type=OPTS.supply_pin_type) + rtr.route() - # Remove the pin shape(s) - self.remove_layout_pin(pin_name) + if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]: + # Find the lowest leftest pin for vdd and gnd + for pin_name in ["vdd", "gnd"]: + # Copy the pin shape(s) to rectangles + for pin in self.get_pins(pin_name): + self.add_rect(layer=pin.layer, + offset=pin.ll(), + width=pin.width(), + height=pin.height()) - # Get new pins - pins = rtr.get_new_pins(pin_name) - for pin in pins: - self.add_layout_pin(pin_name, - pin.layer, - pin.ll(), - pin.width(), - pin.height()) + # Remove the pin shape(s) + self.remove_layout_pin(pin_name) + + # Get new pins + pins = rtr.get_new_pins(pin_name) + for pin in pins: + self.add_layout_pin(pin_name, + pin.layer, + pin.ll(), + pin.width(), + pin.height()) def route_escape_pins(self, bbox): pins_to_route = [] diff --git a/compiler/modules/rom_base_array.py b/compiler/modules/rom_base_array.py index 981375e4..3a0848ee 100644 --- a/compiler/modules/rom_base_array.py +++ b/compiler/modules/rom_base_array.py @@ -22,7 +22,9 @@ class rom_base_array(bitcell_base_array): self.data = bitmap self.tap_direction = tap_direction - self.pitch_match = pitch_match + # This attribute is redundant with the tap direction + # TODO: consolidate pitch matching logic to just be based on tap direction + self.pitch_match = tap_direction == "row" self.bitline_layer = bitline_layer self.strap_spacing = strap_spacing self.wordline_layer = wordline_layer @@ -89,7 +91,6 @@ class rom_base_array(bitcell_base_array): self.poly_tap = factory.create(module_type="rom_poly_tap", add_active_tap=True) self.end_poly_tap = factory.create(module_type="rom_poly_tap", place_poly=True) - print("poly tap width", self.poly_tap.width, "height", self.poly_tap.height, self.tap_direction) self.precharge_array = factory.create(module_type="rom_precharge_array", cols=self.column_size, strap_spacing=self.strap_spacing, @@ -102,7 +103,6 @@ class rom_base_array(bitcell_base_array): self.route_pitch = drc("{0}_to_{0}".format(self.bitline_layer)) def add_pins(self): - print(self.get_wordline_names()) for bl_name in self.get_bitline_names(): self.add_pin(bl_name, "OUTPUT") for wl_name in self.get_wordline_names(): @@ -234,12 +234,10 @@ class rom_base_array(bitcell_base_array): bottom = vector(pin.cx(), pin.by()) top = vector(pin.cx(), gnd_y) self.add_via_stack_center(offset=top, from_layer=self.bitline_layer, to_layer=self.supply_stack[0]) - # self.add_via_center(offset=bottom, layers=self.supply_stack) self.add_layout_pin_rect_ends(name="gnd", layer=self.supply_stack[0], start=bottom, end=top) self.remove_layout_pin("gnd_tmp") - # self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y)) self.add_segment_center(layer=self.bitline_layer, start=gnd_l, end=vector(min_x, gnd_l.y)) self.add_segment_center(layer=self.bitline_layer, start=gnd_r, end=vector(max_x, gnd_r.y)) @@ -333,7 +331,6 @@ class rom_base_array(bitcell_base_array): else: output_layer = "m3" rail_y = self.precharge_inst.get_pins("vdd")[0].cy() - print("cols ", self.bitline_names[0]) for bl in range(self.column_size): src_pin = self.cell_list[0][bl].get_pin("S") diff --git a/compiler/modules/rom_base_cell.py b/compiler/modules/rom_base_cell.py index 1f47b88f..da57ff23 100644 --- a/compiler/modules/rom_base_cell.py +++ b/compiler/modules/rom_base_cell.py @@ -80,7 +80,6 @@ class rom_base_cell(design): self.cell_inst = self.add_inst( name=self.name + "_nmos", mod=self.nmos, ) - print("bitmos", self.cell_inst.height, self.cell_inst.width) if self.bit_value == 0: self.connect_inst(["bl", "wl", "bl", "gnd"]) diff --git a/compiler/modules/rom_decoder.py b/compiler/modules/rom_decoder.py index 4540aadd..8ea798a6 100644 --- a/compiler/modules/rom_decoder.py +++ b/compiler/modules/rom_decoder.py @@ -231,6 +231,14 @@ class rom_decoder(design): self.add_path(self.inv_route_layer, [addr_out_pin.center(), addr_middle, addr_pin.center()]) self.add_path(self.inv_route_layer, [addr_bar_out_pin.center(), addr_bar_middle, addr_bar_pin.center()]) + + self.add_via_stack_center(offset=addr_pin.center(), + from_layer=addr_pin.layer, + to_layer=self.inv_route_layer) + + self.add_via_stack_center(offset=addr_bar_pin.center(), + from_layer=addr_bar_pin.layer, + to_layer=self.inv_route_layer) self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i)) def route_supplies(self): diff --git a/compiler/modules/rom_poly_tap.py b/compiler/modules/rom_poly_tap.py index e5bb288c..803211e4 100644 --- a/compiler/modules/rom_poly_tap.py +++ b/compiler/modules/rom_poly_tap.py @@ -35,7 +35,6 @@ class rom_poly_tap(design): def create_layout(self): self.place_via() - # self.extend_poly() if self.add_tap or self.place_poly: self.place_active_tap() @@ -47,7 +46,6 @@ class rom_poly_tap(design): contact_width = self.poly_contact.width self.height = self.dummy.height self.width = contact_width + self.pitch_offset - print("pitch off", self.pitch_offset) super().add_boundary() def place_via(self): @@ -83,12 +81,9 @@ class rom_poly_tap(design): tap_y = self.via.cy() + self.dummy.width * 0.5 contact_pos = vector(tap_x, tap_y) - # edge of the next nmos - active_edge = self.dummy.width - self.dummy.cell_inst.height - self.poly_extend_active - # edge of the active contact - tap_edge = tap_x + 0.5 * self.active_contact.height - self.pitch_offset += (self.active_space * 2) - (tap_edge - active_edge) + self.contact_x_offset + # This pitch offset is used throughout the memory bank to make sure the pitch of the decoder outputs matches the pitch of the array inputs + self.pitch_offset = 0.5 * self.active_contact.width + self.active_space + 0.5 * self.contact_width + self.active_enclose_contact if self.tx_type == "nmos" and self.add_tap: self.add_via_center(layers=self.active_stack, diff --git a/compiler/modules/rom_precharge_cell.py b/compiler/modules/rom_precharge_cell.py index 6a2f4ac7..f9517b6b 100644 --- a/compiler/modules/rom_precharge_cell.py +++ b/compiler/modules/rom_precharge_cell.py @@ -24,7 +24,6 @@ class rom_precharge_cell(rom_base_cell): self.place_tap() self.extend_well() - print("precharge", self.height, self.width) def add_modules(self): @@ -44,7 +43,6 @@ class rom_precharge_cell(rom_base_cell): self.cell_inst = self.add_inst( name="precharge_pmos", mod=self.pmos, ) - print("premos", self.cell_inst.height, self.cell_inst.width) self.connect_inst(["bitline", "gate", "vdd", "vdd"]) def add_pins(self): @@ -58,7 +56,6 @@ class rom_precharge_cell(rom_base_cell): self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active) def extend_well(self): - print(self.nwell_enclose_active) well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active well_ll = vector(0, well_y) height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y @@ -91,5 +88,4 @@ class rom_precharge_cell(rom_base_cell): pass def short_gate(self): - print("not shorting") pass \ No newline at end of file From 1f35855c6dadb92c4055d0846a4bb41b0720a4e2 Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 14 Sep 2023 21:48:40 -0700 Subject: [PATCH 43/61] remove old rom test --- compiler/tests/14_rom_array_test.py | 43 ----------------------------- 1 file changed, 43 deletions(-) delete mode 100755 compiler/tests/14_rom_array_test.py diff --git a/compiler/tests/14_rom_array_test.py b/compiler/tests/14_rom_array_test.py deleted file mode 100755 index 80e188af..00000000 --- a/compiler/tests/14_rom_array_test.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2023 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import sys, os -import unittest -from testutils import * - -import openram -from openram import debug -from openram.sram_factory import factory -from openram import OPTS - - -class rom_array_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - openram.init_openram(config_file, is_unit_test=True) - - debug.info(2, "Testing 4x4 array for rom cell") - - - # data = [[1, 0, 0, 1, 0, 0, 1, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 0, 0, 1, 0, 0], [0, 0, 0, 0, 1, 0, 0, 0, 1], [0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 0, 0, 0, 0, 0, 1, 0], [0, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 0, 1, 0, 0, 0, 1, 0]] - - - data = [[1, 0, 0], [1, 1, 1], [0,1, 0]] - a = factory.create(module_type="rom_base_array", cols=3, rows=3, bitmap=data, strap_spacing=1, pitch_match=True) - self.local_check(a) - a.sp_write(OPTS.openram_temp + 'simulation_file.sp') - - openram.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = openram.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) From b65ebc61603aadfd64c34b91cbb1ad01f43dce54 Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Fri, 7 Apr 2023 14:56:18 -0700 Subject: [PATCH 44/61] corrected the import statement and removed strap variant attribute which is no longer needed --- technology/gf180mcu/tech/tech.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py index fc34de2a..ed54979c 100644 --- a/technology/gf180mcu/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -6,7 +6,7 @@ # All rights reserved. # import os -import drc as d +from openram import drc as d """ File containing the process technology parameters for Global Foundaries 180nm @@ -59,7 +59,6 @@ cell_properties.nand2_dec.port_map = {'A': 'A', cell_properties.ptx.model_is_subckt = True -cell_properties.use_strap = True cell_properties.strap_placement = 8 # this means strap cell gets placed after every 8 bitcells cell_properties.names["nand2_dec"] = ["gf180mcu_3v3__nand2_1_dec"] From 042bfcabea9a6fc4c1f5f119e8255a3ea26aa894 Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Sun, 22 Jan 2023 18:18:45 -0800 Subject: [PATCH 45/61] added the custom cell definition --- technology/gf180mcu/custom/gf180_bitcell.py | 31 +++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 technology/gf180mcu/custom/gf180_bitcell.py diff --git a/technology/gf180mcu/custom/gf180_bitcell.py b/technology/gf180mcu/custom/gf180_bitcell.py new file mode 100644 index 00000000..91be2e1b --- /dev/null +++ b/technology/gf180mcu/custom/gf180_bitcell.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California +# All rights reserved. +# + +from openram import debug +from openram.modules import bitcell_base +from openram.tech import cell_properties as props + + +class gf180_bitcell(bitcell_base): + """ + A single bit cell (6T, 8T, etc.) This module implements the + single memory cell used in the design. It is a hand-made cell, so + the layout and netlist should be available in the technology + library. + """ + + def __init__(self, version="opt1", name=""): + cell_name = "cell1rw" + super().__init__(name, cell_name=cell_name, prop=props.bitcell_1port) + debug.info(2, "Create bitcell") + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) From 98a4210b06ed69e162791dc63ff0ef6915ef8c49 Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Sun, 22 Jan 2023 16:37:52 -0800 Subject: [PATCH 46/61] added the gds and spice of the bitcell --- technology/gf180mcu/gds_lib/cell1rw.gds | Bin 0 -> 2996 bytes technology/gf180mcu/sp_lib/cell1rw.sp | 11 +++++++++++ 2 files changed, 11 insertions(+) create mode 100644 technology/gf180mcu/gds_lib/cell1rw.gds create mode 100644 technology/gf180mcu/sp_lib/cell1rw.sp diff --git a/technology/gf180mcu/gds_lib/cell1rw.gds b/technology/gf180mcu/gds_lib/cell1rw.gds new file mode 100644 index 0000000000000000000000000000000000000000..d8149eb9c7615fa0499e17efa118770770e5521b GIT binary patch literal 2996 zcmbW3J!n%=6vxkdNpAAe)F!c3D#ec~1x0F8k;X+-iY=O!qSA^89kdQ5mQulrgNT!& zIEXk@D58Q6;!qr%96C6OgM)~J6cR$mnTd(1@k0mq42_pY#!J2Bv*n@k*ieaD z6RBN$F83XHcK`Fv{wLdR-#U7jI#TgI*BAqjzN6z4)oMw6ohp|onISUGE_ISw;Sy0L zpTPg8Fg_QyOc7<;h?GrpSi480Z2m#y_7Evm2PO+t=l>Y{_b!QlX67wX;!eQa0#T}! zNSPgx{YuUw`%Us;ay;v=Q9PWdR;yKzl@Ua9u{T$~Y-Dja zlxhd#<3q=}vz~Kjy;AL9te*SHahM#}c@KPzmb!@#XwXBm zKcL#d*!)>n=n{R=6}?jJV5~mz5dBA7W^NcWhc`p1b}+1Ov-5Y=pK88a-8et)R`!J4 z4WZaG50%Ifv*GdEU}+xNvs$KlWlhQJ&Jy-mvMzxd3pK9KM)_4FKfIkEB)|M_(JG54 zCBBmFe7BXV1H=B;hVP$y20mZn-hqV<)bB+=wS%#G^HKCn)_Z#cvfi%8=yCQ6YLpZv z4SH8a4whzr)KXGVNxp63MkMIBTu;6TOrVQ4uw5hC`v+nGyZ8 zuXhMet7`&vi+BVZ?X1R+|DnPPmAZqBhPV^1g;Ttx>AoXRJOwFZYbo?~edatc@{9f-I_Rjlz4@T;`B{&yiR(Otu%~0?RDAkU)#Xpyg z1${IxsK4UndeC47)`erCzm)6p`}|uE13P*WuHmZx)!SU5ugi57uk>rmwwtM0{NO?> zL%)SK2JuksDo%Eui8tUP-j8Xe+I`0AGlQ}(GblQ*qEvgG9?kH7>;3P{hxCXQ`YYVP u`}73wgJozbod5H<_gOc!BFZU0?62A20RqcRY>0CFvJ3<{+>D literal 0 HcmV?d00001 diff --git a/technology/gf180mcu/sp_lib/cell1rw.sp b/technology/gf180mcu/sp_lib/cell1rw.sp new file mode 100644 index 00000000..2a199681 --- /dev/null +++ b/technology/gf180mcu/sp_lib/cell1rw.sp @@ -0,0 +1,11 @@ +* NGSPICE file created from 018SRAM_cell1_128x8m81.ext - technology: gf180mcuC + +.subckt x018SRAM_cell1_128x8m81 VDD WL GND BL BR nwell pwell +X0 GND a_63_149# a_18_103# pwell nmos_6p0 w=0.95u l=0.6u +X1 a_18_103# WL BL pwell nmos_6p0 w=0.6u l=0.77u +X2 a_63_149# a_18_103# VDD nwell pmos_6p0 w=0.6u l=0.6u +X3 a_63_149# WL BR pwell nmos_6p0 w=0.6u l=0.77u +X4 VDD a_63_149# a_18_103# nwell pmos_6p0 w=0.6u l=0.6u +X5 a_63_149# a_18_103# GND pwell nmos_6p0 w=0.95u l=0.6u +.ends + From 4b4153bdea6ff2e85d5989bf1422d6876a0c9b56 Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Sun, 22 Jan 2023 18:20:10 -0800 Subject: [PATCH 47/61] renamed the gds and sp file to reflect the cell name --- .../{cell1rw.gds => 018SRAM_cell1_128x8m81.gds} | Bin .../{cell1rw.sp => 018SRAM_cell1_128x8m81.sp} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename technology/gf180mcu/gds_lib/{cell1rw.gds => 018SRAM_cell1_128x8m81.gds} (100%) rename technology/gf180mcu/sp_lib/{cell1rw.sp => 018SRAM_cell1_128x8m81.sp} (100%) diff --git a/technology/gf180mcu/gds_lib/cell1rw.gds b/technology/gf180mcu/gds_lib/018SRAM_cell1_128x8m81.gds similarity index 100% rename from technology/gf180mcu/gds_lib/cell1rw.gds rename to technology/gf180mcu/gds_lib/018SRAM_cell1_128x8m81.gds diff --git a/technology/gf180mcu/sp_lib/cell1rw.sp b/technology/gf180mcu/sp_lib/018SRAM_cell1_128x8m81.sp similarity index 100% rename from technology/gf180mcu/sp_lib/cell1rw.sp rename to technology/gf180mcu/sp_lib/018SRAM_cell1_128x8m81.sp From 561e0c228c105e1df28413d519b1c3b7a085b3e0 Mon Sep 17 00:00:00 2001 From: hadirkhan10 Date: Mon, 23 Jan 2023 17:56:43 -0800 Subject: [PATCH 48/61] updated the cell name for layout and schematic --- ...018SRAM_cell1_128x8m81.gds => cell1rw.gds} | Bin 2996 -> 2982 bytes .../{018SRAM_cell1_128x8m81.sp => cell1rw.sp} | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename technology/gf180mcu/gds_lib/{018SRAM_cell1_128x8m81.gds => cell1rw.gds} (89%) rename technology/gf180mcu/sp_lib/{018SRAM_cell1_128x8m81.sp => cell1rw.sp} (87%) diff --git a/technology/gf180mcu/gds_lib/018SRAM_cell1_128x8m81.gds b/technology/gf180mcu/gds_lib/cell1rw.gds similarity index 89% rename from technology/gf180mcu/gds_lib/018SRAM_cell1_128x8m81.gds rename to technology/gf180mcu/gds_lib/cell1rw.gds index d8149eb9c7615fa0499e17efa118770770e5521b..70b18d37060dd05a074b9e6b41a9e36a0ef40ddc 100644 GIT binary patch delta 78 zcmdlYzD!(+fsKKQDS| delta 92 zcmZ1`zC~P#fsKKQDS|Lq`Tzg` diff --git a/technology/gf180mcu/sp_lib/018SRAM_cell1_128x8m81.sp b/technology/gf180mcu/sp_lib/cell1rw.sp similarity index 87% rename from technology/gf180mcu/sp_lib/018SRAM_cell1_128x8m81.sp rename to technology/gf180mcu/sp_lib/cell1rw.sp index 2a199681..86d88176 100644 --- a/technology/gf180mcu/sp_lib/018SRAM_cell1_128x8m81.sp +++ b/technology/gf180mcu/sp_lib/cell1rw.sp @@ -1,6 +1,6 @@ * NGSPICE file created from 018SRAM_cell1_128x8m81.ext - technology: gf180mcuC -.subckt x018SRAM_cell1_128x8m81 VDD WL GND BL BR nwell pwell +.subckt cell1rw VDD WL GND BL BR nwell pwell X0 GND a_63_149# a_18_103# pwell nmos_6p0 w=0.95u l=0.6u X1 a_18_103# WL BL pwell nmos_6p0 w=0.6u l=0.77u X2 a_63_149# a_18_103# VDD nwell pmos_6p0 w=0.6u l=0.6u From bd9ebc3300c4e0efb5a711095082c06881aab8e4 Mon Sep 17 00:00:00 2001 From: Hadir Khan Date: Mon, 13 Mar 2023 13:41:54 -0700 Subject: [PATCH 49/61] updated the spice file --- technology/gf180mcu/sp_lib/cell1rw.sp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/technology/gf180mcu/sp_lib/cell1rw.sp b/technology/gf180mcu/sp_lib/cell1rw.sp index 86d88176..7070979a 100644 --- a/technology/gf180mcu/sp_lib/cell1rw.sp +++ b/technology/gf180mcu/sp_lib/cell1rw.sp @@ -1,11 +1,11 @@ -* NGSPICE file created from 018SRAM_cell1_128x8m81.ext - technology: gf180mcuC +* NGSPICE file created from cell1rw.ext - technology: gf180mcuC -.subckt cell1rw VDD WL GND BL BR nwell pwell -X0 GND a_63_149# a_18_103# pwell nmos_6p0 w=0.95u l=0.6u -X1 a_18_103# WL BL pwell nmos_6p0 w=0.6u l=0.77u -X2 a_63_149# a_18_103# VDD nwell pmos_6p0 w=0.6u l=0.6u -X3 a_63_149# WL BR pwell nmos_6p0 w=0.6u l=0.77u -X4 VDD a_63_149# a_18_103# nwell pmos_6p0 w=0.6u l=0.6u -X5 a_63_149# a_18_103# GND pwell nmos_6p0 w=0.95u l=0.6u +.subckt cell1rw BL BR GND VDD nwell pwell WL +X0 GND a_63_149# a_18_103# pwell nfet_06v0 ad=0.627p pd=3.74u as=0.7275p ps=4.76u w=0.95u l=0.6u +X1 a_18_103# WL BL pwell nfet_06v0 ad=0p pd=0u as=0.282p ps=2.14u w=0.6u l=0.77u +X2 a_63_149# a_18_103# VDD nwell pfet_06v0 ad=0.27p pd=2.1u as=0.489p ps=3.38u w=0.6u l=0.6u +X3 a_63_149# WL BR pwell nfet_06v0 ad=0.7275p pd=4.76u as=0.282p ps=2.14u w=0.6u l=0.77u +X4 VDD a_63_149# a_18_103# nwell pfet_06v0 ad=0p pd=0u as=0.27p ps=2.1u w=0.6u l=0.6u +X5 a_63_149# a_18_103# GND pwell nfet_06v0 ad=0p pd=0u as=0p ps=0u w=0.95u l=0.6u .ends From 5378a308c1deb4b4b33cfea1b44feab9e218c454 Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 26 Oct 2023 21:56:13 -0700 Subject: [PATCH 50/61] updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing --- .gitignore | 4 ++++ compiler/modules/rom_address_control_buf.py | 6 +++--- compiler/modules/rom_decoder.py | 11 ++++++++++- compiler/tests/Makefile | 2 +- 4 files changed, 18 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index cb5e29e1..07af627d 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,10 @@ openram.egg-info/ miniconda/ sky130A/ sky130B/ +gf180mcuA/ +gf180mcuB/ +gf180mcuC/ +gf180mcuD/ skywater-pdk/ sky130_fd_bd_sram/ docker/openram-ubuntu.log diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py index 4a413ce0..d3b1dd47 100644 --- a/compiler/modules/rom_address_control_buf.py +++ b/compiler/modules/rom_address_control_buf.py @@ -119,12 +119,12 @@ class rom_address_control_buf(design): ppoly_center = poly_right - 0.7 * self.poly_width poly_y = A_out.cy() + + # Placement of gate contacts for NAND cell are different in gf180 which requires tech-specific placement. if OPTS.tech_name == "gf180mcu": poly_y = vdd_rail.cy() + 0.5 * drc("minwidth_tx") * 3 + self.poly_extend_active ppoly_center = A_out.cx() + 0.5 * self.interconnect_width + 0.5 * self.poly_width - else: - ppoly_center = poly_right - 0.7 * self.poly_width - poly_y = A_out.cy() + contact_offset = vector(ppoly_center, clk2_pin.cy()) diff --git a/compiler/modules/rom_decoder.py b/compiler/modules/rom_decoder.py index 8ea798a6..7d6dd928 100644 --- a/compiler/modules/rom_decoder.py +++ b/compiler/modules/rom_decoder.py @@ -18,7 +18,7 @@ class rom_decoder(design): # array gets rotated 90deg so rows/cols switch if "li" in layer: self.output_layer = "m1" - self.inv_route_layer = "m2" + self.inv_route_layer = "m1" else: self.output_layer = "m1" self.inv_route_layer = "m3" @@ -239,6 +239,15 @@ class rom_decoder(design): self.add_via_stack_center(offset=addr_bar_pin.center(), from_layer=addr_bar_pin.layer, to_layer=self.inv_route_layer) + + self.add_via_stack_center(offset=addr_out_pin.center(), + from_layer=addr_out_pin.layer, + to_layer=self.inv_route_layer) + + self.add_via_stack_center(offset=addr_bar_out_pin.center(), + from_layer=addr_bar_out_pin.layer, + to_layer=self.inv_route_layer) + self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i)) def route_supplies(self): diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 5801a850..c4019dbf 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -5,7 +5,7 @@ include $(TOP_DIR)/openram.mk ARGS ?= TEST_TECHS ?= scn4m_subm freepdk45 -TECHS ?= scn4m_subm freepdk45 sky130 gf180mcu +TECHS ?= scn4m_subm freepdk45 sky130 TEST_DIR = $(TOP_DIR)/compiler/tests TEST_SRCS = $(sort $(notdir $(wildcard $(TEST_DIR)/*_test.py))) From b453aa23c25c390987bbf0f9b13116bcd836277d Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 30 Oct 2023 17:58:17 -0700 Subject: [PATCH 51/61] fix ptx minwidth calculation for freepdk45 --- compiler/modules/ptx.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py index 995bef1f..bab90514 100644 --- a/compiler/modules/ptx.py +++ b/compiler/modules/ptx.py @@ -223,8 +223,7 @@ class ptx(design): + 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch # Active height is either the transistor width or the wide enough to enclose the active contact - self.active_height = max(self.tx_width, self.active_contact.width + 2 * self.active_enclose_contact) - + self.active_height = max(self.tx_width, drc["minwidth_contact"] + 2 * self.active_enclose_contact) # Poly height must include poly extension over active self.poly_height = self.active_height + 2 * self.poly_extend_active From 26068fd2e119706daacc56b7fe79cb3965cdbce7 Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 30 Oct 2023 20:31:29 -0700 Subject: [PATCH 52/61] more ptx fixes --- compiler/modules/ptx.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py index bab90514..df8f6d45 100644 --- a/compiler/modules/ptx.py +++ b/compiler/modules/ptx.py @@ -223,7 +223,7 @@ class ptx(design): + 2 * self.active_contact_to_gate + self.poly_width + (self.mults - 1) * self.poly_pitch # Active height is either the transistor width or the wide enough to enclose the active contact - self.active_height = max(self.tx_width, drc["minwidth_contact"] + 2 * self.active_enclose_contact) + self.active_height = self.tx_width # Poly height must include poly extension over active self.poly_height = self.active_height + 2 * self.poly_extend_active From a45e16bff589e5745f38523f5b9c3e9f2fa7854a Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 30 Oct 2023 21:00:48 -0700 Subject: [PATCH 53/61] re-added rom tests to regression ignore for freepdk45 --- compiler/tests/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index c4019dbf..27417fa5 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -64,12 +64,13 @@ BROKEN_STAMPS = \ %/50_riscv_512b_1rw_func_test.ok \ %/50_riscv_8k_1rw1r_func_test.ok \ %/50_riscv_8k_1rw_func_test.ok \ + freepdk45/04_rom_address_control_buf.ok \ + freepdk45/05_rom_array_test.ok \ freepdk45/06_rom_decoder_test.ok \ freepdk45/07_rom_column_mux_array_test.ok \ freepdk45/08_rom_decoder_buffer_array_test.ok \ freepdk45/08_rom_precharge_array_test.ok \ freepdk45/10_rom_wordline_driver_array_test.ok \ - freepdk45/14_rom_array_test.ok \ freepdk45/16_rom_control_logic_test.ok \ freepdk45/19_rom_bank_test.ok \ scn4m_subm/06_rom_decoder_test.ok \ From d161cc55a5e482926a2ff421ef9765c0bfc8453b Mon Sep 17 00:00:00 2001 From: SWalker Date: Mon, 30 Oct 2023 22:54:59 -0700 Subject: [PATCH 54/61] fixed missing broken stamp --- compiler/tests/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/tests/Makefile b/compiler/tests/Makefile index 27417fa5..0b1b9de0 100644 --- a/compiler/tests/Makefile +++ b/compiler/tests/Makefile @@ -64,7 +64,7 @@ BROKEN_STAMPS = \ %/50_riscv_512b_1rw_func_test.ok \ %/50_riscv_8k_1rw1r_func_test.ok \ %/50_riscv_8k_1rw_func_test.ok \ - freepdk45/04_rom_address_control_buf.ok \ + freepdk45/04_rom_address_control_buf_test.ok \ freepdk45/05_rom_array_test.ok \ freepdk45/06_rom_decoder_test.ok \ freepdk45/07_rom_column_mux_array_test.ok \ @@ -73,6 +73,7 @@ BROKEN_STAMPS = \ freepdk45/10_rom_wordline_driver_array_test.ok \ freepdk45/16_rom_control_logic_test.ok \ freepdk45/19_rom_bank_test.ok \ + scn4m_subm/04_rom_address_control_buf_test.ok \ scn4m_subm/06_rom_decoder_test.ok \ scn4m_subm/07_rom_column_mux_array_test.ok \ scn4m_subm/08_rom_decoder_buffer_array_test.ok \ From ce1861f34260e2cccab212830c2e2f58bd80cb8e Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 31 Oct 2023 23:23:57 -0700 Subject: [PATCH 55/61] proper output rom bank output layer --- compiler/modules/rom_bank.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/modules/rom_bank.py b/compiler/modules/rom_bank.py index 56a24740..45a7ad81 100644 --- a/compiler/modules/rom_bank.py +++ b/compiler/modules/rom_bank.py @@ -427,7 +427,11 @@ class rom_bank(design,rom_verilog): inv_out_pins = [self.bitline_inv_inst.get_pin("out_{}".format(bl)) for bl in range(self.cols)] mux_pins = [self.mux_inst.get_pin("bl_{}".format(bl)) for bl in range(self.cols)] - self.connect_col_pins(self.route_stack[2], array_out_pins + inv_in_pins, round=True, directions="nonpref") + if "li" in layer: + output_layer = "m1" + else: + output_layer = "m3" + self.connect_col_pins(output_layer, array_out_pins + inv_in_pins, round=True, directions="nonpref") self.connect_col_pins(self.interconnect_layer, inv_out_pins + mux_pins, round=True, directions="nonpref") def route_output_buffers(self): From fc1a9a9a2bcf7b41a63868eec9c09f9f2aa53050 Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 7 Nov 2023 00:56:16 -0800 Subject: [PATCH 56/61] revert change to Openpdks commit --- Makefile | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 6c482b7c..7d9a9740 100644 --- a/Makefile +++ b/Makefile @@ -18,8 +18,8 @@ SRAM_LIB_GIT_COMMIT ?= dd64256961317205343a3fd446908b42bafba388 # Open PDKs OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git -# OPEN_PDKS_GIT_COMMIT ?= 1.0.311 -OPEN_PDKS_GIT_COMMIT ?= 1.0.395 +OPEN_PDKS_GIT_COMMIT ?= 1.0.311 +# OPEN_PDKS_GIT_COMMIT ?= 1.0.395 #OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608 SKY130_PDK ?= $(PDK_ROOT)/sky130A GF180_PDK ?= $(PDK_ROOT)/gf180 @@ -151,10 +151,14 @@ install: $(SRAM_LIB_DIR) @make $(INSTALL_DIRS) .PHONY: install -pdk: $(GF180_PDK) $(SKY130_PDK) +pdk: $(SKY130_PDK) @true .PHONY: pdk +gf180-pdk: $(GF180_PDK) + @true +.PHONY: gf180-pdk + $(INSTALL_BASE)/gds_lib: $(GDS_FILES) @echo @echo "Setting up GDS cell library for OpenRAM." From 6e2dadeff56c3bcc66e4ecd436349180346d7c61 Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 7 Nov 2023 01:00:44 -0800 Subject: [PATCH 57/61] added some documentation for GF180 usage --- Makefile | 1 + docs/source/basic_setup.md | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 7d9a9740..fa6a450b 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ SRAM_LIB_GIT_COMMIT ?= dd64256961317205343a3fd446908b42bafba388 OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git OPEN_PDKS_GIT_COMMIT ?= 1.0.311 +# Uncomment this for gf180 development # OPEN_PDKS_GIT_COMMIT ?= 1.0.395 #OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608 SKY130_PDK ?= $(PDK_ROOT)/sky130A diff --git a/docs/source/basic_setup.md b/docs/source/basic_setup.md index af73ae55..f238dbc3 100644 --- a/docs/source/basic_setup.md +++ b/docs/source/basic_setup.md @@ -139,7 +139,9 @@ make install You can also run these from the package installation directory if you have the OpenRAM library. +## GF180 Setup +OpenRAM currently **does not** support gf180mcu for SRAM generation. However ROM generation for gf180mcu is supported as an experimental feature. To set up gf180mcu, first change ```OPEN_PDKS_GIT_COMMIT``` in ```OpenRAM/Makefile``` to version 1.0.395. Then follow the setup instructions for Sky130 but run ```make gf180-pdk``` instead of ```make pdk```. [SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf [FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents From b9570b8ddf9ac2150dde06ccad3aac25e6070ca1 Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 7 Nov 2023 01:01:05 -0800 Subject: [PATCH 58/61] removed gf180 specific code from ptx --- compiler/modules/ptx.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/compiler/modules/ptx.py b/compiler/modules/ptx.py index df8f6d45..5645d3d7 100644 --- a/compiler/modules/ptx.py +++ b/compiler/modules/ptx.py @@ -130,7 +130,6 @@ class ptx(design): area_sd = 2.5 * self.poly_width * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width - # self.channel_length = drc("minlength_channel") if OPTS.tech_name != "gf180mcu" else drc("minlength_channel_" + self.tx_type) self.channel_length = drc("minlength_channel") if cell_props.ptx.model_is_subckt: # sky130 @@ -199,9 +198,6 @@ class ptx(design): directions=("V", "V"), dimensions=(1, self.num_contacts)) - if OPTS.tech_name == "gf180mcu": - self.poly_width = self.channel_length - # This is the extra poly spacing due to the poly contact to poly contact pitch # of contacted gates extra_poly_contact_width = self.poly_contact.width - self.poly_width From d59a60eaf3fe6ca8687e39f10f8c9488267cfe4b Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 7 Nov 2023 01:18:21 -0800 Subject: [PATCH 59/61] Update gitignore for gf180 --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 07af627d..bf299e04 100644 --- a/.gitignore +++ b/.gitignore @@ -13,6 +13,7 @@ outputs technology/freepdk45/ncsu_basekit technology/sky130/*_lib technology/sky130/tech/.magicrc +technology/gf180mcu/*_lib .idea compiler/tests/results/ open_pdks/ From 6bd437cfa8efd8e3d8d8232a8da77f07ab3fc8e6 Mon Sep 17 00:00:00 2001 From: SWalker Date: Tue, 7 Nov 2023 14:27:11 -0800 Subject: [PATCH 60/61] Fixed bug that made metal-metal vias think they were well contacts --- compiler/base/contact.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index ea7280a1..7ca08d7d 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -41,7 +41,7 @@ class contact(hierarchy_design): self.add_comment("implant type: {}\n".format(implant_type)) self.add_comment("well_type: {}\n".format(well_type)) - self.is_well_contact = implant_type == well_type + self.is_well_contact = (implant_type == well_type) and implant_type is not None # If we have a special tap layer, use it self.layer_stack = layer_stack From e73ff401fb743cf44417929171314a37fd6d51c6 Mon Sep 17 00:00:00 2001 From: vlsida-bot Date: Wed, 8 Nov 2023 03:28:12 +0000 Subject: [PATCH 61/61] Bump version: 1.2.41 -> 1.2.42 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 50e400b7..8d4450b7 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.2.41 +1.2.42