diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py
deleted file mode 100755
index 1386b2cc..00000000
--- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/usr/bin/env python3
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
-# All rights reserved.
-#
-import sys, os
-import unittest
-from testutils import *
-
-import openram
-from openram import debug
-from openram.sram_factory import factory
-from openram import OPTS
-
-
-class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test):
-
-    def runTest(self):
-        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        openram.init_openram(config_file, is_unit_test=True)
-
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
-        OPTS.num_w_ports = 0
-        openram.setup_bitcell()
-
-        debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column")
-        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0])
-        self.local_check(a)
-
-        openram.end_openram()
-
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = openram.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py
deleted file mode 100755
index 6d3a73c5..00000000
--- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/usr/bin/env python3
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
-# All rights reserved.
-#
-import sys, os
-import unittest
-from testutils import *
-
-import openram
-from openram import debug
-from openram.sram_factory import factory
-from openram import OPTS
-
-
-class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
-
-    def runTest(self):
-        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        openram.init_openram(config_file, is_unit_test=True)
-
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 0
-        openram.setup_bitcell()
-
-        debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
-        self.local_check(a)
-
-        openram.end_openram()
-
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = openram.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py
deleted file mode 100755
index b8427d82..00000000
--- a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/usr/bin/env python3
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
-# All rights reserved.
-#
-import sys, os
-import unittest
-from testutils import *
-
-import openram
-from openram import debug
-from openram.sram_factory import factory
-from openram import OPTS
-
-
-class local_bitcell_array_rightrbl_1rw_test(openram_test):
-
-    def runTest(self):
-        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        openram.init_openram(config_file, is_unit_test=True)
-
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
-        OPTS.num_w_ports = 0
-        openram.setup_bitcell()
-
-        debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with right replica column")
-        a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0])
-        self.local_check(a)
-
-        openram.end_openram()
-
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = openram.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main(testRunner=debugTestRunner())