From ee9aad1b21605d45d795e8df6d1d498bd59bce08 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 16 Nov 2018 08:26:09 -0800 Subject: [PATCH] Errors in contributors. --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 4d342362..03b7213f 100644 --- a/README.md +++ b/README.md @@ -181,7 +181,7 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect. - [James Stine] from [VLSIARCH] co-founded the project. - Hunter Nichols maintains and updates the timing characterization. -- Michael Grims created and maintains the multiport netlist code. +- Michael Grimes created and maintains the multiport netlist code. - Jennifer Sowash is creating the OpenRAM IP library. - Jesse Cirimelli-Low created the datasheet generation. - Samira Ataei created early multi-bank layouts and control logic. @@ -190,6 +190,8 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE). - Brian Chen created early prototypes of the timing characterizer. - Jeff Butera created early prototypes of the bank layout. +If I forgot to add you, please let me know! + * * * [Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg