From 85955ce29824d555bb7096f36d13bdbc0396c532 Mon Sep 17 00:00:00 2001 From: biarmic Date: Fri, 30 Jul 2021 12:22:55 +0300 Subject: [PATCH 1/2] Fix addr flop in Verilog --- compiler/base/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 205baeb7..efd19e9f 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -153,7 +153,7 @@ class verilog: self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port)) if self.num_spare_cols: self.vf.write(" spare_wen{0}_reg = spare_wen{0};\n".format(port)) - self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) + self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) if port in self.read_ports: self.add_write_read_checks(port) From e9b370bf21c2fe1bb6ed974f41a2a65a2ca5e8e8 Mon Sep 17 00:00:00 2001 From: erendo Date: Sun, 29 Aug 2021 00:31:32 +0300 Subject: [PATCH 2/2] Fix write masks in Verilog --- compiler/base/verilog.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index efd19e9f..9cfd7d7c 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -190,15 +190,15 @@ class verilog: self.vf.write(" input csb{0}; // active low chip select\n".format(port)) if port in self.readwrite_ports: self.vf.write(" input web{0}; // active low write control\n".format(port)) + + self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port)) + if port in self.write_ports: if self.write_size: self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port)) if self.num_spare_cols == 1: self.vf.write(" input spare_wen{0}; // spare mask\n".format(port)) elif self.num_spare_cols > 1: self.vf.write(" input [{1}:0] spare_wen{0}; // spare mask\n".format(port, self.num_spare_cols-1)) - - self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port)) - if port in self.write_ports: self.vf.write(" input [DATA_WIDTH-1:0] din{0};\n".format(port)) if port in self.read_ports: self.vf.write(" output [DATA_WIDTH-1:0] dout{0};\n".format(port))